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    Lab 3

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    NOOR UR AIN ZAFAR
    This document contains code for a module that implements basic logic gates and a test module to simulate it, the cct module defines logic gates that feed into an output XOR gate and the test module applies input patterns to test it.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Lab 3

    Uploaded by

    NOOR UR AIN ZAFAR
    17 views1 page
    This document contains code for a module that implements basic logic gates and a test module to simulate it, the cct module defines logic gates that feed into an output XOR gate and the test module applies input patterns to test it.

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    lab3

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    This document contains code for a module that implements basic logic gates and a test module to simulate it, the cct module defines logic gates that feed into an output XOR gate and the test module applies input patterns to test it.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    17 views1 page

    Lab 3

    Uploaded by

    NOOR UR AIN ZAFAR
    This document contains code for a module that implements basic logic gates and a test module to simulate it, the cct module defines logic gates that feed into an output XOR gate and the test module applies input patterns to test it.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 1

    module cct(out,A,B);

    input A,B;
    output out;
    wire w1,w2,w3,w4;
    and a1(w1,A,B);
    nand a2(w2,A,B);
    not a3(w3,A);
    nor a4(w4,w1,w2);
    xor a5(out, w3,w4);
    endmodule
    module test_cct;
    reg a,b;
    wire out;
    cct c1(out,a,b);
    initial
    begin
    a=1'b0; b=1'b0;
    #50 a=1'b0; b=1'b1;
    #50 a=1'b1; b=1'b0;
    #50 a=1'b1; b=1'b1;
    #50 a=1'b1; b=1'b1;
    end
    endmodule

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