Addc Lab

bcd
module bcd_tb();
reg clk,rst;
wire [3:0]count;
bcd dut(clk,rst,count);
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
rst=1'b1;
#10 rst=1'b0;
#200 $finish;
end
endmodule
cla
module cla_tb();
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire cout;
cla dut(a,b,cin,sum,cout);
initial
begin
a=4'b0010;b=4'b0001;cin=1'b0;
#10 a=4'b1010;b=4'b0101;cin=1'b0;
#10 a=4'b1010;b=4'b1111;cin=1'b0;
#10 a=4'b1111;b=4'b1111;cin=1'b0;
end
endmodule
counter
module counter_tb();
reg rst,clk;
wire [3:0]count;
counterdown dut(rst,clk,count);
initial
clk=1'b1;
always
#5 clk=~clk;
initial
begin
rst=1'b1;
#10 rst=1'b0;
#200 $finish;
end
endmodule
decoder 24
module decoder24_tb();
reg [1:0]i;
wire [3:0]y ;
decoder24 DUT(i,y);
initial
begin
#10 i=2'b00;
#10 i=2'b01;
#10 i=2'b10;
#10 i=2'b11;
end
endmodule
demux 14
module demux14_tb();
reg [0:0]i ;
reg [1:0]s;
wire [3:0]y;
demux14 DUT(i,s,y);
initial
begin
i=1'b1;
#10 s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
end
endmodule
d flip flop
module dflipflop_tb();
reg clk,rst,din;
wire q;
dflipflop dut(clk,rst,din,q);
initial
begin
clk=1'b0;
end
always
#5
clk=~clk;
initial
begin
rst=1'b1;
din=1'b0;
#10 rst=1'b0;
din=1'b1;
end
encoder 83
module encoder83_tb();
reg en;
reg [7:0]d;
wire [2:0]b;
encoder83 DUT(en,d,b);
initial
begin
en=1'b0;
#10 d=8'b00000001;
#10 d=8'b00000010;
#10 d=8'b00000100;
#10 d=8'b00001000;
#10 d=8'b00010000;
#10 d=8'b00100000;
#10 d=8'b01000000;
#10 d=8'b10000000;
end
endmodule
encoder 83 pri
module encoder83priority_tb();
reg en;
reg [7:0]d;
wire [2:0]b;
encoder83priority DUT(en,d,b);
initial
begin
en=1'b0;
#10 d=8'b00000001;
#10 d=8'b00000011;
#10 d=8'b00000100;
#10 d=8'b00001010;
#10 d=8'b00010110;
#10 d=8'b00110100;
#10 d=8'b01010110;
#10 d=8'b10101010;
end
endmodule
fuladder
module fulladder_tb();
reg a,b,cin;
wire sum,carry;
fulladder dut(a,b,cin,sum,carry);
initial
begin
a=1'b0;b=1'b0;cin=1'b0;
#10 a=1'b0;b=1'b0;cin=1'b1;
#10 a=1'b0;b=1'b1;cin=1'b0;
end
endmodule
full adder gate

module fulladdergate_tb();
reg a,b,cin;
wire sum,c;
fulladdergate dut(sum,c,a,b,cin);
initial
begin
a=1'b0;b=1'b0;cin=1'b0;
#10 a=1'b0;b=1'b1;cin=1'b0;
#10 a=1'b0;b=1'b1;cin=1'b1;
#10 a=1'b1;b=1'b1;cin=1'b1;
end
endmodule
half adder
module halfadder_tb1();
reg a,b;
wire sum,carry;
halfadder1 dut(sum,carry,a,b);
initial
begin
a=1'b1;b=1'b0;
#10 a=1'b0;b=1'b0;
#10 a=1'b1;b=1'b1;
end
endmodule
jk
module jkflipflop_tb();
reg clk,reset,preset;
reg[1:0]jk;
wire q;
jkflipflop dut(clk,reset,preset,jk,q);
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
reset=1'b1;
#10 reset=1'b0;
#10 preset=1'b1;
#10 preset=1'b0;
#10 jk=2'b00;
#20 jk=2'b01;
#20 jk=2'b10;
#20 jk=2'b11;
end
endmodule
jhonson
module johnsoncounter_tb();
reg clk,rst;
wire [3:0]out;
johnsoncounter dut (.out(out),.rst(rst), .clk(clk));
always
#5clk=~clk;
initial begin
rst=1'b1;
clk=1'b0;
#20 rst=1'b0;
end
initial
begin
$monitor ($time,"clk+%b,out=%b,rst=%b",clk,out,rst);
#105 $stop;
end
endmodule
mux 81
module mux81_tb();
reg [7:0]i;
reg [2:0]s;
wire y;
mux81 DUT(i,s,y);
initial
begin
#10 i=8'b00000001;
#10 s=3'b100;
#10 i=8'b00101110;
#10 s=3'b111;
end
endmodule
rca
module rca_tb();
wire [3:0]sum;
wire cout;
reg [3:0]a,b;
reg cin ;
rca dut(sum,cout,a,b,cin);
initial
begin
a=4'b0010;b=4'b0001;cin=1'b0;
#10 a=4'b1010;b=4'b0101;cin=1'b0;
#10 a=4'b1010;b=4'b1111;cin=1'b0;
#10 a=4'b1111;b=4'b1111;cin=1'b0;
end
endmodule
tflipflop
module tflipflop_tb();
reg clk,reset,preset,t;
wire q;
tflipflop dut(clk,reset,preset,t,q);
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
reset=1'b1;
#10 reset=1'b0;
#10 preset=1'b1;
#10 preset=1'b0;
#20 t=1'b0;
#20 t=1'b1;
end
endmodule
universal shifter
module universalshiftregister_tb();
reg [3:0]d;
reg sdl,sdr,clk,clr;
reg[1:0]s;
wire [3:0]q;
universalshiftregister dut(clk,clr,d,sdl,sdr,s,q);
initial
begin
clk=1'b0;
end
always
#10 clk=~clk;
initial begin
clr=1;
sdl=1'b1;
sdr=1'b1;
s=2'b11;
d=4'b1010;
#20 s=2'b01;
#20 s=2'b10;
#20 s=2'b00;
end
endmodule
counter
module counter(
input rst,
input clk,
output reg [3:0]count
);
always@(posedge clk)
if(rst)
count<=4'b0000;
else
count<=count+4'b0001;
endmodule
VERILOG CODE
module fulladder(A,B,cin,Sum,Carry);
input A;
input B;
input cin;
output Sum;
output Carry;
assign Sum = A^B^cin;
assign Carry = (A&B)|(A&cin)|(B&cin); endmodule
For Half Adder
module half_adder( output Sum,Carry, input A,B );
xor(Sum,A,B);
and(Carry,A,B);
endmodule
For Full Adder

module full_adder( output Sum,Cout, input A,B,Cin );
wire s1,c1,c2;
half_adder ha1(s1,c1,A,B);
half_adder ha2(Sum,c2,s1,Cin);
or or1(Cout,c1,c2);
endmodule
For 4-bit Ripple Carry Adder module ripple_adder_4bit(output [3:0] Sum, output Cout, input
[3:0] A,B, input Cin ); wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin), FA2(Sum[1],c2,A[1],B[1],c1),
FA3(Sum[2],c3,A[2],B[2],c2), FA4(Sum[3],Cout,A[3],B[3],c3); endmodule
module carry_look_adder (input [3:0] a, b, input cin, output [3:0] sum, output cout ); wire
g0,p0,g1,p1,g2,p2,g3,p3;
wire c1,c2,c3;
assign g0 = a[0] & b[0];
assign p0 = a[0] ^ b[0];
assign sum[0] = a[0] ^ b[0] ^ cin;
assign c1 = g0 | (p0 & cin);
assign g1 = a[1] & b[1];
assign p1 = a[1] ^ b[1];
assign sum[1] = a[1] ^ b[1] ^ c1;
assign c2 = g1 | (p1 & c1);
assign g2 = a[2] & b[2];
assign p2 = a[2] ^ b[2];
assign sum[2] = a[2] ^ b[2] ^ c2;
assign c3 = g2 | (p2 & c2);
assign g3 = a[3] & b[3];
assign p3 = a[3] ^ b[3];
assign sum[3] = a[3] ^ b[3] ^ c3;
assign cout = g3 | (p3 & c3);
endmodule
module mux81(i, s, y);

input [7:0] i;
input [2:0] s;
output reg y;
always @ ( s or i )
begin
case (s)
3' b 000: y = i [0];
3' b 001: y = i [1];
3' b 010: y = i [2];
3' b 011: y = i [3];
3' b 100: y = i [4];
3' b 101: y = i [5];
3' b 110: y = i [6];
3' b 111: y = i [7];
default: y=1’b Z;
endcase
end
endmodule
module demux14(i, s, y);

input [0:0] i;
input [1:0] s;
output reg [3:0] y;
always@ (s ,i)
begin
y = 4'b0000;
case (s)
2'b00:y[0] = i;
2'b01:y[1] = i;
2'b10:y[2] = i;
2'b11:y[3] = i;
default: y=4’b0000;
endcase
end
endmodule
module decoder24(i, y);

input [1:0]i;
output [3:0]y;
reg [3:0]y;
always@(i)
begin
case (i)
2'b 00 : y = 4'b 0001;
2'b 01 : y = 4'b 0010;
2'b 10 : y = 4'b 0100;
2'b 11 : y = 4'b 1000;
default: y=4’b0000;
endcase
end
endmodule
module enc83(En,d, b);

input En;
input [7:0] d;
output [2:0] b;
reg [2:0]b;
always@ (d, En)
begin
if(En) b = 3'b000;
else
case(d)
8'b00000001: b = 3'b000;
8'b00000010: b= 3'b001;
8'b00000100: b = 3'b010;
8'b00001000: b = 3'b011;
8'b00010000: b = 3'b100;
8'b00100000: b = 3'b101;
8'b01000000: b = 3'b110;
8'b10000000: b = 3'b111;
default: b = 3'b ZZZ;
endcase
end
endmodule
module penc83(en,d, b);

input en;
input [7:0] d;
output [2:0] b;
reg [2:0] b;
always@ (d , en)
if(en) b=3’d0;
else if(d[7]) b = 3'd7;
else if (d[6]) b= 3’d6;
else if (d[5]) b= 3’d5;
else if (d[4]) b= 3’d4;
else if (d[3]) b= 3’d3;
else if (d[2]) b= 3’d2;
else if (d[1]) b= 3’d1;
else b= 3’d0;
endmodule
module jkflop( input clk, input reset, input [1:0] jk, output reg Q );
always @ (negedge clk)
if(reset) Q<=1'b0;
else if (preset) Q<=1'b1;
else
case (jk)
2'b00: Q<=Q;
2'b01: Q<=1'b0;
2'b10: Q<=1'b1;
2'b11: Q<=~Q;
default: Q<=1'bZ;
endcase
endmodule
module D_ff(output Q, input clk,rst,din); reg Q;

always @(posedge clk or posedge rst) begin
if(rst) Q <= 1'b0;
else Q <= din;
end
endmodule
module counter_behav ( count,rst,clk); input rst, clk;

output reg [3:0] count;
always @(posedge clk)
if (reset) count <= 4'b0000;
else count <= count + 4'b0001;
endmodule
module bcd_count(clk, rst);
input clk;,
input rst;
output reg[3:0] count;
always @ (posedge clk or posedge rst) begin
if(rst) count = 4'b0000;
else if (count ==4’b1001) count=4’b0000; else
count = count+1;
end
endmodule

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bcd

full adder gate

For Full Adder

module mux81(i, s, y);

module demux14(i, s, y);

module decoder24(i, y);

module enc83(En,d, b);

module penc83(en,d, b);

module D_ff(output Q, input clk,rst,din); reg Q;

module counter_behav ( count,rst,clk); input rst, clk;

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