Varilog Lab#1 AO221 Program
Varilog Lab#1 AO221 Program
Varilog Lab#1 AO221 Program
AO221 Program:
module AO221(f,a,b,c,d,e);
input a,b,c,d,e;
output f;
wire w1,w2;
and g1(w1,a,b);
and g2(w2,c,d);
or g3(w1,w2);
endmodule
module stimulus();
wire W1,W2;
reg A,B,C,D,E;
initial begin
end
endmodule
Output
Varilog lab#2
input a,b;
output c,s;
xor g1 (s,a,b);
and g2 (c,a,b);
endmodule
reg A,B;
wire C,S;
initial begin
A=1'b0; //here 1 is for assigning single bit in registor and 0 is the value
B=1'b1; //here 1 is for assigning single bit in registor and 1 is the value
end
endmodule
\Output:
input a,b,cin;
xor g1 (w1,a,b);
and g2 (w2,a,b);
and g3 (w3,cin,w1);
xor g4 (s,w1,cin);
or (cout,w2,w3);
endmodule
reg A,B,Cin;
wire Cout,S,W1,W2,W3;
initial begin
A=1'b0; //here 1 is for assigning single bit in registor and 0 is the value
B=1'b1; //here 1 is for assigning single bit in registor and 1 is the value
Cin=1'b1;
end
endmodule
Output:
With 4 bits
module Full_adder (s,cout,cin,a,b);
input a,b,cin;
xor g1 (w1,a,b);
and g2 (w2,a,b);
and g3 (w3,cin,w1);
xor g4 (s,w1,cin);
or (cout,w2,w3);
endmodule
reg Cin;
wire cout;
initial begin
A=4'b0011; //here 1 is for assigning single bit in registor and 0 is the value
B=4'b1111; //here 1 is for assigning single bit in registor and 1 is the value
Cin=1'b1;
end
endmodule
output: