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    Ddcolabsub 1

    Uploaded by

    asmrquotes24

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Ddcolabsub 1

    Uploaded by

    asmrquotes24
    2 views8 pages

    Original Title

    DDCOLABSUB-1

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    2 views8 pages

    Ddcolabsub 1

    Uploaded by

    asmrquotes24

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    Name : Vikas K S

    USN : PES1202402891

    Section : j

    #And

    #cir1.v

    module and2(a,b,c);

    input a,b;

    output c;

    assign c=a&b;

    endmodule

    module or2(a,b,c);

    input a,b;

    output c;

    assign c=a|b;

    endmodule

    module circuit1(a,b,c,d);

    input a,b,c;

    output d;

    wire x ;

    and2 and2_1(a,b,x);

    or2 or2_1(x,c,d);

    endmodule

    #cir1_tb.v

    module tb;

    reg a,b,c;
    wire d ;

    circuit1 circuit1_1(a,b,c,d);

    initial begin $dumpfile ("not5dump.vcd");

    $dumpvars(0,tb);

    end

    initial begin

    #0 a=0;b=0;c=0;

    #5 a=0;b=0;c=1;

    #5 a=0;b=1;c=0;

    #5 a=0;b=1;c=1;

    #5 a=1;b=0;c=0;

    #5 a=1;b=0;c=1;

    end

    endmodule
    #OR

    #2cir.v

    module and2(a,b,c);

    input a,b;

    output c;

    assign c=a&b;

    endmodule

    module or2(a,b,c);

    input a,b;

    output c;

    assign c=a|b;

    endmodule

    module circuit1(a,b,c,d);

    input a,b,c;
    output d;

    wire x;

    and2 and2_1(a,b,x);

    or2 or2_1(x,c,d);

    endmodule

    #2cir_tb.v

    module tb;

    reg a,b,c;

    wire d ;

    circuit1 circuit1_1(a,b,c,d);

    initial begin $dumpfile ("not3dump.vcd");

    $dumpvars(0,tb);

    end

    initial begin

    #0 a=0;b=0;c=0;

    #5 a=0;b=0;c=1;

    #5 a=0;b=1;c=0;

    #5 a=0;b=1;c=1;

    #5 a=1;b=0;c=0;

    #5 a=1;b=0;c=1;

    end

    endmodule
    #cir3.v

    module and2(a,b,c);

    input a,b;

    output c;
    assign c=a&b;

    endmodule

    module or2(a,b,c);

    input a,b;

    output c;

    assign c=a|b;

    endmodule

    module circuit1(a,b,c,d);

    input a,b,c ;

    output d;

    wire x ;

    and2 and2_1(a,b,x);

    or2 or2_1(x,c,d);

    endmodule

    module circuit2(a2,b2,c2,z);

    input a2,b2,c2;

    output z;

    circuit1 circuit1_1(c2,b2,a2,x);

    circuit1 circuit2(b2,a2,x,z);

    endmodule

    #cir3_tb.v

    module tb;

    reg a,b,c;

    wire d ;

    circuit1 circuit1_1(a,b,c,d);
    initial begin $dumpfile ("not6dump.vcd");

    $dumpvars(0,tb);

    end

    initial begin

    #0 a=0;b=0;c=0;

    #5 a=0;b=0;c=1;

    #5 a=0;b=1;c=0;

    #5 a=0;b=1;c=1;

    #5 a=1;b=0;c=0;

    #5 a=1;b=0;c=1;

    #5 a=1;b=1;c=0;

    #5 a=1;b=1;c=1;

    #5 a=0;b=0;c=0;

    end

    endmodule

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