Verilog code for Basic gates and Test bench

module nandg (c,a,b)

input a;

input b;

output c;

assign c=~(a & b);

end module

Test Bench
module nandg_tst_v;

reg a;

reg b;

wire c;

nandg uut (

.a(a),

.b(b),

.c(c)

);

initial

begin

a = 0;b = 0;

#100 a = 0;

b = 1;

#100 a = 1;

b = 0;

#100 a = 1;

b = 1;

end module
NOT GATE
module NOT_Gate(

input A,

output Y);

assign Y = ~A; // Y is the opposite of A

endmodule

TEST BENCH
module NOT_Gate_tb;

reg A;

wire Y;

NOT_Gate inst(.A(A), .Y(Y));

initial

begin

$dumpfile("dump.vcd");

$dumpvars;

#1000 $finish;

end

initial begin

A='b0;

#50 $finish;

end

always #5 A=~A;

Endmodule
OR GATE
module orgate (a, b, y);

input a, b;

output y;

assign y = a | b;

endmodule

TEST BENCH
module orgate_tb;

wire y;

reg a, b;

orgate my_gate( .a(a), .b(b), .y(y) );

initial

begin

$dumpfile("dump.vcd");

$dumpvars(1);

$monitor(a, b, y);

#1 a = 1'b0; b = 0'b0;

#2 a = 1'b0; b = 1'b1;

#3 a = 1'b1; b = 1'b0;

#4 a = 1'b1; b = 1'b1;

end

endmodule

AND GATE

module gate(a,b,y);

input a,b;
 output y;

assign y=a&b;

endmodule

TEST BENCH
module testbench_gate;

reg a,b;

wire y;

gate DUT(a,b,y);

initial

begin

$dumpfile("gate.vcd);

$dumpvars(1,testbench_gate);

$mointor(a,b,y);

a=0;b=0;c=0;

#5 a=1;b=0;c=0;

#5 a=0;b=1;c=1;

#5 a=0; b=0; c=1;

#5 a=1;b=1;c=1;

#5 $finish;

end

endmodule

NAND GATE
module gate(a,b,y);

input a,b;

output y;

assign y=~(a|b);
endmodule

TEST BENCH
module gate_testbench;

reg a,b;

wire y;

gate DUT(a,b,y);

initial

begin

$dumpfile("gate.vcd");

$dumpvars(1,gate_testbench);

$monitor(a,b,y);

a=0;b=0;

#5 a=1; b=0;

#5 a=0; b=0;

#5 a=1; b=1;

#5 a=0; b=0;

#5 $finish;

end

endmodule
ALL GATES STRUCTURAL DESCRIPTION USING PRIMITIVE
GATES
module example(a,b,c,d,e,f,y);

input a,b,c,d,e,f;

output y;

wire t1,t2,t3,y;

nand #1 G1 (t1,a,b);

and #2 G2 (t2,c,~b,d);

nor #1 G3 (t3,e,f);

nand #1 G4 (y,t1,t2,t3);

endmodule

TEST BENCH
module example_testbench;

reg a,b,c,d,e,f;

wire y;

example DUT(a,b,c,d,e,f,y);

initial

begin

$dumpfile ("example.vcd");

$dumpvars (1,example_testbench);
$monitor($time,"a=%b,b=%b,c=%b,d=%b,e=%b,f=%b,y=%b",a,b,c,d,e,f,y);

a=0;b=0;c=0;d=0;e=0;f=0;

#5 a=1;b=1;c=0;d=1;e=0;f=0;

#5 a=1;b=0;c=1;d=1;e=0;f=0;

#5 a=1;b=1;c=0;d=1;e=0;f=0;

#5 a=1;b=0;c=0;d=1;e=0;f=0;

#5 $finish;

end

endmodule
EX-OR GATE DATA FLOW DESCRIPTION
module example1(a,b,y);

input a,b;

output y;

assign y=(~a&b)|(a&~b);

endmodule

TEST BENCH
module example1_testbench;

reg a,b;

wire y;

example1 DUT(a,b,c); //instantiation

initial

begin

$dumpfile("example1.vcd");

$dumpvars(1,example1_testbench);

$monitor(a,b,y);

a=0;b=0;

#5 a=0; b=1;

#5 a=1; b=0;

#5 a=0; b=0;

#5 a=1; b=1;

#5 a=0; b=1;

$finish;

end

endmodule
STRUCTURAL DESCSRIPTION OF AND GATE
module and_gate(a,b,y);

input a,b;

output y;

wire f;

nand u1(f,a,b);

inv u2(f,y);

endmodule

module inv(a,y);

input a;

output y;

assign y=~a;

endmodule

TEST BENCH
module example1_testbench;

reg a,b;

wire y;

and_gate DUT(a,b,y);

initial

begin

$dumpfile("and_gate.vcd");

$dumpvars(1,example1_testbench);

$monitor(a,b,y);

a=0;b=0;

#5 a=1;b=0;

#5 a=1;b=1;

#5 a=0;b=1;

$finish;
 end

endmodule

FULLADDER DATA FLOW DESCSRIPTION

module fulladder(a,b,c,s,c);

input a,b,c;

output s,c;

assign s=a^b^c;

c=(a&b)|(b&c)|(c&a);

endmodule

TEST BENCH
module fulladder_testbench;

reg a,b,c;

wire s,c;

fulladder DUT(a,b,c,s,c);

initial

begin

$dumpfile("fulladder.vcd");

$dumpvars(1,fulladder_testbench);

$mointor(a,b,c,s,c);

a=0;b=0;c=0;

#5 a=0;b=0;c=1;

#5 a=0;b=1;c=0;

#5 a=1;b=0;c=0;

#5a=1;b=0;c=1;
 #5a=1;b=1;c=1;

$finish;

end

endmodule

STRUCTURAL DESCSRIPTION OF FULLADDER

module fulladder_stru(input a,b,cin, output sum,carryout);

wire w1,w2,w3;

xor u1(sum,a,b,cin);

and u2(w1,a,b);

and u3(w2,b,cin);

and u4(w3,a,cin);

or u5(carryout,w1,w2,w3);

endmodule

TEST BENCH
module test_fulladderstruct;

reg a,b,cin;

wire sum,carryout;

fulladder_stru DUT(a,b,cin,sum,carryout);// instantiate the module to be tested

initial

begin

$dumpfile("fulladder_stru.vcd");

$dumpvars(1,test_fulladderstruct);

$monitor(a,b,cin,sum,carryout);

a=0;b=0;cin=0;

#5 a=0;b=1;cin=0;
 #5 a=0;b=1;cin=1;

#5 a=1;b=0;cin=0;

#5 a=1;b=0;cin=1;

#5 a=1;b=1;cin=0;

#5 a=1;b=1;cin=1;

end

endmodule

HALF ADDER DESCRIPTION USING DATAFLOW DESCRIPTION

(Assignment statement)
module halfadder(input a,b, output sum,carryout);

assign sum=(a^b);

assign carryout=(a&b);

endmodule

Test bench
module test_halfadder;

reg a,b;

wire sum,carryout;

halfadder DUT(a,b,sum,carryout);//instantiate the module to be tested

initial

begin

$dumpfile("halfadder.vcd");

$dumpvars(1,test_halfadder);

$monitor(a,b,sum,carryout);

a=0;b=0;

#5 a=0;b=1;

#5 a=1;b=0;

#5 a=1;b=1;
 end

endmodule

FULL ADDER DESCRIPTION USING DATAFLOW DESCRIPTION

module fulladder_beh(a,b,cin,sum,carryout);

input a,b,cin;

output sum,carryout;

assign#20 sum=(a^b^cin);

assign #10 carryout=(a&b)|(b&cin)|(a&cin);

endmodule

TEST BENCH
module fulladder_testbench;

reg a,b,cin;

wire sum,carryout;

fulladder_beh DUT(a,b,cin,sum,carryout);

initial

begin

$dumpfile("fulladder_beh.vcd");

$dumpvars(1,fulladder_testbench);

$monitor(a,b,cin,sum,carryout);

a=0;b=0;cin=0;

#5 a=0;b=0;cin=1;

#5 a=0;b=1;cin=0;

#5 a=0;b=1;cin=1;

#5 a=1;b=0;cin=0;

#5 a=1;b=0;cin=1;

#5 a=1;b=1;cin=0;
 #5 a=1;b=1;cin=1;

end

endmodule

STRUCTURAL DESRIPTION OF FULLADER USING TWO

HALFADDERS
module Full_Adder (input a, b, c, output cout, sum);

wire w1, w2, w3;

Half_Adder HA1 (a, b, w1, w2);

Half_Adder HA2 (w2, c, w3, sum);

or #2 (cout, w1, w3);

endmodule

module Half_Adder(input a, b, output cout, sum);

and #2 (cout, a, b);

xor #3 (sum, a, b);

endmodule

TEST BENCH
module Test_Full_Adder; // No need for Ports

reg a, b, c; // variables

wire sum, cout; // wires

// Instantiate the module to be tested

Full_Adder DUT (a, b, c, cout, sum);

initial begin // initial block

$dumpfile("Full_Adder.vcd");

$dumpvars(1,Test_Full_Adder);

$monitor(a,b,c,cout,sum);

a=0; b=0; c=0; // at t=0 time units

#20 a=1; b=1; // at t=20 time units

#20 a=0; b=0; c=1; // at t=40 time units

 #20 a=1; c=0; // at t=60 time units

#20 $finish; // at t=80 finish simulation

end // end of initial block

endmodule

STRUCTURAL DESRIPTION OF FULLADER USING TWO

HALFADDERS
module fulladder (input a, b, c, output cout, sum);

wire w1, w2, w3;

Half_Adder HA1 (a, b, w1, w2);

Half_Adder HA2 (w2, c, w3, sum);

or #2 (cout, w1, w3);

// instantiation of half adder

module Half_Adder(input a, b, output cout, sum);

and #2 (cout, a, b);

xor #3 (sum, a, b);

endmodule

TEST BENCH
module Test_Full_Adder; // No need for Ports

reg a,b,c; // variables

wire sum,cout;// wires

fulladder DUT(a,b,c,cout,sum);

initial

begin // initial block

$dumpfile("fulladder.vcd");

$dumpvars(1, Test_Full_Adder);

a=0; b=0; c=0; // at t=0 time units

 #20 a=1; b=1;c=1; // at t=20 time units

#20 a=0; b=0; c=1; // at t=40 time units

#20 a=1; c=0;c=0; // at t=60 time units

#20 $finish; // at t=80 finish simulation

end // end of initial block

endmodule

STRUCTURAL DESCRIPTION OF AND GATE

module struct_gate(input a,b, output y);

wire w;

nand u1(w,a,b);

not u2(y,w);

endmodule

TEST BENCH
module testbench_structgate;

reg a,b;

wire y;

struct_gate DUT(a,b,y);

initial

begin

$dumpfile("struct_gate.vcd");

$dumpvars(1,testbench_structure);

$monitor(a,b,y);

a=0;b=0; //t=0 units

#5 a=1;b=0; //t=5 units

#5 a=0;b=1; //t=10 units

#5 a=1;b=1; //t=15 units

end
endmodule

STRUCTURAL DESRIPTION OF FULLADER USING TWO

HALFADDERS BEHAVIOURAL DESCRIPTION(PROCEDURAL
BLOCK)

module Full_Adder (input a, b, c, output cout, sum);

wire w1, w2, w3;

Half_Adder HA1 (a, b, w1, w2);

Half_Adder HA2 (w2, c, w3, sum);

or #2 (cout, w1, w3);

endmodule

//module Half_Adder(input a, b, output cout, sum);

and #2 (cout, a, b);

xor #3 (sum, a, b);

reg sum,cout;

always@(a,b)

begin

sum=(a^b);

cout=(a&b);

end

endmodule

TEST BENCH

module Test_Full_Adder; // No need for Ports

reg a, b, c; // variables

wire sum, cout; // wires

 Full_Adder FA (a, b, c, cout, sum);

initial begin // initial block

$dumpfile("Full_Adder.vcd");

$dumpvars(1,Test_Full_Adder);

a=0; b=0; c=0; // at t=0 time units

#20 a=1; b=1; // at t=20 time units

#20 a=0; b=0; c=1; // at t=40 time units

#20 a=1; c=0; // at t=60 time units

#20 $finish; // at t=80 finish simulation

end // end of initial block

endmodule

Behavioral description of binary adder

module binary_adder( input a,b,output sum,carry);

assign sum=(a^b);

assign carry=(a&b);

endmodule

structural Description of binary adder

module struct_adder(input a,b,output sum,carry);

and g1(w1,a,b);

and g2(w2,a,b);

or g3(sum,w1,w2);

not g4(a,~a);

not g5(b,~b);

endmodule

module struct_adder(input a,b,output sum,carry);

input a,b;
output sum,carry;

reg sum,carry;

always @(a,b,sum,carry)

begin

sum=(a^b);

carry=(a&b);

end

endmodule

TEST BENCH
module testbench_binaryadder;

reg a,b;

wire sum,carry;

binary_adder DUT(a,b,sum,carry);// instantiation of Module

initial

begin

$dumpfile("binary_adder.vcd");

$dumpvars(1,testbench_binaryadder);

$monitor(a,b,sum,carry);

t=0 a=0; b=0;

#5 a=1; b=0;

#5 a=0; b=1;

#5 a=1; b=1;

end

endmodule

Four BITFULL ADDER VECTOR DECLARATION (ASSIGNMENT

STATEMENT)
module adder4 (S, cout, A, B, cin);

input [3:0] A, B;
input cin;

output [3:0] S;

output cout;

assign {cout,S} = A + B + cin;

endmodule

TEST BENCH FA VECTOR DECLARATION

module testbench_4bitadder;

reg[3:0] a,b;

reg cin;

wire sum,carryout;

adder4 DUT(Sum,carryout,a,b,cin);

initial

begin

$dumpfile("adder4.vcd");

$dumpvars(0,testbench_4bitadder);

$monitor(a,b,cin,sum,carryout);

a=0000; b=0000;cin=0;

#5 a=0000; b=0000;

#5 a=0001; b=0001;

#5 $finish;

end

endmodule

4 bit adder description using concatenation operator

module adder4 (a, b, cin,sum,carryout);

input [3:0] a, b;
input cin;

output [3:0]sum;

output carryout;

assign {carryout,sum} = a + b + cin;

endmodule

Structural description of 4 bit adder using fulladders

module addr4(a,b,cin,sum,carryout);

input [3:0]a,b;

input cin;

output carryout;

output [3:0]c;

output [3:0] sum;

wire c1,c2,c3;

fulladder FA1(a[0],b[0],cin,sum[0],c1);

fulladder FA2(a[1],b[1],c1,sum[1],c2);

fulladder FA3(a[2],b[2],c2,sum[2],c3);

fulladder FA4(a[3],b[3],c3,sum[3],carryout);

endmodule

behavioural description of fulladder

module fulladder(a,b,cin,sum,carryout);

input a,b,cin;

output sum,carryout;

assign sum=(a^b^cin);

assign carryout=(a&b)|(b&cin)|(a&cin);

endmodule

behavioural description of fulladder using behavioural modelling

module fulladder(a,b,cin,sum,carryout);
input a,b,cin;

output reg sum,carryout;

reg carryout,sum;

always @ (a,b,cin)

begin

{sum,carryout}=a+b+cin;

Sum=(a^b^cin);

Carryout=(a&b)|(b&cin)|(a&cin);

end

endmodule

Test BENCH

module testbench_4bitadder;

reg[3:0]a,b;

reg cin;

wire [3:0]sum;

wire carryout;

adder4 DUT(a,b,cin,sum,carryout);// instantiate the adder4 module

initial

begin

$dumpfile("fulladder.vcd");

$dumpvars(0,testbench_4bitadder);

$monitor(a,b,cin,sum,carryout);

a=4'b0000; b=4'b0000;cin=0;

#5 a=4'b0000; b=4'b0001;

#5 a=4'b0010; b=4'b0001;
 #5 a=4'b0101; b=4'b0101;

#5 a=4'b1001; b=4'b0011;

#5 $finish;

end

endmodule

MULTIPLEXER 2:1 USING DATAFLOW DESCRIPTION

module mux2to1 (in, sel, out);

input [1:0] in;

input sel;

output out;

assign out = in[sel];

endmodule

TEST BENCH OF 2:1 MUX

module muxtest;

reg A,B;

reg S;

wire F;

mux2to1 M(A,B,S,F);

initial

begin

$dumpfile ("mux2to1.vcd");

$dumpvars (0,muxtest);

$monitor ($time," A=%b, S=%b, F=%b", A,B,S,F);

A=0;B=0; S=0;

#5 A=1;S=0; B=0;
#5 A=0;S=1; B=1;

#5 $finish;

end

endmodule

4: 1 MUX USING 2:1 MUX(STRUCTURAL DESCRIPTION)

module mux4to1(i0,i1,i2,i3, s0,s1,out);

input i0,i1,i2,i3;

output out;

input s0,s1;

wire W1,W2;

mux2to1 M0(i0,i1,s0,W1);

mux2to1 M1(i2,i3,s0,W2);

mux2to1 M2(W1,W2,s1,out);

endmodule

2:1 MUX BEHAVIOURAL DESCRIPTION

module mux2to1(A,B, sel, out);

input A,B;

input sel;

output out;

//assign out = A&B[sel];

assign out= (sel&A)|(~sel&B);

endmodule

4:1 MUX USING DATAFLOW DESCRIPTION

module mux4to1(i0,i1,i2,i3, s0,s1,out);
input i0,i1,i2,i3;

input s0,s1;

output out;

assign out= (~s0&~s1&i0)|(~s0&s1&i1)|(s0&~s1&i2)|(s0&s1&i3);

endmodule

TEST BENCH
module muxtest;

reg i0,i1,i2,i3;

reg s0,s1;

wire out;

mux4to1 M(i0,i1,i2,i3,s0,s1,out);

initial

begin

$dumpfile ("mux4to1.vcd");

$dumpvars (0,muxtest);

$monitor (i0,i1,i2,i3,s0,s1,out);

#5 i3=0;i2=0; i1=0; i0=1;s0=0;s1=0;

#5 i3=0;i2=0;i1=1; i0=0;s0=0;s1=1;

#5 i3=0;i2=1;i1=0; i0=0; s0=1;s1=0;

#5 i3=1;i2=0; i1=0;i0=0; s0=1;s1=1;

//#5 D=1; A=0;B=0;C=0; s0=1;s1=1;

MUX 4:1 USING 2:1 MUX STRUCTURAL DESCRIPTION

(VECTOR DECLARATION)
module mux4to1 (in, sel, out);

input [3:0] in;

input [1:0] sel;

output out;

wire [1:0] t;

mux2to1 M0 (in[1:0],sel[0],t[0]);

mux2to1 M1 (in[3:2],sel[0],t[1]);

mux2to1 M2 (t,sel[1],out);

endmodule

Test bench
module mux4to1_testbench:

reg [3:0]in;

reg[1:0] sel;

wire out;

mux4to1 DUT(A,S,F);

initial

begin

$dumpfile ("mux4to1.vcd");

$dumpvars (0,muxtest);

$monitor ($time," A=%b, S=%b, F=%b", A,S,F);

#5 A=4'b0001; S=2'b00;

#5 S=2'b01;A=4'b0010;

#5 S=2'b10;A=4'b0100;

#5 S=2'b11;A=4'b1000;

#5 $finish;

end

endmodule