Asdjflkaj SDF

電子學(一) 期中考
(共 10 題、3 頁)
注意事項：
1. 考試時間 13:20~16:20，可提前交卷。
2. 答案須填寫於答案卷並標明題號，交卷時只須繳回答案卷。
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4. 作弊者一律以 0 分計算。
(10%) Q1. An inverting amplifier is designed for a nominal gain of 4 and a gain error of 0.1% using an op
amp that exhibits an output impedance of 2kΩ. If the input impedance of the circuit must be equal
to approximately 2kΩ, calculate the required open-loop gain of the op amp.
Ans 1. (負責助教: 陳奕成)
1
(共 10 題、3 頁)
(10%) Q2. (a) Assuming A0 = ∞, compute the closed-loop gain of the inverting amplifier shown in Fig. Q2.
Verify that the result reduces to expected values if (b) R1 → 0 and (c) R3 → 0.
Fig. Q2
2
(共 10 題、3 頁)
(10%) Q3. The integrator of Fig. Q3 senses an input signal given by Vin = Vp sin ωt. Determine the output
signal amplitude if A0 = ∞.
Fig. Q3
Ans 3. (負責助教: 簡爾彣)
−1 −1 𝑉𝑝
𝑉𝑜𝑢𝑡 = ∫ 𝑉𝑖𝑛 𝑑𝑡 = ∫ 𝑉𝑜 sin 𝜔𝑡 𝑑𝑡 = cos 𝜔𝑡
𝑅1 ×𝐶1 𝑅1 ×𝐶1 𝑅1 ×𝐶1 ×𝜔
𝑉𝑝
Amplitude of output =
𝑅1 × 𝐶1 × 𝜔
3
(共 10 題、3 頁)
(10%) Q4. We wish to design the differentiator of Fig. Q4 for a pole frequency of 1MHz. If the values of R1
and C1 cannot be lower than 1kΩ and 1nF, respectively, compute the required gain of the op amp.
Fig. Q4
𝑉𝑖𝑛 −𝑉𝑥 𝑉𝑥 −𝑉𝑜𝑢𝑡

1 = , −𝐴0 𝑉𝑥 = 𝑉𝑜𝑢𝑡
𝑅1
𝑠𝐶1
𝑉𝑜𝑢𝑡 −𝑠𝐶1 𝑅1
=
𝑉𝑖𝑛 1 𝑠𝑅1 𝐶1
1+ +
𝐴0 𝐴0
𝐴0 + 1
𝑠𝑝 = −
𝐶1 𝑅1
𝐴0 + 1
2𝜋 × 1MHz =
1nF × 1kΩ
𝐴0 = 5.28V/V
4
(共 10 題、3 頁)
(10%) Q5. Beginning with VD,on = 800mV and considering the small-signal resistance for each diode,
calculate the change in Vout if Iin changes from 3 mA to 3.1 mA in the circuit of Fig. Q5. Using
VT = 26mV if needed.
Fig. Q5
Ans 5. (負責助教: 李皓元)
(a) ΔVout = Δi  R1 = 0.1 mA  1 kΩ = 0.1 V
26 mV
(b) rd1 = rd2 = = 8.667 Ω, ΔVout = Δi  (R1 + rd2) = 0.1 mA  8.667 Ω = 100.867 mV
3 mA
(c) ΔVout = Δi  rd2 = 0.1 mA  8.667 Ω = 0.867 mV
𝑉𝐷,𝑜𝑛 𝑉𝑇
(d) ID = Iin - = 2.6 mA, rd2 = = 10 Ω, ΔVout = Δi  (R1 // rd2) = 0.995 mV
𝑅2 𝐼𝐷
5
(共 10 題、3 頁)
(10%) Q6. Assuming Vin = Vp sin ωt, plot the output waveform of the circuit depicted in Fig. Q6 for an initial
condition of +0.5V across C1. Assume Vp = 2V, ω = 1rad/s, VD,on = 800mV, and ignore the small-
signal resistance of diode.
Fig. Q6
Ans 6. (負責助教: 李皓元)
6
(共 10 題、3 頁)
(10%) Q7. Plot the current ﬂowing through R1 in the circuits of Fig. Q7 as a function of Iin. Assume a
constant-voltage diode model with VD,on = 800mV and VB = 2V.
(a) (b)
(c) Fig. Q7
(a) (b)
(c)
7
(共 10 題、3 頁)
(10%) Q8. Suppose in Fig. Q8, the diodes carry a current of 5mA and the load, a current of 20mA. If the
load current increases to 24mA and the diodes absorb the current change, what is the change in
the total voltage across the three diodes? Assume R1 is much greater than the small-signal
resistance of diode. Using VT = 26mV if needed.
Fig. Q8
Ans 8. (負責助教: 陳冠穎)
VT 26 mV
rd = = = 5.2 Ω
ID 5 mA
Iload + ID = 25 mA
When Iload = 24 mA → ID = 1 mA
∆Vout = ∆ID × 3rd = (−4mA) × 3(5.2Ω) = −62.4 mV
8
(共 10 題、3 頁)
(10%) Q9. In the Fig. Q9, what is the minimum allowable value of VDD if M1 must not enter the triode region?
Assume VTH = 0.4V, μnCox = 200μA/V2, and ignore the channel-length modulation.
Fig. Q9
Ans 9. (負責助教: 陳冠穎)
To avoid triode region, VDS ≥ VGS − VTH or VDS ≥ 1 - 0.4 = 0.6 V
1 W
ID1 = μn Cox (VGS − VTH )2
2 L
1 μA 10
= (200 2 ) ( ) 0.62 = 2000 μA = 2 mA
2 V 0.18
By KCL,
VDD − VDS
2 mA =
RD
VDD = 2 × 1 + 0.6 = 2.6 V
9
(共 10 題、3 頁)
(10%) Q10. Assume μnCox = 200μA/V 2 , μpCox = 100μA/V 2 , and VTH = 0.4V for NMOS devices and -0.4V
for PMOS devices. If λ = 0, what value of W/L places M1 at the edge of saturation in Fig. Q10?
Fig. Q10
[End of Midterm Exam]
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電子學(一) 期中考

Ans 1. (負責助教: 陳奕成)

Ans 2. (負責助教: 陳奕成)

Ans 3. (負責助教: 簡爾彣)

Ans 4. (負責助教: 簡爾彣)

𝑉𝑖𝑛 −𝑉𝑥 𝑉𝑥 −𝑉𝑜𝑢𝑡

Ans 5. (負責助教: 李皓元)

(a) ΔVout = Δi  R1 = 0.1 mA  1 kΩ = 0.1 V

(c) ΔVout = Δi  rd2 = 0.1 mA  8.667 Ω = 0.867 mV

Ans 6. (負責助教: 李皓元)

Ans 7. (負責助教: 簡爾彣)

Ans 8. (負責助教: 陳冠穎)

∆Vout = ∆ID × 3rd = (−4mA) × 3(5.2Ω) = −62.4 mV

Ans 9. (負責助教: 陳冠穎)

To avoid triode region, VDS ≥ VGS − VTH or VDS ≥ 1 - 0.4 = 0.6 V

VDD = 2 × 1 + 0.6 = 2.6 V

Ans 10. (負責助教: 陳奕成)

[End of Midterm Exam]

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