iC-TW3 SENSOR SIGNAL CONDITIONER WITH

TEMPERATURE COMPENSATION AND LINE DRIVER

Rev B2, Page 1/26

FEATURES APPLICATIONS
• Fully differential 3-channel signal conditioning • Programmable general purpose
• PGS inputs for differential and single-ended signals sensor interface
• Overall gain of -3 to 57 dB, adjustable in steps of 0.08 dB • Optical position sensors
• Output referred offset range of ±1.2 V, adjustable in steps of • Magnetic position sensors
2 mV • Incremental position sensors
• Signal bandwidth to 1 MHz and in/out latency below 1 µs • Linear scales
• Selectable automatic gain and offset control for encoder
applications
• On-chip or off-chip temperature sensing
• Temperature drift compensation for gain and offset via
programmable look-up-tables PACKAGES
• Short-circuit-proof outputs: 1 Vpp to 100 Ω, 2 Vpp to 1 kΩ
• I2 C interface to restore device setup from serial EEPROM
• Bidirectional 1-wire interface for direct RAM and EEPROM
access
• Optical setup link via 1-wire interface operating a photo receiver
• Single 3.0 V to 5.5 V supply QFN32
• Operating temperature range of -40 to +125 °C 5 mm x 5 mm
RoHS compliant

BLOCK DIAGRAM

Copyright © 2007, 2017 iC-Haus http://www.ichaus.com

iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 2/26

DESCRIPTION

The general purpose sensor signal conditioner For encoder applications an automatic gain and off-
iC-TW3 provides highly accurate non contact trim- set control compensates sensor offset voltages and
ming of three independent sine/cosine sensor signals. stabilizes the output signal level.
The differential output signals can be calibrated to 1
Vpp or to 2 Vpp, alternatively. The direct connection of sine/cosine encoders, MR
sensor bridges or photosensor arrays is possible and
The internal or an external temperature sensor linked supported by a selectable input impedance.
to the chip can influence the gain and offset correction
by arbitrary temperature-dependent compensation pa-
rameters sourced from a look-up table.
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 3/26

PACKAGING INFORMATION

PIN CONFIGURATION QFN32 (5 mm x 5 mm) PIN FUNCTIONS

(top view) No. Name Function
1 PINZ Signal Input Z+
2 NINZ Signal Input Z-
32 31 30 29 28 27 26 25 3 TESTEN Test Mode Enable Input
4 CLK External Clock Input (optional)
1 24 5 NZO Signal Output Z-
2 23 6 ZO Signal Output Z+
7 GNDB Driver Ground
3 22 8 VDDB +3...+5.5 V Driver Supply Voltage
4 <P-CODE> 21 9 NBO Signal Output B-
5 20 10 BO Signal Output B+
<A-CODE>
6 19 11 GND Digital Ground
7 <D-CODE> 18 12 SCL I2C Interface, clock line
13 SDA I2C interface, data line
8 17 14 VDD +3...+5.5 V Digital Supply Voltage
15 GNDA Driver Ground
9 10 11 12 13 14 15 16 16 n.c.1
17 AO Signal Output A+
18 NAO Signal Output A-
19 VDDA +3...+5.5 V Driver Supply Voltage
20 1W 1-Wire Interface, bidirectional port
21 NERR Error Message Output (active low)
22 NRST External Reset Input (active low)
23 NSTORE2 Coefficient Store Input (active low)
24 n.c.1
25 NINA Signal Input A-
26 PINA Signal Input A+
27 KELVIN External Temperature Sensor Input
28 GNDIN Input Ground
29 VDDIN +3...+5.5 V Input Supply Voltage
30 PINB Signal Input B+
31 NINB Signal Input B-
32 VC 1.21 V Reference Voltage Output,
Reference Voltage Input (optional)

TP TP3 Thermal Pad

IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes);
1
Pin is not connected.
2
Pin NSTORE should be wired to VDD.
3
The Thermal Pad of the QFN package (bottom side) is to be connected to a ground plane on the PCB which must have GND potential.
iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 4/26

PACKAGE DIMENSIONS

RECOMMENDED PCB-FOOTPRINT
4.90
3.10
15
R0.

SIDE
0.90 ±0.10

4.90
3.10
0.70
0.50 0.30

TOP BOTTOM
5 3.10

3.10
5

0.40

0.50 0.25
All dimensions given in mm.
Tolerances of form and position according to JEDEC MO-220. dra_qfn32-5x5-3_pack_1, 10:1
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 5/26

ABSOLUTE MAXIMUM RATINGS

These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol Parameter Conditions Unit
No. Min. Max.
G001 VDDx() Voltage at VDD, VDDA, VDDB, VDDIN referenced to GND, GNDA, GNDB, GNDIN -0.3 6.0 V
G002 V() Voltage applied to any other pin referenced to GND -0.3 VDD + 0.5 V
G003 V() Voltage Difference VDDA, VDDB vs. 0.5 V
VDD
G004 V() Voltage Difference VDDIN vs. VDD 0.5 V
G005 V() Voltage Difference GNDA, GNDB vs. 0.5 V
GND
G006 V() Voltage Difference GNDIN vs. GND 0.5 V
G007 Vd ESD Susceptibility Of Signal Outputs: HBM, 100 pF discharged through 1.5 kΩ 2 kV
AO, NAO, BO, NBO, ZO, NZO
G008 Vd ESD Susceptibility (remaining pins) HBM, 100 pF discharged through 1.5 kΩ 2 kV
G009 Tj Junction Temperature -40 150 °C
G010 Ts Storage Temperature -40 150 °C

THERMAL DATA

Item Symbol Parameter Conditions Unit

No. Min. Typ. Max.
T01 Ta Operating Ambient Temperature Range -40 125 °C
T02 Rthja Thermal Resistance Chip To Ambient surface mounted to PCB according 40 K/W
to JEDEC 51

All voltages are referenced to ground unless otherwise stated.

All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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ELECTRICAL CHARACTERISTICS
Operating conditions: VDD, VDDA, VDDB, VDDIN = 3.0...5.5 V, Tj = -40...125 °C, reference point GND unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Total Device
001 VDDx Permissible Supply Voltage 3.0 5.5 V
at VDD, VDDA, VDDB, VDDIN
002 I(VDDx) Total Supply Current VDDx = 3.3 V 15 mA
VDDx = 5.5 V 25 mA
003 Vc()hi Clamp-Voltage hi at all pins Vc()hi = V() - VDD; I() = 10 mA 0.3 1.4 V
004 Vc()lo Clamp-Voltage lo at all pins I() = -10 mA -1.2 -0.3 V
Analog Signal Inputs PINA, NINA, PINB, NINB, PINZ, NINZ
101 Vin()sig Permissible Input Voltage Range 1.4 VDD - 1.2 V V
102 Vin()os Input Offset Voltage ±5 ±15 mV
103 Iin() Input Current ENSIGAB = 0, ENSIGZ = 0 -35 35 nA
104 Rpu() Input Pull-Up Resistor ENSIGAB = 1, ENSIGZ = 1 2.0 2.5 3 MΩ
105 fg -3 dB Bandwidth PGA gain of 36 dB 1.2 MHz
106 CMRR Common Mode Rejection Ratio fc < 1 MHz 40 dB
fc < 1 kHz 60 dB
107 PSRR Power Supply Rejection Ratio fc < 1 MHz 40 dB
fc < 1 kHz 60 dB
√
108 en Input Voltage Noise f = 1 kHz 20 n V/√Hz
f = 100 Hz 25 n V/√Hz
f = 0.1 to 10 Hz 2µ V/ Hz
109 ∆DGAIN Dynamic Gain Step Width 0.08 dB
110 ∆DOFFS Dynamic Offset Step Width 2 mV
Temperature Sensor and Analog Input KELVIN
201 Tor Int. Temperature Sensor Operat- after calibration of ADC; -50 150 °C
ing Range
202 Tacc Device-To-Device Temp. Sensor after calibration of ADC, ± 10 °C
Variation Tj = -40 °C to 125 °C
203 Vin()low Temperature Input Voltage CELSIUS(7:0) = 10 1.7 V
CELSIUS(7:0) = 245 0.9 V
204 Iin() Input Current at KELVIN V(KELVIN) = 0 .. VDD -50 50 nA
205 T()lo Lo-Temperature ADC Reading, after calibration of ADC;
via Register CELSIUS(7:0) XCELSIUS = 0, internal sensor: Tj = -40 °C 19
XCELSIUS = 1, ext. sensor: V(KELVIN) = 1.7 V 10
206 T()hi Hi-Temperature ADC Reading, after calibration of ADC;
via Register CELSIUS(7:0) XCELSIUS = 0, internal sensor: Tj = 125 °C 224
XCELSIUS = 1, ext. sensor: V(KELVIN) = 0.9 V 245
Reference Voltage Input/Output VC
301 Vout(VC) Reference Voltage Output VEXT = 0; CL = 100 nF, I() = 0 mA 1.10 1.21 1.35 V
302 Vin(VC) Permissible Input Voltage Range VEXT = 1 0 2.21 V
at VC
303 Iin(VC) Input Current at VC VEXT = 1 -0.1 1 µA
Power-On Reset and Input NRST
401 VDDon Turn-On Threshold (power-on increasing voltage at VDD 3.0 V
release)
402 VDDoff Turn-Off Threshold (power-down decreasing voltage at VDD 2.6 V
reset)
403 Vt()hi Input Threshold Voltage hi VDD = 3.3 V +/- 10 % 1.5 V
VDD = 5.0 V +/- 10 % 3.3 V
404 Vt()lo Input Threshold Voltage lo VDD = 3.3 V +/- 10 % 0.8 V
VDD = 5.0 V +/- 10 % 1.0 V
405 Ipu() Input Pull-Up Current V() = 0...VDD - 1 V -3 µA
406 Vpu() Input Pull-Up Voltage Vpu() = VDD - V(), I() = -3 µA 700 mV
iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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ELECTRICAL CHARACTERISTICS
Operating conditions: VDD, VDDA, VDDB, VDDIN = 3.0...5.5 V, Tj = -40...125 °C, reference point GND unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Oscillator CLK, TESTEN
501 Vt()hi Input Threshold Voltage hi VDD = 3.3 V +/- 10 % 1.5 V
VDD = 5.0 V +/- 10 % 3.3 V
502 Vt()lo Input Threshold Voltage lo VDD = 3.3 V +/- 10 % 0.8 V
VDD = 5.0 V +/- 10 % 1.0 V
503 Ipd() Input Pull-Down Current V() = 1 V...VDD 3 µA
504 Vpd() Input Pull-Down Voltage I() = 3 µA 700 mV
505 fosc Oscillator Frequency TEST_CLK = 1, measured at NERR;
CLKDIV = 0 (low active) 2 MHz
CLKDIV = 1 4 MHz
506 fin() Permissible External Clock Fre- 4 MHz
quency at CLK
1-Wire Interface 1W
601 Vs()lo Saturation Voltage lo I() = 1 mA 300 mV
602 Isc()lo Short-Circuit Current lo 2 mA
603 Ipu() Input Pull-Up Current V() = 0...VDD - 1 V -3 µA
604 Vpu() Input Pull-Up Voltage Vpu() = VDD - V(), I() = -3 µA 700 mV
605 tr(), tf() Rise and Fall Time (10/90%) VDD = 3.3 V, CL = 10 pF 32 ns
606 Vt()hi Input Threshold Voltage hi VDD = 3.3 V +/- 10 % 1.5 V
VDD = 5.0 V +/- 10 % 3.3 V
607 Vt()lo Input Threshold Voltage lo VDD = 3.3 V +/- 10 % 0.8 V
VDD = 5.0 V +/- 10 % 1.0 V
I2C Interface SDA, SCL
701 Vs()lo Saturation Voltage lo I() = 1 mA 400 mV
702 Isc()lo Short-Circuit Current lo V() = 1V...VDD 3 mA
703 Ipu() Pull-Up Current V() = 0...VDD - 1 V -3 µA
704 Vpu() Input Pull-Up Voltage Vpu() = VDD - V(), I() = -3 µA 700 mV
705 Vt()hi Input Threshold Voltage hi at VDD = 3.3 V +/- 10 % 1.5 V
SDA VDD = 5.0 V +/- 10 % 3.3 V
706 Vt()lo Input Threshold Voltage lo at VDD = 3.3 V +/- 10 % 0.8 V
SDA VDD = 5.0 V +/- 10 % 1.0 V
707 fclk() Write/Read Clock Frequency at CLKDIV = 0 100 kHz
SCL
708 tbusy()cfg Duration Of Startup Configuration CLKDIV = 0, 2 LUT blocks 20 ms
CLKDIV = 0, 16 LUT blocks 80 ms
Digital Output NERR
901 Vs()lo Saturation Voltage lo I() = 1 mA 400 mV
902 Vs()hi Saturation Voltage hi Vs()hi = VDD - V(); I() = -1 mA 400 mV
903 Isc()lo Short-Circuit Current lo 3 mA
904 Isc()hi Short-Circuit Current hi -2.5 mA
iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 8/26

ELECTRICAL CHARACTERISTICS
Operating conditions: VDD, VDDA, VDDB, VDDIN = 3.0...5.5 V, Tj = -40...125 °C, reference point GND unless otherwise stated
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Line Driver Outputs AO, NAO, BO, NBO, ZO, NZO
B01 Vpk()max Permissible Output Amplitude VDD = 3 V, RL = 50 Ω vs. VDD/2 550 mV
B02 Vdc() Output DC Voltage VDD / 2
B03 ∆Vout() Output Voltage Load Depen- I() = 0...5 mA 50 mV
dency
B04 Isc()lo Short-Circuit Current lo pin shorten to VDD/2 12 50 mA
B05 Isc()hi Short-Circuit Current hi pin shorten to VDD/2 -50 -12 mA
B06 Isc() Output Current Limitation hi/lo V() = 0...VDD 40 50 mA
B07 SR()hi, lo Slew Rate hi/lo CL() = 5 nF 3 V / µs
CL() = 50 pF 4 V / µs
B08 tS Settling Time CL() = 5 nF, to 0.1% of final value 1 µs
B09 dbVlin Output Linearity 100 kHz sine and diff. 1 Vpp output voltage;
RL() > 1 kΩ 80 dB
RL() = 120 Ω 60 dB
B10 CLmax Maximum Capacitive Output no sustained oscillation 100 nF
Load
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 9/26

PROGRAMMING

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 10 Automatic Compensation . . . . . . . . . . . . . . . . . Page 19

VEXT: Target voltage select
DYNAMIC: Automatic compensation control
I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 12 FREQ: Automatic adaption frequency
CHECKSUM: EEPROM Checksum GENTLE: Automatic compensation update rate

1-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 13 Temperature Sensing . . . . . . . . . . . . . . . . . . . . . Page 20

XCELSIUS: Temperature sensor select
FCELSIUS: Fine temperature offset value
A/B Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 CCELSIUS: Coarse temperature offset value
SINGLEIN: Single ended input functionality CELSIUS: Current temperature value
ENSIGAB: Input signal error detection control
CGAINA/B: Coarse gain select for channel A/B Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21
COFSA/B: Coarse offset select for channel A/B ERR_SIG: Signal unconnected alarm
DGAINA/B: Dynamic gain on channel A/B ERR_TEMP: Temperature alarm
DOFSA/B: Dynamic offset on channel A/B ERR_EE: EEPROM error condition
OGAIN: Output amplifier gain select on channel
A/B Temperature Compensation . . . . . . . . . . . . . . Page 22
FILTER: Signal path filter select TEMP: Temperature compensation control
PDA/B: Power down control for channel A/B
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 23
Z Signal Path (Index) . . . . . . . . . . . . . . . . . . . . . . Page 17 PD_CELSIUS: Power down control for internal tem-
SINGLEZ: Single ended input functionality for in- perature sensor
dex channel Z TEST_CLK: Internal test clock oscillator control
MODEZ: Channel Z output mode select CLKDIV: Internal clock divider select
BYPASSZ: Channel Z comparator bypass control
GAINZ: Gain select for channel Z Typical Applications . . . . . . . . . . . . . . . . . . . . . . Page 24
OFSZ: Offset select for channel Z
OGAINZ: Output amplifier gain select on channel
Z
ENSIGZ: Input signal error detection control on
channel Z
PDZ: Power down control for channel Z
POLARITYZ: Channel Z polarity select
iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 10/26

REGISTER MAP
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration Registers
0x00 ROM Device ID[7:0]
0x01 OGAIN[1:0] SINGLEIN FREQ[1:0] GENTLE DYNAMIC TEMP
0x02 VEXT XCELSIUS OGAINZ[1:0] MODEZ BYPASSZ SINGLEINZ POLARITYZ
0x03 ERR_SIG ERR_TEMP ERR_EE TALARM[2:0] ENSIGZ ENSIGAB
0x04 EN_NSTORE* FILTER[1:0] PDZ PDB PDA
0x05 CCELSIUS[3:0] FCELSIUS[3:0]
0x06 GAINZ[2] OFSZ[5:0]
0x07 GAINZ[1:0] CGAINB[2:0] CGAINA[2:0]
0x08 COFSA[7:0]
0x09 COFSB[7:0]
0x0A DGAINA[7:0]
0x0B DGAINB[7:0]
0x0C DOFSA[7:0]
0x0D DOFSB[7:0]
0x0E VC[1:0]* CLKSLOW* CLKDIV TEST_CLK PD_CELSIUS
0x0F Internal Checksum(7:0)
0x10 TEST_ADC* TEST_VGA* TEST_PGA* VTEST1* VTEST0* PD_BG* TEST_BG*
0x11
0x12 CELSIUS[7:0]
0x13
Internal State Machine Registers
0x14 INTERNAL USE
0x15 INTERNAL USE
0x16 INTERNAL USE
0x17 INTERNAL USE
0x18 INTERNAL USE
0x19 INTERNAL USE
0x1A INTERNAL USE
0x1B INTERNAL USE
0x1C INTERNAL USE
0x1D INTERNAL USE
0x1E INTERNAL USE
0x1F INTERNAL USE
0x20 INTERNAL USE
0x21 INTERNAL USE
0x22 INTERNAL USE
0x23 INTERNAL USE
0x24 INTERNAL USE
0x25 INTERNAL USE
0x26 INTERNAL USE
0x27 INTERNAL USE
Peripheral Registers
0x40 CELSIUSRAW[7:0]
0x41 CHANNEL OFS_P OFS_N GAIN_P GAIN_N
0x42 EE_ERR XERR_OUT 1OUTPUT 1INPUT XSTORE SIG_VALID
iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 11/26

REGISTER MAP
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x43 EE_IRQ 1INPUT_IRQ XS-
TORE_IRQ
Notes Only the configuration registers are user programmable.
*) Bits marked by an asterisk are solely intended for IC test and must be kept
on zero for normal operation.

Table 4: Register layout

 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 12/26

I2C INTERFACE

Startup Note that the EEPROM address space maps to the

An external I2 C 1-kbit EEPROM (e.g. 24xx01 family) 1-wire address 128. Accessing EEPROM address 0
is used to store configuration parameters permanently. is therefore equivalent to accessing memory location
On power-up and after reset is released iC-TW3 ac- 128 via the 1-wire interface (see page 13).
cesses the external EEPROM and reads its device
configuration according to Table 6. EEPROM Description Corresponding
Address Configuration Register
EEPROM Checksum 0x00 <reserved> -
The checksum at address 0x0F contains the 8-bit sum 0x01 Config. 1 0x01
of registers 0x01 to 0x0E plus the 8-bit sum of all LUT 0x02 Config. 2 0x02
bytes up to and including the final block with its break- 0x03 Config. 3 0x03
point set to 255. 0x04 Config. 4 0x04
0x05 Temp. Sensing 0x05
On startup iC-TW3 calculates the expected checksum 0x06 Config. Index 0x06
and compares it with the value stored at EEPROM 0x07 Coarse Gain 0x07
address 0x0F. If computed and stored address match 0x08 COFSA 0x08
normal operation begins. Otherwise, iC-TW3 asserts 0x09 COFSB 0x09
an error condition and pin NERR is pulled low. 0x0A DGAINA 0x0A
0x0B DGAINB 0x0B
It is the user’s responsibility to store the correct check- 0x0C DOFSA 0x0C
sum in the EEPROM during production programming. 0x0D DOFSB 0x0D
0x0E Test 1 0x0E
CHECKSUM(7:0) Addr. 0x0F; bit 7:0 R/W 0x0F CHECKSUM 0x0F
Code Function EEPROM Description LUT Block Number
Address
... Checksum of EEPROM contents:
over 0x01 to 0x0E and 0x10 to 0x1B (minimum) 0x10 Breakpoint 0 0
over 0x01 to 0x0E and 0x10 to 0x6F (maximum) 0x11 GAINA 0
0x12 GAINB 0
Table 5: Checksum 0x13 OFSA 0
0x14 OFSB 0
0x15 OFSZ 0
EEPROM Register Map
0x16 Breakpoint 1 (255) 1
The 14 bytes of device configuration data are followed
0x17 GAINA 1
by a minimum of 2 to a maximum of 16 lock-up-table
0x18 GAINB 1
blocks (LUT). The LUT block size is 6 bytes each and
0x19 OFSA 1
the final block is indicated by its breakpoint value of
0x1A OFSB 1
255.
0x1B OFSZ 1
. . .
Thus, a minimum of 28 bytes are read with 2 active . . .
LUT blocks and 112 bytes are read with 16 active LUT . . .
blocks during the configuration phase. 0x6A Breakpoint 255 15
0x6B GAINA 15
The last LUT block ist indicated by a breakpoint value of 0x6C GAINB 15
255. Further descriptions on LUTs are given in section 0x6D OFSA 15
"Temperature Compensation" on page 22. 0x6E OFSB 15
0x6F OFSZ 15
Note that the checksum is only calculated up and
including the last LUT block. Table 6: EEPROM register map
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 13/26

1-WIRE INTERFACE

The 1-wire interface provides read and write access to short high followed by a long low. A one-bit is encoded
the register bank and to the external EEPROM. When as a long high followed by a short low.
read access is not required an infrared phototransistor
can be directly connected to the pin in order to build The modulated signal is independent of the receiver or
a cost effective wireless write-only port for in-field or the transmitted clock frequency. Since iC-TW3 uses
production programming. a free-running oscillator it is important to implement a
robust, frequency insensitive protocol.
The communication bit stream is pulse-width modulated
(PWM) as shown in Figure 1. A zero-bit is encoded as a

1- wire timing

idle start 1 0 delay idle

tlong tlong tshort tshort tlong tshort tdelay tidle

Figure 1: Pulse width modulation bit stream

Parameter Description min max

tstart Low time start condition (Master only) 1 ms
tlong Unit time long (Master and iC-TW3) tshort + 10 µs 400 µs
tshort Unit time short (Master and iC-TW3) 35 µs tlong - 10 µs
tdelay Delay on register read (iC-TW3 only) 35 µs
tidle Interface idle before next access
Access was write to external EEPROM 8 ms
Access was not write to external EEPROM 3 ms

Table 7: 1-Wire interface timing

 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 14/26

Addressing by generating a start condition followed by the write

The EEPROM address 0x00 maps to the 1-wire ad- command (000) and by the address and register data.
dress 128. Accessing EEPROM address 0 is therefore
equivalent to accessing memory location 128 through
the 1-wire interface. All other 1-wire addresses are thus Read Sequence
determined by adding 128 to the EEPROM address of A read sequence is depicted in Figure 3. After the start
interest. condition the read command (001) is followed by the
register address. The master then releases the wire
Write Sequence and iC-TW3 begins to pull low while internally access-
Figure 2 describes the write sequence of the 1-wire ing the data. When the data is ready it is produced while
interface. On an idle wire, a write sequence is initiated following the same PWM rules valid for the master.

1-Wire Write Access Wire not driven

3-bit command word
000 = write Wire driven by master
Idle, wire is high 001 = read Filler bit, value 0

idle start 000 address(7:0) 0 data(7:0) idle

To initiate communication 8-bit register address: Wait at least for tidle

pull low for at least tstart 0 to 127: internal registers before new access
128 to 255: external EEPROM

Figure 2: Register write sequence

1-Wire Read Access Wire not driven Wire driven by master Wire driven by iC-TW3
3 bit command word
000 = write iC-TW3 starts returning data
Idle, wire is high 001 = read Master releases driver (first bit is dummy)

idle start 001 address(7:0) delay X data(7:0) idle

To initiate communication 8-bit register address: iC-TW3 drives low until Wait at least for tidle
pull low for at least tstart 0 to 127: internal registers data is ready before new access
128 to 255: external EEPROM

Figure 3: Register read sequence

 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
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Rev B2, Page 15/26

A/B SIGNAL PATH

iC-TW3 incorporates two analog gain paths called chan- sated. Figure 4 depicts a diagram of a single signal
nel A and B, respectively. Gain and offset of both paths path, Table 8 below summarizes gain and offset char-
are independently controlled and temperature compen- acteristics.

VDD

ENSIGAB

COFSA/B(5:0)

FILTER(1:0)

PINA/PINB AO/BO
+ +
NINA/NINB Input + dynamic output
- NAO/NBO
CGAINA/B(2:0)
SINGLEIN FGAINA/B(7:0) OGAIN(1:0)
FOFSA/B(7:0)
VDD/2

Figure 4: The A/B signal path

Input Amplifier Dynamic Amplifier Output Amplifier Composite

Gain range 0..36 dB -2..18.4 dB -3 dB, 0 dB, 6 dB -5..60 dB
Gain step 6.0 dB 0.08 dB
±1.24 V ±0.25 V ±1.49 V
Offset range input gaininput gaininput gaininput
referred
40 mV 2 mV
Offset step input referred gaininput gaininput
gain_of _input_amplifier_in_dB
gaininput = 10 20

Table 8: Overview of gain and offset characteristics

Single ended signals sor connections. Any input terminal left unconnected
Single ended input functionality is provided by connect- is pulled to VDD and triggers a sensor error condition
ing the negative input terminal (pins NINA and NINB) err_sig.
to an internally generated voltage of VDD /2. This is
enabled by setting the control bit SINGLEIN to 1. Alter- ENSIGAB Addr. 0x03; bit 0 R/W
natively, an externally generated reference voltage may Code Function
be applied to the negative input terminals. 0 Pull-up resistors disconnected and error reporting
disabled (default)
1 Pull-up resistors and error reporting active on A/B
SINGLEIN Addr. 0x01; bit 5 R/W inputs
Code Function
0 A and B inputs are differential (default) Table 10: Input signal error detection control
1 A and B inputs are single ended

Table 9: Single ended input functionality Gain and offset

Registers CGAINA(2:0) and CGAINB(2:0) are used to
set the coarse gain. Coarse gain is static and it is not
Input error detection changed by the temperature or automatic compensa-
Weak input pull-up resistors are enabled by setting con- tion algorithm.
trol bit ENSIGAB to 1. The resistors are at minimum
2.0 MΩ. When driving the input with a high impedance The highest legal value for CGAINA(2:0) and
source it might be necessary to disable the pull-up re- CGAINB(2:0) is 6. Equivalently registers COFSA(5:0)
sistors to avoid excessive signal distortion. The pull-up and COFSB(5:0) are used to control the static off-
resistors are used to sense floating or damaged sen- set of the input signal. Note that COFSA(5:0) and
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 16/26

COFSB(5:0) are in 2’s complement format and their enabled the values of FGAINA/B and FOFSA/B are
value range is limited from -31 to +31. equal to the register values in DGAINA/B(7:0) and
DOFSA/B(7:0). Refer to chapter "Temperature Com-
CGAINA(2:0) Addr. 0x07; bit 2:0 R/W pensation" on page 22 for a detailed explanation of fine
CGAINB(2:0) Addr. 0x07; bit 5:3 R/W gain and fine offset calculations. DGAINA/B(7:0) and
Code gain = cgain x 6 dB DOFSA/B(7:0) can be programmed to a fixed value or
0x00 0 dB (default) it is automatically updated when dynamic adaption is
0x01 6 dB enabled.
...
0x06 36 dB Output driver
The output amplifier is capable of driving a 100 Ω differ-
Table 11: Coarse gain select for channel A/B ential load and is stable with capacitive loads of up to
100 nF. Control register OGAIN(1:0) is used to select
COFSA(7:0) Addr. 0x08; bit 7:0 R/W the output amplifier gain. A gain of -3 dB is useful to
COFSB(7:0) Addr. 0x09; bit 7:0 R/W accommodate input signals larger than 1 V and gain of
Code 2’K Code 5:0, and decimal offset = cofs x 40 mV +6 dB will provide a 1 Vpp single-ended output. Note
0xE1 0x21, -31 -1240 mV that the selected output amplifier gain will influence the
... ... automatic gain compensation. Refer to section "Auto-
0xFF 0x3F, -1 -40 mV matic Compensation" on page 19 for details.
0x00 0x00, 0 0 mV (default)
0x01 0x01, +1 40 mV OGAIN(1:0) Addr. 0x01; bit 7:6 R/W
... ... Code Function
0x1F 0x1F, +31 1240 mV 0x00 0 dB (default)
0x01 Reserved
Table 12: Coarse offset select for channel A/B 0x02 +6 dB
0x03 -3 dB
DGAINA(7:0) Addr. 0x0A; bit 7:0 R/W
DGAINB(7:0) Addr. 0x0B; bit 7:0 R/W
Table 15: Output amplifier gain on channel A/B
Code gain = dgain x 0.08 dB - 2 dB
0x00 -2 dB (default) A programmable 1st -order low-pass filter can be en-
... abled to limit the path bandwidth. The filter cut-off
0x19 0 dB frequency can be set via the FILTER(1:0) register.
0x1A 0.08 dB
... FILTER(1:0) Addr. 0x04; bit 4:3 R/W
0xFF 18.4 dB Code Function
0x00 1 MHz (default)
Table 13: Dynamic gain select for channel A/B 0x01 500 kHz
0x02 200 kHz
DOFSA(7:0) Addr. 0x0C; bit 7:0 R/W 0x03 reserved
DOFSB(7:0) Addr. 0x0D; bit 7:0 R/W
Code offset = cofs x 2 mV Table 16: Signal path filter
0x81 -254 mV
... In order to save power the complete signal path can be
0xFF -2 mV disabled using the control bits PDA and PDB respec-
0x00 0 mV (default) tively. When disabled the outputs are high impedance.
0x01 2 mV The dynamic adaption should be disabled when either
... channel A or B is disabled.
0x7F 254 mV
PDA Addr. 0x04; bit 0 R/W
Table 14: Dynamic offset select for channel A/B PDB Addr. 0x04; bit 1 R/W
Code Function
Value FGAINA/B and FOFSA/B are fine gain and off- 0 Channel A/B is enabled (default)
set control respectively. They are calculated dynam- 1 Channel A/B is powered down
ically according to the temperature compensation al-
gorithm. In case temperature compensation is not Table 17: Power down control on channel A/B
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 17/26

Z SIGNAL PATH (INDEX)

A third analog path is used for index signal processing output referred offset correction. This is used to elimi-
frequently found in encoder applications. Refer to Fig- nate inherent amplifier offset as well as sensor offset.
ure 5 for an overview. An input amplifier with a gain Additionally, the same offset correction is used to skew
range of 0 to 36 dB is used to amplify the index signal the comparator shift point to a desired level. The offset
to an intermediate level. The input amplifier employs correction is temperature compensated with a LUT.

VDD

ENSIGZ
OFSZ(5:0) BYPASSZ

PINZ ZO
+ + + +
1Vpp output
NINZ NZO
- POLARITYZ
- -
GAINZ(2:0) MODEZ OGAINZ(1:0)
SINGLEINZ

VDD/2

Figure 5: The Z signal path

Input Amplifier Output Amplifier Composite

Gain range 0..36 dB -3 dB, 0 dB, 6 dB -3..42 dB
Gain step 6 dB
±1.86 V ±1.86 V
Offset range input gaininput gaininput
referred
60 mV
Offset step input referred gaininput
gain_of _input_amplifier_in_dB
gaininput = 10 20

Table 18: Gain and offset characteristics for channel Z

A single ended input referenced to VDD /2 is provided by MODEZ Addr. 0x02; bit 3 R/W
setting bit SINGLEINZ of register 0x02. Alternatively, Code Function
pin NINZ can be biased with an external voltage. 0 1 Vpp out (default)
1 Rail-to-rail output
SINGLEINZ Addr. 0x02; bit 1 R/W (requires OGAINZ(1:0) set to 0x2)
Code Function
Table 20: Channel Z output mode select
0 Channel Z input is differential (default)
1 Channel Z is single ended
BYPASSZ Addr. 0x02; bit 2 R/W
Table 19: Single ended input functionality Code Function
0 Comparator is enabled (default)
1 Comparator is bypassed
A zero-crossing comparator generates a 1.0 Vpeak-peak
output signal or a rail-to-rail signal depending on control
Table 21: Channel Z comparator bypass
bit MODEZ. The comparator can be bypassed which
allows using the Z Path as a regular amplifier path. By-
passing can be toggled via bit BYPASSZ of register
0x02.
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 18/26

Gain and offset OGAINZ(1:0) Addr. 0x02; bit 5:4 R/W

Gain and offset selections on channel Z are made Code Function
available by providing control bits GAINZ(2:0) and 0x00 0 dB (default)
OFSZ(5:0). Note that the maximum value for gain on 0x01 Reserved
channel Z is 6 which corresponds to a total gain of 0x02 +6 dB
36 dB. 0x03 -3 dB

Table 24: Output amplifier gain on channel Z

GAINZ(2:0) is split up amongst register 0x06 which
holds the MSB and register 0x07 holding the other two Input error detection
bits. OFSZ(5:0) is the correction value to the output of Pull-up resistor and error detection on channel Z can be
the input amplifier and is interpreted as 2’s complement. controlled by bit ENSIGZ of register 0x03, disabling of
The input referred offset is therefore gain dependent. the complete Z path can be achieved by setting bit PDZ
of register 0x04 to 1. For more detailed information on
pull-up and power control refer to section "A/B PATH"
on page 15 as the behaviour of index path and signal
The output gain on channel Z can be set via control bits
path equal regarding these matters.
OGAINZ(1:0). For more details again refer to section
"A/B PATH" on page 15.
ENSIGZ Addr. 0x03; bit 1 R/W
Code Function
0 Pull-up resistors disconnected and error reporting
GAINZ(2:0) Addr. 0x06; bit 7 R/W disabled (default)
Addr. 0x07; bit 1:0 1 Pull-up resistors and error reporting active on inZ
Code gain = gainz x 6 dB
0x00 0 dB (default) Table 25: Input signal error detection control
0x01 6 dB
... PDZ Addr. 0x04; bit 2 R/W
0x06 36 dB Code Function
0 Channel Z is enabled (default)
Table 22: Gain select for channel Z 1 Channel Z is powered down

Table 26: Power-down control on channel Z

OFSZ(5:0) Addr. 0x06; bit 5:0 R/W
Code 2’K Decimal offset = cofs x 60 mV Polarity of channel Z
0x21 -31 -1860 mV Furthermore, the polarity on channel Z can be inverted
... ... by setting or not setting bit POLARITYZ.
0x3F -1 -60 mV
0x00 0 0 mV (default) POLARITYZ Addr. 0x02; bit 0 R/W
0x01 +1 60 mV Code Function
... ... 0 Channel Z has normal polarity (default)
0x1F +31 1860 mV 1 Channel Z has inverted polarity

Table 23: Offset select for channel Z Table 27: Channel Z polarity select
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 19/26

AUTOMATIC COMPENSATION

Automatic gain and offset correction is available for dual Note that setting FREQ(1:0) to other values than 0 does
sensor bridges that are 90° out of phase. These types not affect the signal bandwidth of the amplifier. It merely
of sensors are used for encoder applications. limits the rate of automatic adaption.

Automatic compensation removes any sensor offset

FREQ(1:0) Addr. 0x01; bit 4:3 R/W
and sets the gain to achieve a fixed output voltage.
Code Function
The target output voltage depends on the output gain
00 No tracking limit (default)
OGAIN(1:0) as well as on the control bit VEXT. When
01 200 kHz
using an external reference voltage, the appropriate
10 20 kHz
voltage must be applied to pin VC.
11 2 kHz

VEXT Addr. 0x02; bit 7 R/W

Table 31: Automatic compensation adaption rate
Code Function
0 Internally generated 1 V or 2 V is used as output
target voltage, depending on register OGAIN(1:0).
In normal operation the compensation algorithm will
1 Voltage applied to pin VC defines target output
voltage (see Table 29).
adjust both gain and offset simultaneously in order to
achieve fast convergence. If control bit GENTLE of
Table 28: Target voltage selection register 0x01 is set, gain and offset registers are up-
dated alternately. This reduces output jumpiness at the
Target Output
expense of slower convergence.
OGAIN(1:0) Output Gain VEXT Voltage Vppdiff
00 0 dB 0 1V GENTLE Addr. 0x01; bit 2 R/W
01 reserved 0 Code Function
10 6 dB 0 2V 0 Gain and offset are updated simultaneously
11 -3 dB 0 1V 1 Gain and offset are updated alternately
00 0 dB 1 2.21 V - V(VC)
01 reserved 1 Table 32: Automatic compensation sequence control
10 6 dB 1 (2.21 V - VC) x 2
11 -3 dB 1 2.21 V - VC
Automatic compensation can be used in conjunction
Table 29: Target output voltages with temperature compensation. Automatic compensa-
tion will then remove any residual offset or gain mis-
match not corrected by the temperature correction al-
Automatic compensation is enabled by setting control
gorithm.
bit DYNAMIC of register 0x01 to 1. If enabled, it will
constantly alter register DOFSA/B and DGAINA/B to
maintain zero offset and the target output amplitude. Limitation
Control bits FREQ(1:0) of register 0x01 are used to The automatic compensation measures the amplitude
limit the tracking rate. If the input frequency increases and offset at the output of iC-TW3. In order to provide
above the limit tracking will stop. Normally, it is not meaningful information the output signals must be of
required to limit the tracking frequency although it can reasonable encoder quality at all times. They need to
be useful for certain bandwidth limited sensors. be 90° out of phase and most importantly the ampli-
tude must be larger than 0.5 V peak-peak differential
DYNAMIC Addr. 0x01; bit 1 R/W (larger than 0.25 V peak-peak single ended) whereas
Code Function the offset must be less then +/- 0.25 V. In situations
0 Automatic function is disabled where the minimum amplitude is not guaranteed, e.g
1 Automatic function is enabled by removing the MR input sensor from the magnetic
source, wrong offset and gain control correction data
Table 30: Automatic compensation enable might be generated.
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 20/26

TEMPERATURE SENSING

iC-TW3 contains an on-chip temperature sensor. Op- CCELSIUS(3:0) Addr. 0x05; bit 7:4 R/W
tionally, an external sensor can be used by setting bit Code Bit 3 is sign, bits 2:0 are magnitude of correction
XCELSIUS of register 0x02 to 1. An external tempera- 1111 Most negative correction
ture sensor is useful for remote temperature sensing or ... ...
in situations where the internal sensor does not provide 1001 Least negative correction
adequate accuracy. Also, device self-heating due to 1000 No correction
heavy output loads can have an impact on the internal 0000 No correction (default)
sensor readings. Connect the external temperature 0001 Least positive correction
sensor with its analog output to pin KELVIN. ... ...
0111 Most positive correction

Table 34: Coarse offset correction

XCELSIUS Addr. 0x02; bit 6 R/W
Code Function FCELSIUS(3:0) Addr. 0x05; bit 3:0 R/W
0 Select internal temperature sensor (default) Code Value added to ADC reading is FCELSIUS(3:0) - 8
1 Select external temperature sensor 0000 -8 (default)
0001 -7
Table 33: Temperature sensor select ... ...
1111 7

Table 35: Fine offset correction

An ADC converts the analog temperature signal into an
8-bit digital word. In case the on-chip sensor is used CELSIUS(7:0) Addr. 0x12; bit 7:0 R
the 8-bit value spans a temperature range of -50 °C to Data Function
150 °C. It is recommended to calibrate the ADC using 0x00 Current temperature ADC value that is used for
register 0x05 even when using an external temperature compensation calculations. Value of this register is
0x40 + FCELSIUS(3:0) - 8
sensor.
0xFF

Table 36: Temperature data

Calibrating the temperature ADC

The raw ADC value can be accessed through register Temperature alarm
0x40. A ±2 increment hysteresis is applied to the ADC The iC-TW3 features a built-in temperature alarm sys-
value to remove conversion noise and the offset regis- tem. An alarm threshold can be specified by the user
ter 0x05 is added. The final value is stored in register via the TALARM(2:0) bits in register 0x03. A temper-
0x12 and is used for temperature compensation. ature alarm is asserted once the temperature value
generated by the ADC is above the defined threshold.
The alarm is indicated by the ERR_TEMP bit set to 1
as well as by pin NERR going low.
To achieve best temperature accuracy it is required to
calibrate the ADC by correctly programming register TALARM(2:0) Addr. 0x03; bit 4:2 R/W
0x05. At any known ambient temperature the register Code tempthreshold = (TALARM(2:0) x 16) + 144
0x05 is programmed such to read the expected ADC 000 144 (default)
value. As an example, consider the product assem- 001 160
bly floor with an ambient temperature of 20 °C. Due to ... ...
device variation the ADC value read before calibration 110 240
can be anything between 0 °C to 40 °C. Register 0x05 111 Alarm disabled
is now used to tune the ADC output value to the correct
binary representation of 20 °C. Table 37: Temperature alarm threshold
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 21/26

ERROR CONDITIONS

iC-TW3 maintains three status bits reporting system ERR_TEMP Addr. 0x03; bit 6 R
error conditions. These bits are ERR_EE, ERR_TEMP Code Error message
and ERR_SIG of register 0x03. If any error condition is 0 ADC reading is below value defined in register
triggered, i.e. indicated by any of these bits being set TALARM(2:0)
to 1, this will also assert pin NERR pulling it low. 1 ADC reading is above value defined in register
TALARM(2:0)
Notes This error is not latched. Disabling temperature
ERR_EE Addr. 0x03; bit 5 R monitoring is possible by setting TALARM(2:0) to
Code Error message ’111’.
0 No error since the last reset
1 One of the following error conditions has occurred
Table 39: Temperature alarm
since the last reset:
1. EEPROM checksum error*
ERR_SIG Addr. 0x03; bit 7 R
2. EEPROM read error
3. EEPROM write error Code Error message
Notes This error message can not be disabled and its bit 0 All input terminals are connected
status is maintained until the device is reset. 1 An input terminal is left unconnected
*) A permanent logic zero read at SDA does not lead Notes This error is not latched. To enable this alarm
to a checksum error. ENSIGAB or ENSIGZ must be set 1.

Table 38: EEPROM data error Table 40: Signal unconnected alarm
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 22/26

TEMPERATURE COMPENSATION

Temperature compensation is enabled by setting con- TEMP Addr. 0x01; bit 0 R/W
trol bit TEMP of register 0x01. A piece-wise linear Code Function
interpolation of values stored in a look-up-table (LUT) 0 Temperature compensation is disabled (default)
is employed to calculate the gain and offset for a given 1 Temperature compensation is enabled
temperature. Figure 6 shows a sample configuration
with seven breakpoints. Table 41: Temperature compensation enable

gain/ofs

ofsZ
ofsB
ofsA
gainB
gainA

ADC value
bp0 bp1 bp2 bp3 bp4 bp5 bp6
0 255

Figure 6: LUT with seven breakpoints

There can be a minimum of two up to a maximum LUT entry. All addresses thereafter including their data
of 16 temperature breakpoints within the LUT. Each will be ignored.
breakpoint has five interpolation values associated to it
namely GAINA, GAINB, OFSA, OFSB and OFSZ. For Temperature dependent gain and offset is determined
more details on the layout of the LUT refer to section by performing linear interpolation between breakpoints.
"EEPROM" on page 12. Temperature dependent gain and offset are TGAINA/B
and TOFSA/B respectively.
Breakpoints can be placed freely across the temper-
ature axis except for the first and the last breakpoint. Fine gain FGAINA/B and fine offset FOFSA/B (see fig-
The first breakpoint must be located at ADC value 0 ure 4 on page 15) are calculated as follows:
(which roughly corresponds to -50 °C when using the
internal sensor), the last breakpoint must be located at
ADC value 255 (150 °C with the internal sensor). fgain = tgain + dgain
fofs = tofs + dofs
The LUT is stored in the off-chip EEPROM from memory
location 0x10 onward. Note that the EEPROM address
space maps to the 1-wire address 128. Accessing EEP- Whereas TGAIN and TOFS are the temperature depen-
ROM address 0 is therefore equivalent to accessing dent values calculated using the LUT and DGAIN and
memory location 128 through the 1-wire interface. The DOFS are registers updated either manually or by the
breakpoint entry with a value of 255 marks the last valid automatic compensation function.
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 23/26
EEPROM address 16 22 28
1-wire address 16 + 128 = 144 22 + 128 = 150 28 + 128 = 156

0 1 255
gainA gainA gainA
gainB gainB gainB
ofsA ofsA ofsA
ofsB ofsB ofsB
ofsZ ofsZ ofsZ

3 breakpoint look-up table

EEPROM address 16 22 106

1-wire address 16 + 128 = 144 22 + 128 = 150 106 + 128 = 234

0 1 255
gainA gainA gainA
gainB gainB gainB
ofsA ofsA ofsA
ofsB ofsB ofsB
ofsZ ofsZ ofsZ

16 breakpoint look-up table

Figure 7: Temperature LUT memory map

TEST MODES

The iC-TW3 posses two registers 0x0E and 0x10 which TEST_CLK Addr. 0x0E; bit 1 R/W
provide access to basic testing functionality. The Code Function
PD_CELSIUS bit allows powering off the internal tem- 0 Clock is not driven on any pin (default)
perature sensor. If powered down, the temperature 1 Clock is driven on pin NERR
sensor output value can be forced to a desired value
by writing to register 0x40. The user can then test the Table 43: Internal clock oscillator
compensation circuit without cycling the device temper-
ature. CLKDIV Addr. 0x0E; bit 2 R/W
Code Function
PD_CELSIUS Addr. 0x0E; bit 0 R/W 1 fsystem = fosc (default)
Code Function 0 fsystem = fosc / 2
0 Temperature sensor enabled (default)
1 Temperature sensor disabled Table 44: Internal clock divider selection

Table 42: Temperature sensor power control

 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 24/26

TYPICAL APPLICATIONS

A typical application is shown in figure 8. Three differ- A, B and Z outputs are driving 120Ω terminated trans-
ential MR sensor bridges are connected to the iC-TW3. mission lines.

+3...5.5V +3...5.5V

VDDIN/A/B VDD
0.1μF 0.1μF
GNDIN/A/B GND
termination
120 Ω
PINA AO
R
Sensor NAO
Bridge 0
NINA
BO
PINB R
NBO
Sensor
Bridge 1
ZO
NINB
R
NZO
PINZ
VDD

Index 10k
Sensor SCL SCL
NINZ SDA SDA
24xx01
iC-TW3 EEPROM

Figure 8: Typical application MR Sensors

REVISION HISTORY

Rel. Rel. Date∗ Chapter Modification Page

B2 2017-08-07 BLOCK DIAGRAM Update of block diagram 1
PACKAGING INFORMATION QFN with top marking, revision of footnote, update of QFN package drawing 3ff
I2C INTERFACE Table 5: contents supplemented. 12
Text moves to grey note boxes.
AUTOMATIC COMPENSATION ’Limitation’ paragraph added. 19
ORDERING INFORMATION P/O code of eval board 26

∗ Release Date format: YYYY-MM-DD

 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 25/26
iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the
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Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.

The data specified is intended solely for the purpose of product description and shall represent the usual quality of the product. In case the specifications contain
obvious mistakes e.g. in writing or calculation, iC-Haus reserves the right to correct the specification and no liability arises insofar that the specification was from
a third party view obviously not reliable. There shall be no claims based on defects as to quality in cases of insignificant deviations from the specifications or in
case of only minor impairment of usability.
No representations or warranties, either expressed or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder
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particular, this also applies to the stated possible applications or areas of applications of the product.

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Software and its documentation is provided by iC-Haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Products
and Services with iC-Haus amendments and the ZVEI Software clause with iC-Haus amendments (www.ichaus.com/EULA).
 iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B2, Page 26/26

ORDERING INFORMATION

Type Package Order Designation

iC-TW3 32-pin QFN, 5 mm x 5 mm, iC-TW3 QFN32

thickness 0.9 mm,
RoHS compliant

Evaluation board iC-TW3 EVAL TW3D_2D

Please send your purchase orders to our order handling team:

Fax: +49 (0) 61 35 - 92 92 - 692

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For technical support, information about prices and terms of delivery please contact:

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