QP CODE : 71248

LINEAR INTEGRATED CIRCUITS SOLUTION

(CBCGS SEM – 4 DEC 2019)
BRANCH – ELECTRONICS AND TELECOMMUNICATION

Q.1 Attempt the questions.

a) In the circuit given in Fig 1(a) if the voltage V+ and V- are to be amplified by the
same factor, the value of R should be ___________. (01)
i)3.3k Ω ii)33k Ω iii)330 Ω iv) None of these.
Justify. (04)

SOLUTION:

ii) 33 kΩ

The circuit above represents a subtractor circuit.

If RF=22kΩ, R1=10kΩ, R2=15kΩ

Then, = since input at both the terminals are to be amplified with same
gain.
22 × 10 𝑅
=
10 × 10 15 × 10

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 R= 33 kΩ

b) If the input to the ideal comparator shown in Fig 1(b) is a sinusoidal signal of 8
volt peak to peak without any DC component, then the duty cycle is of the output
comparator is ___________. (01)
i)33.33% ii)25% iii)20% iv) None of these.
Justify. (04)

SOLUTION:

i) 33.33%

The above circuit acts as an open loop non-inverting comparator with an input of
8V peak to peak.
Hence, Vm=4 V and VREF=2V.
To find the duty cycle we need to know the on time (TON) and off time (TOFF) of the
circuit above which can be obtained from input output waveform.
This waveform can be plotted by non-inverting op-amp properties as follows
When, Vin > VREF , Vo = +VSAT
Vin < VREF , Vo = -VSAT
Hence the waveform is

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From the output waveforms shown above, input signal crosses the reference point
of 2V at two points in the positive half cycle of input signal. Therefore at the two
crossing points we can have the equation-
4sinѲ=2

Ѳ=sin-1( )

Ѳ= 30˚
Thus at θ = 30̊, input signal crosses the reference point. Since there are two
reference points in the positive half cycle of input signal and both are
symmetric from both the ends. So we get two angles corresponding to two
crossings as follows,

Ѳ1 = 30˚-0˚ and Ѳ2=180 ˚ - 30 ˚

Ѳ1=30 ˚ and Ѳ2=150 ˚

Thus between θ1 = 30̊ to θ2 = 150̊ output voltage is high (+Vsat). The

complete cycle of input signal corresponds to θ = 360̊.
Thus the duty cycle of the output square wave can be represented as follows,

° ° °
Duty cycle = D = = = =
° °

D= 33.33%

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c) What is the frequency of IC 555 astable multivibrator shown in Fig 1(c)? (01)
i) 241 Hz ii) 178 Hz iii)78 Hz iv) 8 Hz.
Justify. (04)

SOLUTION:

i) 241 Hz

Here RA=103 Ω, RB=3×106Ω and C=10-9

Since this is an astable multivibrator frequency is given by

f= = ( )
= ) ( × ))×
. . ((

f = 241 Hz

d) An amplifier using OPAMP with slew rate SR=1 V/µs has a gain of 40 dB. If this
amplifier has to amplify sinusoidal signal of 20 KHz faithfully without any slew
rate induced distortion, then the input signal must not exceed ______. (01)
i)795 mV ii)395 mV iii)79.5 mV iv) 39.5 mV
Justify. (04)

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SOLUTION:

ii) 395 mV

Here SR= 1 V/µs = 106 V/s

Gain AVF=40
f=20 kHz = 20 × 103 Hz

Since, slew rate = 𝑚𝑎𝑥

We need to find Vo
Vo = AVF × Vm sin(ωt)
= 40 × Vm × sin(2×π×f×t)
= 40 × Vm × sin(2×π×20×103×t)
𝒅𝑽𝒐
= 𝑉𝑚 × 40 × 2 × 𝜋 × 20 × 10 × cos(2×π×20×103×t)
𝒅𝑻
𝒅𝑽𝒐
For to be maximum i.e. slew rate cos term should be 1.
𝒅𝑻
𝒅𝑽𝒐
Therefore, 𝑚𝑎𝑥 = 𝑉𝑚 × 40 × 2 × 𝜋 × 20 × 10
𝒅𝑻

106 = 𝑉𝑚 × 40 × 2 × 𝜋 × 20 × 10

Vm =
× × × ×

Vm=198.94mV
This is maximum amplitude, hence the peak to peak voltage becomes
Vp-p=2×Vm
Vp-p= 397.88mV.
Hence the input signal must not exceed 395mV.
Q.2.
a) Sketch the implementation of an instrumentation amplifier using three op-
amps and explain its operation. (10)

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SOLUTION:
An instrumentation amplifier can be implemented using 3 op-amps as shown in
the figure below.

Consider 3 op-amps A1, A2 and A3 where A1 and A2 act as non-inverting amplifier

such that their inverting terminal (-) is connected to resistor R2 instead of ground.
The input impedance of all the op-amps (A1, A2 and A3) is assumed to be infinite,
the currents flowing would be zero. Hence the current flowing through the
resistors R1, R2 and R3 is same i.e. ‘I’.
Using the concept of virtual short we can obtain the voltages at nodes A and B as
follows
VA = V2 and VB = V1
Hence the expression for current I is,

I= =

The output voltage of op-amp 2 (A2) is given by

Vo2 = VA + IR1 = V2 + IR1

= V2 + R1

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 =
( )
=

The output voltage of OP-AMP1 is given by

V01 = VB – IR1
= V1 – IR1

= V1 - x R1

=
Hence the output of the first stage is given by

V02 - V01 = -

V02 - V01 = [1 +
Therefore, the gain of the first state is given by

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 AV1 = =1+
The second stage is a difference amplifier with a gain of

AV2 =
Therefore, the overall gain AV of the three OP-AMP instrumentation amplifier is
given by,
AV = AV1 x AV2

∴ AV = [1 + X
Hence by using a variable resistor R2 the overall gain can be easily and linearly
varied.
The output voltage is then given by,
V0 = AV x (V1 – V2)
The triple OP-AMP instrumentation amplifier is available in IC form. For example,
ICAD522 or INA 101. These devices will contain all the components except the
variable resistance R2 shown in the figure above.
b) Compare Ideal and Practical op-amp. (5)
SOLUTION:

Sr.No. Characteristics Practical op-amp Ideal op-amp

value value
1 Input Resistance (Ri) 2 MΩ Infinite
2 Output Resistance (Ro) 75 Ω 0
3 Voltage gain (AV) 2 × 105 Infinite
4 Bandwidth B.W. 1 MHz Infinite
5 CMRR 90 dB Infinite
6 Slew rate (S) 0.5 V/µs Infinite
7 Input offset voltage (Vios) 2 mV 0
8 PSRR 150 µV/V 0
9 Input bias current (IB) 50 nA 0
10 Input offset current (Iios) 6 nA 0

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c) Explain current foldback protection in voltage regualtors. (5)
SOLUTION:

The circuit above shows a simplified circuit schematic of a discrete voltage

regulator with foldback current limiting technique, which actually decreases the
output current while operating in overload conditions.
The advantage of foldback current limiting is that it reduces the power dissipation
taking place in the series pass transistor Q1 under the short circuit condition as
compared to power dissipation taking place in short circuit current protection.
As seen in the schematic above R3 and R4 are added to the short circuit protection.
Transfer characteristics of foldback current limiting circuit is as shown below

Q.3.
a) Design a Schmitt trigger circuit to convert 5V, 1 kHz sinusoidal signal to square
wave using IC 741, VUT=0.8V VLT=-0.8V and ±VSAT = ±11V. Draw its transfer
characteristics, input and output waveforms.

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SOLUTION:
Data:
+VSAT = +11V , -VSAT = -11V , VUT=0.8V , VLT= -0.8V , Vin = 5V

f = 1 kHz = 103 Hz ∴ T= = = 1𝑚𝑠.

Let us assume R2 = 10kΩ

∴ VUT = ×𝑉

×
∴ 0.8 = × 11
×

R1 = 127.5 kΩ

With this values of R1 and R2 the desired inverting Schmitt trigger can be obtained.

The waveform of input and output can be given as follow

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Transfer characteristics of above Schmitt trigger is

b) With the help of circuit diagram, derive the expression of output analog voltage
for a weighted resistor DAC. (10)
SOLUTION:
The circuit diagram of binary weighted resistor type DAC is as shown below

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This consists of ‘n’ binary weighted resistors and ‘n’ SPTD (Single Pole Double
Throw) switches, whose position of moving arm is controlled by value of binary
input applied to it.
Let the n bit digital input word to the DAC be d1, d2, d3, …. dn with d1 as MSB (most
significant bit) and dn as LSB (least significant bit).
Let RF be the feedback resistor and Io be the output current. Let the op-amp be an
ideal op-amp so that the current flowing into its terminals is zero due to its infinite
input resistance.
Assuming the op-amp to be ideal , the output current Io can be expressed as sum
of individual currents through the weighted resistors (current going into op-amp is
zero).
Io = I1 + I2 + …. + In

∴ Io = 𝑑 + 𝑑 + ⋯+ 𝑑

Here 𝑑 , 𝑑 , … . , 𝑑 can have a value of ‘0’ or ‘1’.

Io = (𝑑 2 + 𝑑 2 + ⋯+ 𝑑 2 ) (eqn. 1)

The ouput voltage is given by

Vo = IoRF

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 This is the required
Vo = VR (𝑑 2 + 𝑑 2 + ⋯+ 𝑑 2 )
expression for output
analog voltage. (eqn. 2)

From eqn. 1 and eqn.2 we can conclude that,

K= and VFS = VR.

So if RF = R and K=1
Vo = VR(𝑑 2 + 𝑑 2 + ⋯+ 𝑑 2 )
By substituting values of d1, d2, d3, …. dn in above equation or eqn. 2 value of
corresponding analog output voltage Vo can be obtained.

Q.4.
a) Design an IC 555 astable multivibrator for an output frequency 1 kHz and a duty
cycle of 60%. (10)
SOLUTION:
Data:
Output frequency fo = 1kHz = 103 Hz
Duty cycle D= 0.60
Let us assume C = 0.01µF
.
fo =
( )
. .
∴RA + 2RB = =
× × . ×

RA + 2RB = 144000 ….(1)

Now, Duty cycle D =

0.6 = from equation (1)

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 RA + RB = 86400 ….(2)

On solving equation (1) and (2)

RA = 28.8 kΩ
RB = 57.6 kΩ
The circuit diagram of astable multivibrator as per above parameters is as given
below

b) With the help of a functional block diagram explain the working of voltage
regulator LM 317 to give an output voltage variable from 6V to 12V to handle
maximum load current of 500mA. (10)
SOLUTION:
1. Functional block diagram of positive adjustable voltage regulator LM 317 is as
shown below

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2. The functional block diagram above shows that LM 317 is a series regulator and
a Darlington pair acts as a series pass element.
3. The output voltage is compared with the internally generated voltage reference
to produce an error voltage which drives the Darlington transistor to regulate the
output voltage.
4. RLIMIT is an internal sensing resistance. The voltage across it is proportional to load
current. This voltage is applied to the internal protection circuitry.
5. If the load current exceeds beyond its maximum value, the Darlington pair will
be automatically turned off to protect the IC.
6. LM 317 is monolithic IC voltage regulator with an adjustable output voltage
which can supply more than 1.5A current to the load. Its output voltage is
adjustable over a range of 1.2V to 37V.
7. It employs the internal current limiting and thermal shutdown and safe area
compensation.
Data: Vo = 6V to 12V
IL(max) = 500mA
Let us assume maximum value of IADJ = 100µA and let R1 = 240Ω.
1. Calculate minimum and maximum values of R 2

Vo = 1.25 1 + +𝐼 𝑅

Vo = 1.25 1 + + 100 × 10 ×𝑅

For Vo = 6V i.e. minimum the corresponding value of R2 will be R2min

∴ 6 = 1.25 1 + + 10 ×𝑅

R2min = 894.48 Ω

For Vo = 12V , value of R2max will be

∴ 12 = 1.25 1 + + 10 ×𝑅

R2max = 2025.24 Ω

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Thus we want R2 to vary from 894.48 Ω to 2025.24 Ω. Hence we choose R2 to be a
series combination of a fixed resistor of 680 Ω and a potentiometer of 1k Ω value.
2. To obtain 500mA, we should use TO-3 package with 20W power consumption
rating.
3. Filter capacitors:
We assume that the regulator is close to the unregulated input supply. Hence the
input capacitor Ci is not to be used. But for better ripple rejection use capacitor
C2 = 10µF between adjustment terminal and ground. The output capacitor Co=1 µF
is also being used.
4. Protective diodes:
As the output voltage is less than 25V and capacitors are smaller than 25µF, it is not
necessary to use the protective diodes.
The minimum voltage drop across LM 317 is 3V. Hence the input voltage V in ≥ 13V.
Hence the complete designed Voltage regulator is as shown below:

Q.5.
a) Design a Wein bridge oscillator using op-amp to oscillate a frequency of 965 Hz
and explain the working of Wein bridge oscillator. (10)
SOLUTION:
fo = 965 Hz
Let us assume C= 0.01 µF = 0.01 ×10-6 F.

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To calculate value of R, R1 and RF:

fo =

∴R = =
× . × × . ×

R = 16.49kΩ.

Let R1=R

R1=16.49kΩ

RF ≥ 2R1

RF=32.98 kΩ

The designed Wein bridge oscillator is as follows:

Working of Wein bridge oscillator

1. A wein bridge oscillator with a non-inverting op-amp amplifier is as shown below

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2. The Wein bridge has 4 arms. The arm AD which contains a series of combination
of R and C, whereas arm CD contains a parallel combination of R and C.
This value of R and C is used to decide the value of oscillator frequency such that

f=
3. The resistors RF and R1 are used to generate a reference voltage which remains
constant independent of the frequency f.
4. The AC input voltage is applied between the points A and C of the bridge. When
Wein bridge is used in oscillator circuit, the feedback voltage is applied between
these points.
5. The AC output of the bridge is obtained between the points B and D which is
connected as inputs of the non-inverting amplifier.
6. The value of feedback factor β depends upon the frequency. At oscillator
frequency fo the phase shift introduced is zero and thus value of feedback factor β
is 1/3.
7. According to Barkhausen criteria the phase shift around the loop should be zero
and loop gain should be greater than 1.
i.e. |Aβ|≥1
substituting β=1/3, we get A≥3.
Therefore the gain of the amplifier should be greater than or equal to 3.

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b) List and explain the various performance parameters of DAC. (10)
SOLUTION:
1. Resolution:
 Resolution is defined as the smallest possible change in the analog output
voltage. Resolution should be as high as possible.
 Resolution depends upon the number of bits in digital input applied to DAC
such that Resolution=2n for n bits.
Therefore, Resolution increases with increase in number of bits.
 If VFS is the full scale analog output voltage then resolution of DAC is
Resolution =

2. Accuracy:
 Accuracy of a DAC indicates how close the analog output voltage is to
theoretical value or simply the deviation of actual output from theoretical
value.
 Accuracy depends upon the accuracy of the values of resistors used in the
ladder and the precision of the reference voltage used.
 Accuracy is always specified in terms of percentage of the full scale output.
That means maximum output voltage eg. If the full scale output is 15V and
accuracy is ±0.1% then the maximum error is given by 0.001 × 15= 0.015 V or
15mV.
3. Linearity:
 The relationship between the digital input and analog output is expected to
be linear. However practically it is not so due to error in the values of resistor
used for the resistive network.
4. Temperature Sensitivity:
 The ideal requirement is that analog output voltage of DAC should not
change due to changes in temperature. But practically analog output is a
function of temperature. It is so because the resistance values and op-amp
parameters change with changes in temperature.
5. Setting time:
 Theoretically the analog output voltage should change instantaneously as
soon as there is a change in the digital input.
 Practically the analog output of DAC does not change instantaneously. Due

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 to resistors and op-amp in the circuits, oscillations are observed at the
output.
 The time required to settle the analog output within ½ LSB of the final value,
from the instant of change in digital input is called as setting time.

 The setting time should be as small as possible.

6. Speed:
 It is defined as the time taken by a DAC to perform a conversion from
digital to analog.
 It is also defined as the number of conversions that can be performed per
second.
 Speed of a DAC should be as high as possible.
7. Long term drift:
 This results mainly due to resistor and semiconductor aging and can affect
all the characteristics. Characteristics mainly affected are speed, linearity,
etc.
8. Supply rejection:
 It indicates the ability of DAC to maintain all its important characteristics
unchanged when the supply voltage is varied. Supply rejection is usually
specified as percentage of full scale change at or near full scale at 25˚C.
9. Input-Output Equation:
 The input output equation of a DAC can be used to calculate the analog
output voltage corresponding to given digital input word.
 The output voltage (Vo) equation can be given as
Vo = K VR D
Where D is fractional binary value and is given as
D = ( d12-1 + d22-2 + …. + dn2-n )
Where d1 is MSB and dn is LSB.
 Or Vo can be simply given as
Vo = Resolution × D.
Q.6. Short notes on (Attempt any 4): (20)
a) Comparison of linear and switching regulators.
SOLUTION:

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Sr.No. Parameter Linear Regulator Switching Regulator
1 Circuit Diagram

2 Region of operation Active region Saturated or Cut-off

3 Switching No switching Transistor acts as a switch
4 Complexity Less High
5 Efficiency Low (40%) High (90%)
6 Switching frequency Very low Very high (25kHz)
7 Switching losses Zero Very high
8 RFI/EMI Absent Very high
9 Component stress High Very high
10 Regulation Excellent Good
11 Cost Lowest Moderate
12 Size/Weight Large/Bulky Small/Light weight
13 Power handling Low High
capacity

b) Active filters using opamp:

SOLUTION:
1. Active filters use active devices like op-amp and transistor along with the passive
components like resistor, capacitor or inductors.
2. An active low pass filter designed using op-amp can be shown as below
3. The RC circuit together forms a passive low pass filter since they are passive
elements.
4. The input Vin is applied to this RC circuit and the output Vo is applied back to
input of the amplifier.
5. In active filter op-amp is used as a non-inverting amplifier where R F and R1 can be
selected for desired value of passband gain such that
𝑅
𝐴 =1+
𝑅

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6. The frequency response of an active low pass filter can be given as

Features:
 It is possible to provide desired gain.
 The frequency response becomes more sharp.
 The passband and stopband can be separated clearly.
c) Precision Rectifiers:
SOLUTION:
1. In conventional rectifier circuits it is not possible to rectify AC voltages
below 0.6 volts, because the minimum voltage required to forward bias a
silicon diode is 0.6 volts as shown in graph below of forward characteristics
of silicon diode

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2. By using precision rectifiers it is possible to rectify the AC input voltages of very
small magnitudes even less than0.6 volts.
3. The distortion in precision rectifiers is reduced as compared to conventional
rectifiers. Also the transfer characteristics is linear.
4. Precision rectifiers have high impedance hence loading on the input source is
reduced.
5. There are two main classification of precision rectifier:
 Precision half wave rectifier (HWR)
 Precision full wave rectifier (FWR)
Precision half wave rectifier can be implemented using inverting and non-
inverting amplifier as well.
d) PLL IC 565:
SOLUTION:
1. PLL IC 565 is a 14 pin DIP and 10 pin metal can package. Pin configuration of
565 is as shown below

2. Functional block diagram of IC 565 is as shown below

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3. The free running frequency of VCO (i.e. when inputs 2 and 3 are grounded) is
given by
.
𝑓 = 𝐻𝑧

Where RT and CT are externally connected components to pin 8 or pin 9

respectively as shown in functional block diagram.
This externally connected RT can have a value between 2kΩ and 20kΩ whereas C T
can have any value.
4. To compare fi and fo pin 4 and pin 5 is connected externally.
5. The 3.6kΩ external resistor along with capacitor C connected between pin 7
and pin 10, such that value of this capacitor C should be sufficiently large to
minimize variation in output at pin 7.
6. The 565 PLL is capable of locking to and tracking an input signal over ±60%
bandwidth with respect to fo (center frequency).
7. The lock range fL of the PLL is given by

Lock range: ΔfL = ± 𝐻𝑧

Where f0= free running frequency of VCO in Hz

V=(+V) - (-V) volts.
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8. The expression for the capture range is given by:

∆
Capture range : ∆𝑓 = ±
( )( . )× ×

Where C is expressed in farads.

e) Widlar current source:
SOLUTION:
1. In other current sources the output current Io is approximately equal to
reference current IREF. To avoid this condition value of R should be as large as
1MΩ which is not possible to implement in an IC.
Therefore Widlar current source is used.
2. Widlar current source using transistors is represented as follows

Such that
 Both Q1 and Q2 are identical.
 β of both the transistors is large.
3. Due to voltage drop at RE the VBE1 of Q1 will always be less than VBE2 of
transistor Q2.
∴ VBE1 = VBE2.

4. As VBE1 is small, the value of IC1 will also be smaller which means that the output
(load) current Io will be smaller than IREF.
∴ Io < IREF.

Thus IB1 ≠ IB2 and IC1 ≠ IC2 for Widlar current source.

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5.Due to this asymmetric arrangement and nature of base and collector; V CC ,Q2
and R1 will establish a reference current IREF and then RE will determine difference
between IC1 and IREF.
6. Output resistance Ro at Q1 is given by

Ro ≈ r01(1 + gm1RE).

7. Advantages of Widlar current source:

 Smaller value of R1 for small values of Io therefore the fabrication of R1 on IC

chip becomes possible.
 Improved stability of Io against variation in VCE of output transistor.
 High output resistance.

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