Lecture 1

VLSI DESIGN FLOW: RTL TO
GDS
Lecture 1
Basic Concepts of Integrated Circuit: I
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Basic Concepts of Integrated Circuit
▪ Historical Perspective
▪ Structure
▪ Fabrication
▪ Designing vs. Fabrication
VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Art of Copying …
Charles Babbage, On the Economy of Machinery and

Manufactures, Chapter 11, 1832
“…sources of excellence in the work produced by machinery

depend on a principle…., and is one upon which the
cheapness of the articles produced seems greatly to
depend.
The principle alluded to is that of COPYING, taken in its

most extensive sense.”
Source:
https://commons.wikimedia.org/wiki/Fi
le:Charles_Babbage_-_1860.jpg, See
page for author, Public domain, via
Wikimedia Commons

VLSI: An Historical Perspective

VLSI: An Historical Perspective
Electronic Circuit: Increasing Integration:
▪ Various active and passive components ▪ Small-Scale Integration, Large-Scale
➢ Connecting discrete components Integration, Very Large-Scale Integration
become expensive, time-consuming,
and unreliable. Moore’s Prediction:
▪ Number of components in an IC realized at
Integrated Circuit: minimum cost will double every year
▪ Monolithic silicon chips containing several ➢ Later revised to double every two year
components
➢ IC Technology Shrinking Transistors:
IC Technology: ▪ Moore’s prediction enabled by the shrinking
sizes of transistors
▪ Several key inventions and discoveries
➢ 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, 16
➢ Photolithography nm ….
▪ Improving the speed, energy efficiency and
cost per transistor
▪ Designing an IC becomes more complicated
Structure of an Integrated
Circuit

Structure of Integrated Circuit (1)
▪ ICs are composed of multiple
layers
▪ Diffusion layer, implant layer,

metal layer etc.
▪ Bottom: devices
▪ Above devices: interconnect

layers of metal separated by
insulator
➢ Can be more than 10 such
metal layers
➢ Via is used to make
electrical connection
between different layers

Problem:
Connect points A1 to A2 and B1 to B2 using wires.
▪ Wires cannot go outside the rectangle shown.
▪ The wires are constrained to be in the plane containing

A1, A2, B1, B2.
What happens when the constraint of wires being in the

same plane is removed?

▪ Multiple layers are necessary to make connections between devices that would otherwise
short when connected in a single layer
▪ Layers defined by mask and fabricated using photolithography

Photolithography

Photolithography (1)
▪ Process of transferring geometric shapes that
are defined on a mask to the surface of a silicon
wafer
▪ Features marked on a glass plate with opaque

chrome thin films
➢ Also known as photomasks or reticles.
▪ For different layers of integrated circuits different

masks are used
▪ Photolithography is carried out for each layer

Photolithography (2)

Terminologies related to IC
Fabrication

Silicon Wafer and Ingots
Silicon Wafer:
▪ A silicon wafer is a thin slice of silicon that
serves as a substrate for an integrated circuit
▪ Currently, 300 𝑚𝑚 wafer are widely used
Silicon Ingots:
▪ Massive cylindrical single crystal of silicon
Source:
https://commons.wikimedia.org/wiki/File:I ▪ Silicon ingots are mostly prepared using
CC_2008_Poland_Silicon_Wafer_1_edit.png
FxJ, Public domain, via Wikimedia
Czochralski (CZ) process
Commons
➢ Pure seed crystal is pulled out from a
highly pure melted silicon at 1425℃
▪ A silicon wafer is sliced out from silicon ingots
Source: https://commons.wikimedia.org/wiki/File:Monokristalines_Silizium_f%C3%BCr_die_Waferherstellung.jpg,
German Wikipedia, original upload 7. Okt 2004 by Stahlkocher

Dies and Chips
Dies:
▪ Slices of silicon wafer containing the complete circuit are
called dies
▪ Hundreds of rectangular shaped integrated circuits are
fabricated on a single silicon wafer
▪ Dies are sliced out from silicon wafers after fabrication and
testing
Chips:
▪ After dies are sliced, they are encapsulated into a supporting
case for protection against physical and chemical damage.
▪ Packaged dies are generally known as chips

Designing vs. Fabrication

Designing vs. Fabrication
Designing:
▪ Determining the parameters and
composition of a circuit that can achieve
the desired functionality
Fabrication:
▪ It involves actual creation of integrated
circuit for a given design (layout of various
layers)

Semiconductor Foundries
Foundry:
▪ Semiconductor manufacturing plant where the fabrication of integrated circuits is done.
▪ Cost of setting-up and maintaining is very high.
▪ Sustainable only when the facilities of foundry are utilized close to their full potential

Semiconductor Industry: Business Model
Fabless Design Companies:
▪ Only designing, fabrication is outsourced
▪ Do not require to setup and maintain costly
foundries.
▪ Example: Qualcomm, Nvidia, etc.
Merchant Foundries:
▪ Only fabrication (for others)
▪ Draws business from many companies and
utilize foundry to full potential .
▪ Example: TSMC, UMC, GF, etc.
Integrated Device Manufacturers:
▪ Both designing and fabrication done in the same company
▪ Production is more efficient and cost-effective due to control over all the steps of the
process.
▪ Example: Intel, Samsung
Sharing Information between Design and Fabrication
Design and Fabrication:
▪ Related Task
▪ Share Information:
➢ Process Design Kit (PDK)
➢ Design (Layout)

References
▪ J. D. Plummer. “Silicon VLSI Technology: Fundamentals, Practice and Modeling”. Pearson
Education India, 2009.
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.
inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 21

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VLSI DESIGN FLOW: RTL TO

▪ Designing vs. Fabrication

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 2

Charles Babbage, On the Economy of Machinery and

“…sources of excellence in the work produced by machinery

The principle alluded to is that of COPYING, taken in its

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 3

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 4

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 6

▪ Diffusion layer, implant layer,

▪ Above devices: interconnect

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 7

Connect points A1 to A2 and B1 to B2 using wires.

▪ Wires cannot go outside the rectangle shown.

▪ The wires are constrained to be in the plane containing

What happens when the constraint of wires being in the

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 8

▪ Layers defined by mask and fabricated using photolithography

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 9

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 10

▪ Features marked on a glass plate with opaque

▪ For different layers of integrated circuits different

▪ Photolithography is carried out for each layer

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 11

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 12

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 13

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VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 15

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VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 18

Design and Fabrication:

VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 20

inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh 21

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