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    Lecture 38

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    Thanushsaran S

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    © All Rights Reserved
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    Lecture 38

    Uploaded by

    Thanushsaran S
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    3 views12 pages

    Lecture 38

    Uploaded by

    Thanushsaran S

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    © All Rights Reserved
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    of 12

    VLSI DESIGN FLOW: RTL TO

    GDS

    Lecture 38
    Chip Planning - II
    Sneh Saurabh
    Electronics and Communications
    Engineering
    IIIT Delhi
    Lecture Plan
    ▪ Chip Planning
    ➢ Hierarchical Design Methodology
    ➢ Floorplanning
    ➢ Power Planning

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Large Object (Macro) Placement
    ▪ Placement of large objects undertaken during
    floorplanning
    ➢ Blocks (obtained in partition), RAM, analog
    blocks (such as PLL), etc.
    ▪ Placement of standard will be undertaken during
    placement stage
    ▪ Initial macro placement is guided by connectivity
    ➢ Strongly connected macros placed close
    together
    ➢ Fly lines can guide the floorplan
    ➢ Macros interacting with external world close
    to I/O pads
    ▪ Predictive routing (rough routing) can be done to
    get an initial idea of problem in the floorplan

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Macros Placement: Guidelines (1)
    ▪ Some guidelines can help in obtaining good floorplan

    ▪ Allot contiguous region for


    ▪ Avoid narrow channels between macros
    standard cells

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Macros Placement: Guidelines (2)
    ▪ Add halos around corners
    ➢ Halos are placement blockages

    Use flexibility of:


    ▪ Orientation: reflection, rotation by 90°
    ▪ Shapes: rectilinear
    ▪ Pin assignment: locations of movable pins

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Floorplanning: Standard Cell Rows
    ▪ Height of standard cell rows is equal to the
    height of the standard cells in the library
    ➢ Multiple rows of different heights
    created can also be created

    ▪ Standard cell rows generally created by


    abutment
    ▪ Rows are created oriented in alternating
    180-degree rotation

    ▪ Routing channels can be created between


    rows to avoid congestion

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Power Planning

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Power Planning: Components

    ▪ Power Pads: Supply power to the


    chip from the external world

    ▪ Power Rings: carry power around the


    periphery of the die
    ➢ Usually use top metal layers
    ➢ Power Delivery Network (PDN)
    built in the core area

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Power Delivery Network (PDN)
    Mesh Grid Topology:
    ▪ Popular topology for PDN
    ▪ Rails and straps usually organized as a uniformly
    spaced array

    Advantages of mesh grid topology


    ▪ Provides low resistance
    ▪ Reliability increases
    ▪ Uniform current distribution

    Design Parameters:
    ▪ Layers in which the grid spans
    ▪ Width and spacing of wires

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Electromigration
    Electromigration
    ▪ Flow of unidirectional current in a metal can causes transport of metal mass in the direction
    opposite to current flow
    ▪ Ions gain momentum from electrons
    ▪ May eventually lead to shorts and open

    ▪ PDN prone to electromigration


    ▪ Current in PDN needs to be kept within limit defined by process technology
    ➢ Ensure conductor size is adequate
    ➢ Ensure there are no current density “hot spots”

    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh


    Voltage Drop
    Cause of Voltage Drop: Impact on Performance
    ▪ Resistance (𝑅): between supply voltage ▪ Slows down signal propagation along the
    origin and load path
    ▪ Inductance (𝐿): mainly between package- ▪ Maximum frequency at which a circuit will
    to-die interconnection operate is limited
    ▪ Static and Dynamic Voltage Drop ▪ Need to perform voltage drop analysis in
    𝑑𝑖 both static and dynamic conditions
    𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = 𝑖𝑅 + 𝐿
    𝑑𝑡 ➢ Fix IR drop hotspots

    Decoupling Capacitors (Decap Cells)


    ▪ Capacitors inserted between power and
    ground wires
    ➢ Acts as local charge storage
    ➢ Placed on die at strategic locations
    ▪ Demerits: increase die area and leakage
    power dissipation
    ▪ Number of decap cells, size and
    placement should be optimized
    VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh
    References
    ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
    2023.

    soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh

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