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UNIT-1
IC FABRICATION

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CONTENT
TECHNICAL TERMS
1.1 CLASSIFICATION OF INTEGRATED CIRCUITS
1.1.1Monolithic ICS
1.1.2Thin and Thick Film ICS
1.1.3Thin-Film ICS
1.1.4Thick-Film ICS
1.1.5 Hybrid or Multi-Chip ICS.
1.2 PREPARATION OF THE SILICON WAFER MEDIA
1.2.1 Czochralski Crystal Growth Process
1.3 EPITAXIAL GROWTH
1.4 INSULATION LAYER
1.4.1 Active Mask or Isolation Mask (thin-ox)
1.4.2 Local Oxidation of Silicon (LOCOS)
1.5 PHOTOLITHOGRAPHY
1.5.1 Isolation Diffusion.
1.5.3 Emitter Diffusion
1.6 ION IMPLANTATION
1.6.1 Ion Implantation System
1.7 ALUMINUM METALLIZATION
1.8 INTEGRATED TRANSISTORS
1.9 INTEGRATED DIODE
1.10TRANSISTOR CONNECTED AS DIODE
1.11 INTEGRATED CAPACITORS
1.12 INTEGRATED RESISTOR
1.13 PACKAGING
1.14 DESIGN RULES ARISES DUE TO MANUFACTURING PROBLEMS
1.15 DIODE & TRANSISTOR FABRICATION
1.16 FET, CAPACITANCE & RESISTOR FABRICATION
1.17 CMOS & MOSFET FABRICATION
1.18 MONOLITHIC IC
EXAMPLE PROBLEMS
QUESTION BANK
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TECHNICAL TERMS
1. Silicon (Si): A gray, tetravalent, nonmetallic chemical element occurring abundantly in
nature making up 27.8% of earth's crust.
2. Shaping: Finished mono crystalline ingot is ground to a rough size diameter and is either
"notched" or "flatted" along its length to indicate the orientation of the ingot.
3. Slicing: Ingots are sliced into wafers using a diamond ID saw.
4. Edge grinding: An important step in the manufacturing of silicon wafer to reduce wafer
breakage in the remaining manufacturing processes or future device manufacturing
processes.
5. Lapping: Lapping removes saw marks and defects from the surface of the wafers, while
also thins and relieves stress accumulated in the wafer from the slicing process.
6. Etching and cleaning: Using sodium hydroxide or acetic and nitric acids, the microscopic
cracks and surface damage caused by lapping are removed
7. Final Cleaning: This step is to remove trace metals, residues, and particles on the wafers
8. Final sort and inspection: Wafers are inspected to meet customer's specifications.
9. P-Type Wafer: Have Boron as main Dopant. Can be P+ or P- depending on dopant level.
P-type wafers can have 100 or 111 orientation. 111 orientation wafers are normally used in
Bi-polar devices.
10. N-Type Wafer: Have Phosphorous, Antimony or Arsenic as main dopants. Can be N+ or
N- depending on dopant level. The most common N-type wafer is doped with either An or P.
11. Dopant: An element that contributes an electron to a conduction process, thus altering
the conductivity.
12.Total Thickness Variation (TTV): The difference between the thickest and thinnest
points.
13. Bow: Measure how concave or convex the deformation of the median surface of the
wafer at the center point, independent of any thickness variations.
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14. Warp: The difference between the maximum and minimum values of the median surface
from an established reference plane.
15. Global Total Indicated Reading (GTIR): The maximum peak-to-valley deviation of a
wafer surface as measured from a specified reference plane.
16. Site Total Indicated Reading (STIR): Site by site measurement of the flatness of a
wafer.
17. Resistivity: Measurement of difficulty that charged carriers have in moving through the
wafer.
18. Primary Flat: The longest flat on the wafer.
19. Secondary Flat: The shorter flat on the wafer.
20. Particles: Unwanted impurities on the surface of the wafer.
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1.1 CLASSIFICATION OF INTEGRATED CIRCUITS
An integrated circuit (IC) consists of several interconnected transistors, resistors, capacitors
etc., all contained in one small package with external connecting terminals. The circuit may
be entirely self-contained, requiring only input and output connections and supply voltage to
function. Alternatively, a few external components may have to be connected to make the
circuit operative.
On the basis of fabrication techniques used, the ICs can be divided into following three
classes.
1.1.1Monolithic ICS

Figure 1.1 Monolithic ICS
The word monolithic is derived from the Greek monos, meaning single and lithos,
meaning stone. Thus monolithic circuit is built into a single stone or single crystal i.e. in
monolithic ICs, all circuit components, (both active and passive) and their interconnections
are formed into or on the top of a single chip of silicon. This type of technology is ideal for
manufacturing identical ICs in large quantities and, therefore, provides lowest per unit cost
and highest order of reliability. Monolithic ICs are by far the most common type of ICs used
in practice, because of mass production, lower cost and higher reliability. [Figure 1.1, 1.2]

Figure1.2 Monolithic ICS
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Since their invention, manufacturers have been manufacturing monolithic ICs to carry out all
types of functions. Commercially available ICs of this type can be used as amplifiers, voltage
regulators, crowbars, AM receivers, TV circuits, and computer circuits. However, the
monolithic circuits have the following limitations or drawbacks:
Low power rating. Since monolithic ICs are of about the size of a discrete small-signal
transistor, they typically have a maximum power rating of less than 1 watt. This limits their
use to low-power applications.
Poorer isolation between components.
No possibility of fabrication of inductors.
Small range of values of passive components used in the ICs.
Lack of flexibility in circuit design as for making any variation in the circuit, a new set of
masks is required.
1.1.2Thin and Thick Film ICS

Figure1.32Thin and Thick Film ICS
These devices are larger than monolithic ICs but smaller than discrete circuits. These ICs can
be used when power requirement is comparatively higher. With a thin-or thick-film IC, the
passive components like resistors and capacitors are integrated, but the transistors and diodes
are connected as discrete components to form a complete circuit. Therefore, commercially
available thin- and thick-film circuits are combination of integrated and discrete components.
The essential difference between the thin- and thick-film ICs is not their relative thickness but
the method of deposition of film. Both have similar appearance, properties and general
characteristics. [Figure1.3]


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1.1.3Thin-Film ICS
They are fabricated by depositing films of conducting material on the surface of a glass or
ceramic base. By controlling the width and thickness of the films, and by using different
materials selected for their resistivity, resistors and conductors are fabricated. Capacitors are
produced by sandwiching a film of insulating oxide between two conducting films. Inductors
are made by depositing a spiral formation of film. Transistors and diodes can be produced by
thin-film technology; but usually tiny discrete components are connected into the circuit.
One method used for producing thin films is vacuum evaporation in which vaporized material
is deposited on a substrate contained in a vacuum. In another method, called cathode
sputtering, atoms from a cathode made of the desired film material are deposited on a
substrate located between a cathode and an anode.
1.1.4Thick-Film ICS
They are sometimes referred to as printed thin-film circuits. In their manufacturing process
silk-screen printing techniques are used to create the desired circuit pattern on a ceramic
substrate. The screens are actually made of fine stainless steel wire mesh, and the inks are
pastes having conductive, resistive, or dielectric properties. After printing, the circuits are
high temperature-fired in a furnace to fuse the films to the substrate. Thick-film passive
components are fabricated in the same way as those in thin-film circuits. As with thin-film
circuits, active components are added as separate devices. A portion of thick-film circuit is
given in figure.ICs produced by thin-or thick film techniques have the advantages of forming
passive components with wider range and better tolerances, better isolation between their
components, greater flexibility in circuit design and of providing better high-frequency
performance than monolithic ICs.
However, such ICs suffer from the drawbacks of larger physical size, comparatively higher
cost and incapability of fabrication of active components.




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1.1.5 Hybrid or Multi-Chip ICS.

Figure1.4. Hybrid or Multi-Chip ICS
As the name implies, the circuit is fabricated by interconnecting a number of individual chips.
The active components are diffused transistors or diodes. The passive components may be
group of diffused resistors or capacitors on a single chip, or they may be thin-film
components. Wiring or a metalized pattern provides connections between chips. Hybrids ICs
are widely used for high power audio amplifier applications from 5 W to more than 50 W.
The structure of a hybrid or multi-chip IC is shown in figure. Like thin- and thick-film ICs,
hybrid ICs usually has better performance than monolithic ICs. Although the process is too
expensive for mass production, multi-chip techniques are quite economical for small quantity
production and are more often used as prototypes for monolithic ICs. [Figure1.4.]
On basis of chip size
ICs can also be classified on the basis of their chip size as given below:
1. Small scale integration (SSI)3 to 30 gates/chip.
2. Medium scale integration (MSI)30 to 300 gates/chip.
3. Large scale integration (LSI)300 to 3,000 gates/chip.
4. Very large scale integration (VLSI)more than 3,000 gates/chip.
On the basis of applications
ICs are of two types namely, linear ICs and digital ICs.
When the input and output relationship of a circuit is linear, linear ICs are used. An important
application of linear IC is operational amplifier commonly referred to as op-amp. As it was
originally designed for performing mathematical operations such as summation, subtraction,
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multiplication, differentiation, integration, sign changing etc. so it was named OP-AMP.
Though now-a-days it has numerous usages (such as scale changing, analog computer
operations, in instrumentation and control systems and in various phase-shift and oscillator
circuits) but still it is known by old popular name op-amp.
When the circuit is either in on-state or off-state and not in between the two, the circuit is
called the digital circuit. ICs used in such circuits are called the digital ICs. They find wide
applications in computers and logic circuits.
1.2 PREPARATION OF THE SILICON WAFER MEDIA
Wafer products are measured at various stages of the process to identify defects inducted by
the manufacturing process. This is done to eliminate unsatisfactory wafer materials from the
process stream and to sort the wafers into batches of uniform thickness and at a final
inspection stage. These wafers will become the basic raw material for new integrated circuits.
The following is a summary of the steps in a typical wafer manufacturing process.
Crystal Growth and Wafer Slicing Process
The first step in the wafer manufacturing process is the formation of a large, perfect silicon
crystal. The crystal is grown from a seed crystal that is perfect crystal. The silicon is
supplied in granular powder form, and then melted in a crucible. The seed is immersed
carefully into the crucible of molten silicon, and then slowly withdrawn.
Step 1: Obtaining the Sand
The sand used to grow the wafers has to be a very clean and good form of silicon. For this
reason not just any sand scraped off the beach will do. Most of the sand used for these
processes is shipped from the beaches of Australia.
Step 2: Preparing the Molten Silicon Bath
The sand (SiO
2
) is taken and put into a crucible and is heated to about 1600C just above its
melting point. The molten sand will become the source of the silicon that will be the wafer.
Step 3: Making the Ingot
A pure silicon seed crystal is now placed into the molten sand bath. This crystal will be
pulled out slowly as it is rotated. The dominant technique is known as the Czochralski (cz)
method. The result is a pure silicon cylinder that is called an ingot.



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1.2.1 Czochralski Crystal Growth Process
Make sure that the inside of the machine is very clean too and that the gas flow - the gas you
introduce but also the SiO coming from the molten Si because parts of the crucible dissolve -
does not interfere with the growing crystal.
Dissolve the Si in the crucible and keep its temperature close to the melting point. Since you
cannot avoid temperature gradients in the crucible, there will be some convection in the
liquid Si. You may want to suppress this by big magnetic fields.
Insert your seed crystal, adjust the temperature to "just right", and start withdrawing the seed
crystal. For homogeneity, rotate the seed crystal and the crucible. Rotation directions and
speeds and their development during growth, are closely guarded secrets!
First pull rather fast - the diameter of the growing crystal will decrease to a few mm. This is
the "Dash process" ensuring that the crystal will be dislocation free even though the seed
crystal may contain dislocations. [Figure1.5]
Now decrease the growth rate - the crystal diameter will increase - until you have the desired
diameter and commence to grow the commercial part of your crystal at a few mm/second.

Figure 1.5 Czochralski Crystal
The radial and lateral doping level is influenced - it will not stay constant without some
special measures
The concentration of impurities, especially interstitial oxygen, may change. In general, the
concentration increases from "head" to "tail".
Crystal lattice defects still present may change in size and distribution.
So you must do something - change the rotation speeds, the temperature, the growth speed -
whatever.
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This is where crystal growing becomes an art - and you will not find much literature about
this. This is the tricky and secret part: Changing all important parameters continuously so
that the crystal is homogeneous.[ Figure1.6.]

Figure1.6. Czochralski Crystal
But you cannot simply pull out the crystal after the desired length has been reached. The
thermal shock of the rapidly cooling end would introduce large temperature gradients in the
crystal which in turn produce stress gradient - plastic deformation (easy in Si at high
temperatures) will take place and this means dislocation are nucleated and driven into the
crystal.
The dislocation will even run up into the formerly dislocation free part of the crystal,
destroying your precious Silicon. [Figure1.7.]
So you withdraw gradually by just increasing the pulling rate a little bit which will lead to
a reduced diameter. The crystal then ends in an "end cone" similar to the "seed cone".

Figure1.7. Czochralski Crystal
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Here is a picture of a state-of-the-art 200 mm Si crystal as they are grown by the thousands
for present day (2000) chip manufacture. [Figure1.8.]
While it does look like oversized chromium-plated salami, it is a much more sophisticated
product (and much more expensive).


Figure1.8. Chip Manufacture Process
Note that this huge crystal is hanging on a rather thin Si seed crystal (see inset). This seed
crystal does not only have to support the weight of the crystal, but also the torque needed to
rotate the crystal during its growth.
Step 4: Preparing the Wafers
After the ingot is ground into the correct diameter for the wafers, the silicon ingot is sliced
into very thin wafers. This is usually done with a diamond saw.

A diamond saw for cutting wafers
Each of these wafers will then go through polishing until they are very smooth and just the
right thickness (see Polishing Process, below). [Figure 1.9.]


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Figure 1.9. Manufacturing Process

Thickness Sorting
Following slicing, silicon wafers are often sorted on an automated basis into batches of
uniform thickness to increase productivity in the next process step, lapping. During thickness
sorting, the wafer manufacturer can also identify defect trends resulting from the slicing
process.
Lapping & Etching Processes
Lapping removes the surface silicon which has been cracked or otherwise damaged by the
slicing process, and assures a flat surface. Wafers are then etched in a chemically active
reagent to remove any crystal damage remaining from the previous process step.
Thickness Sorting and Flatness Checking
Following lapping or etching, silicon wafers are measured for flatness to identify and control
defect trends resulting from the lapping and etching processes. Wafers are also often sorted
on an automated basis according to thickness in order to increase productivity in the next
process step, polishing.
Polishing Process
Polishing is a chemical/mechanical process that smoothes the uneven surface left by the
lapping a detching processes and makes the wafer flat and smooth enough to support optical
photolithography.

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A wafer polishing machine Wafers in storage trays Final Dimensional and Electrical
Properties Qualification
The wafers undergo a final test, performed in order to demonstrate conformance with
customer specification for flatness, thickness, resistivity and type. Process induced defect and
defect trend information is used by the wafer manufacturer for yield and process
management of the immediately preceding steps. Information regarding surface defects, such
as scratches and particles, and defect trend information are used by the wafer manufacturer
for yield and process improvement.

1.3 EPITAXIAL GROWTH


Figure1.10. Epitaxial growth
Silicon is most commonly deposited by dosing with silicon tetrachloride and hydrogen at
approximately 1200 C:
SiCl
4
(g) + 2H
2
(g) Si(s) + 4HCl(g)
This reaction is reversible, and the growth rate depends strongly upon the proportion of the
two source gases. Growth rates above 2 micrometres per minute produce polycrystalline
silicon, and negative growth rates (etching) may occur if too much hydrogen chloride
byproduct is present. (In fact, hydrogen chloride may be added intentionally to etch the
wafer.) An additional etching reaction competes with the deposition reaction:
SiCl
4
(g) + Si(s) 2SiCl
2
(g)
Silicon VPE may also use silane, dichlorosilane, and trichlorosilane source gases. For
instance, the silane reaction occurs at 650 C in this way:
SiH
4
Si + 2H
2

This reaction does not inadvertently etch the wafer, and takes place at lower temperatures
than deposition from silicon tetrachloride. However, it will form a polycrystalline film unless
tightly controlled, and it allows oxidizing species that leak into the reactor to contaminate the
epitaxial layer with unwanted compounds such as silicon dioxide. [Figure1.10.]
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VPE is sometimes classified by the chemistry of the source gases, such as hydride VPE and
metal organic VPE.
On the high resistivity P-type substrate a low resistivity 25 a m thick layer of N-type is
epitaxial grown. For this purpose, the wafers are placed in a diffusion furnace at 1,200 C
and a gas mixture of silicon atoms and pentavalent atoms is passed over the wafers. This
forms a thin layer of N- type semiconductor on the heated surface of the substrate, as shown
in figure. It is this epitaxial layer that all active and passive components of an IC are formed.
This layer ultimately becomes the collector for a transistor or an element for a diode or a
capacitor. The resistivity of P-type substrate for NA = 1.4 x10
21
atoms/m
3
is typically 10
ohm-cm. The resistivity of N-type epitaxial layer is suitably chosen in the range of (0.1 0.5)
ohm-cm. This layer is finally polished and cleaned. [Figure1.11]

Figure 1.11 System for growing Silicon epitaxial films

1.4 INSULATION LAYER
Oxide grown on silicon may result in an uneven surface due to unequal thickness of oxide
grown from same thickness of silicon. Stress along the edge of an oxidized area may produce
severe damage in the silicon. To relieve this stress, the oxidation temperature must be
sufficiently high to allow the stress in the oxide to relieve by viscous flow. In the LOCOS
process, the transistor area is masked by SiO
2
/SiN sandwich and the thick field oxide is then
grown. The oxide grows in both the directions vertically and also laterally under the
sandwich and results in an encroachment into the gate region called as bird's beak.
Si+2H
2
O SiO
2
+ 2H
2

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Figure 1.12 Formation of bird's beak
This reduces the active area of the transistor and specially the width. Some improvements in
the LOCOS process produce Bird's crest which reduces the encroachments, but it is non-
uniform. The goal is to oxidize Si only locally, whenever a field oxide is needed. [Fig 1.12]

This is necessary for the following reasons:
Local oxide penetrates into the Si, so the Si-SiO
2
interface is lower than the source-drain
regions to be made later. This could not be achieved with oxidizing all of the Si and then
etching of unwanted oxide.
For device performance reasons, this is highly beneficial, if not absolutely necessary.

1.4.1 Active Mask or Isolation Mask (thin-ox)
It describes the areas where thin oxides are needed to implement the transistor gates and
allow implantations to form P/N type diffusions. A thin layer of SiO
2
is grown and covered
with SiN and this is used as mask. The bird's bead must be taken into account while
designing thin-ox.

1.4.2 Local Oxidation of Silicon (LOCOS)
During etching, anything irregular becomes more irregular. So we grow oxide fields
50% above and 50% below the wafer. This is called LOCal Oxidation of Silicon(LOCOS).

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Figure 1.13 Formations of LOCOS

Creation of LOCOS
0.45 mU of silicon, when oxidized, becomes 1 mU of SiO2 because of change in
density. When field oxides are grown, there is an encroachment of the oxide layer in the
active transistor region below the gate oxide, because of the affinity of the SiO2 gate oxide
for oxygen. The resulting structure resembles a bird's beak (as shown in figure 1.14) . This
affects the device performance.

Figure 1.14 bird's beak
If we use Si3N4 as the gate dielectric, it will not let oxygen pass through. But due to
mismatch of the thermal coefficients of Si and Si3N4, hence the resulting stress produces a
non-planar structure called bird's crest(as shown in figure 1.15,16) .

Figure 1.15 bird's creast

The thermal coefficients of Si and SiO
2
match. So when Si
3
N
4
is used as the gate dielectric,
we first grow a thin oxide layer underneath. The stress, which would otherwise be generated
on the account of the difference in the thermal coefficients of Si and SiO
2
is now reduced.
Since SiO2 is now there, bird's beak will be formed.

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Figure 1.16 Comparison of the LOCOS process with and without some sacrificial
polysilicon
1.5 PHOTOLITHOGRAPHY
Photolithography is the method that sets the surface dimensions (horizontal) of various parts
of devices and circuits. Its goal is twofold. First goal is to create in and on the wafer surface a
pattern whose dimensions are as close to the device requirements as possible. This is known
as resolution of images on the wafer and the pattern dimensions are known as feature or
image sizes of the circuit. Second goal is the correct placement called alignment or
registration of the circuit patterns on the wafer. The entire circuit patterns must be correctly
placed on the wafer surface because misaligned mask layers can cause the entire circuit to
fail. In order to create patterns on the wafer, the required pattern is first formed in the
reticules or photo masks. The pattern on reticle or mask is then transferred into a layer of
photo resist. Photo resist is a light sensitive material similar to the coating on a regular
photographic film. Exposure to light causes changes in its structure and properties. If the
exposure to light causes photo resist changing from a soluble to insoluble one, it is known as
negative acting and the chemical change is called polymerization. Similarly, if exposure to
light causes it change from relatively non-soluble to much more soluble, it is known as
positive acting and the term describing it is called as photo solubilisation. The exposure
radiation is generally UV and E-beam. Removing the soluble portions with chemical solvents
called developers leaves a pattern on the photoresist depending upon the type of mask used.
A mask whose pattern exists in the opaque regions is called clear field mask. The pattern
could also be coded in reverse, and such masks are known as dark field masks.

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Figure 1.17 Clear Field mask
The result obtained from the photo masking process from different
combinations of mask and resist polarities is shown in the following table:

Figure 1.18 Dark Field mask
The second transfer takes place from the photo resist layer into the wafer surface layer. The
transfer occurs when etchants remove the portion of the wafer's top layer that is not covered
by the photo resist. The chemistry of the photo resists is such that they do not dissolve in the
chemical etching solutions; they are etching resistant; hence the name photo resists. The
etchant generally used to remove silicon dioxide is hydrogen fluoride (HF).
The choice of mask and resist polarity is a function of the level of dimensional control and
defect protection required to make the circuit work. For example, sharp lines are not
obtainable with negative photo resists while etchants are difficult to handle with positive
photo resists. After the pattern has been taken on resist, the thin layer needs to be etched.
Etching process is used to etch into a specific layer the circuit pattern that has been defined
during the photo masking process. For example, aluminum connections are obtained after
etching of the aluminum layer.

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Figure1.19 Fabrication Process
Photo resist Polarity
Negative Positive
Clear Field Hole Island
Dark Field Island Hole
Table 1.1 Photo resist Polarity
1.5.1 Isolation Diffusion.
SiO
2
layer is removed from the desired areas (four selected portions from the wafer, as
illustrated in Figure using photolithographic etching process explained above. The remaining
Si02 layer serves as mask for the diffusion of acceptor impurities. The wafer is now
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subjected to isolation diffusion at a suitably high temperature and for appropriate time period
allowing P-type impurity (boron in this case) to penetrate into the N-type epitaxial layer
through the openings in SiO
2
layer and ultimately reach the P-type substrate. The temperature
and time period of diffusion are required to be carefully controlled. The process results in
formation of N-type regions, called the isolation islands. The name is given as they are
separated by back-to-back P-N junctions. Their purpose is to permit electrical isolation
between various components of IC. Each electrical element is later on formed in a separate
isolation island. The bottom of the N-type isolation island ultimately forms the collector of
an N-P-N transistor. The P-type substrate is always kept negative with respect to the isolation
islands and provided with reverse bias at P-N junctions. If P-N junctions are forward biased,
the isolation will get lost.

Figure1.20. Isolation Diffusion
Isolation diffusion is controlled so as to cause high acceptor concentration P+ (typically NA
= 5 x 10
26
atoms/m
3
) in the region between the isolation islands. This concentration is much
higher than that of P-type substrate. This is for preventing the depletion region of the reverse-
biased isolation island-to-substrate junction from extending into P+ region and from possibly
connecting two adjacent isolation islands. Two adjoining isolation islands are connected to
the P-type substrate by a barrier capacitance or transition capacitance. This is undesirable and
is called the parasitic Capacitance. It adversely affects the performance of the IC and puts a
limitation on its use. The parasitic capacitance has two components; the capacitance C
1
from
the bottom of the re type region to the substrate and capacitance C
2
from the sidewalls of the
isolation islands to the P-region. The bottom component C
t
is essentially due to step junction
formed by epitaxial growth and, therefore, varies as the square root of the voltage V between
the isolation region and substrate (i.e.C
1
is directly proportional to V). The sidewall
capacitance C
2
is associated with a diffused graded junction and so varies as V
-1/2
. The total
capacitance is of the order of a few pF.


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1.5.2 Base Diffusion
During this process a new layer of SiO
2
is formed over the wafer. The new pattern of
openings is created depending upon the circuit needs. In these openings P-type impurities
like boron are diffused under regulated environments to form P-regions. This forms the base
region of an N-P-N transistor or as well as resistors, the anode of diode, and junction
capacitor. In this case, the diffusion time is so controlled that the P-type impurities do not
reach the substrate. The resistivity of the base layer is usually much higher than that of the
isolation regions.

Figure1.21. base Diffusion
1.5.3 Emitter Diffusion
A layer of SiO
2
is again formed over the entire surface and openings in the P-type regions, as
shown figure, are formed again by employing masking and etching processes. The N-type
impurities like phosphorous are then diffused through these windows under controlled
environments to form the transistor emitters, the cathode regions for diodes, and junction
capacitors. Additional windows (such as W
1
and W
2
in figure) are usually made into the N-
regions to permit aluminum metallic connections.

Figure 1.22. Emitter Diffusion
1.6 ION IMPLANTATION
Ion Implantation is an alternative to deposition diffusion and is used to produce a shallow
surface region of dopant atoms deposited into a silicon wafer. This technology has made
significant roads into diffusion technology in several areas. In this process a beam of
impurity ions is accelerated to kinetic energies in the range of several tens of kV and is
directed to the surface of the silicon. As the impurity atoms enter the crystal, they give up
their energy to the lattice in collisions and finally come to rest at some average penetration
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depth, called the projected range expressed in micro meters. Depending on the impurity and
its implantation energy, the range in a given semiconductor may vary from a few hundred
angstroms to about 1micro meter. Typical distribution of impurity along the projected range
is approximately Gaussian. By performing several implantations at different energies, it is
possible to synthesize a desired impurity distribution, for example a uniformly doped region.

1.6.1 Ion Implantation System
A typical ion-implantation system is shown in the figure below.


Figure1.23 Ion Implantation System
A gas containing the desired impurity is ionized within the ion source. The ions are generated
and repelled from their source in a diverging beam that is focused before if passes through a
mass separator that directs only the ions of the desired species through a narrow aperture. A
second lens focuses this resolved beam which then passes through an accelerator that brings
the ions to their required energy before they strike the target and become implanted in the
exposed areas of the silicon wafers. The accelerating voltages may be from 20 kV to as much
as 250 kV. In some ion implanters, the mass separation occurs after the ions are accelerated
to high energy. Because the ion beam is small, means are provided for scanning it uniformly
across the wafers. For this purpose the focused ion beam is scanned electrostatic ally over the
surface of the wafer in the target chamber.
Repetitive scanning in a raster pattern provides exceptionally uniform doping of the wafer
surface. The target chamber commonly includes automatic wafer handling facilities to speed
up the process of implanting many wafers per hour.


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Properties of Ion Implantation
The depth of penetration of any particular type of ion will increase with increasing
accelerating voltage. The penetration depth will generally be in the range of 0.1 to 1.0 micro
meters.

1.7 ALUMINUM METALLIZATION
For making electrical connection between various components of the IC, several windows
are opened on a newly created SiO
2
layer. Now a thin layer of aluminum is deposited on the
entire top surface. Further, photo resist technique is used to etch away all the unwanted
aluminum areas. The structure then provides the connected strips to which leads are attached,
as illustrated in figures represents the complete IC layout of the circuit shown in figure.

Figure1.24 Aluminum Metallization
1.8 INTEGRATED TRANSISTORS
Epitaxial growth

Figure1.25.

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Create SiO
2
(oxidation)

Figure1.26.
Open window in SiO
2
and perform boron diffuse to create P-layer.

Figure1.27.

Oxidation again, open window in new SiO
2
layer perform phosphorus diffusion to
create N-layer.


Figure1.28.
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Oxidize again, open windows for base, emitter and collector contact. Metallization
deposit Al, remove all except in contact regions.

Figure1.29.
Step-1: First of all an N-type silicon layer of about 5 to 25 m (1 m = 10-6 m) thick is
grown on the P-type substrate. The N-type layer is grown by placing the wafer in a special
furnace called reactor at 900 to 1200C. This process is called Epitaxial as shown in Figure
(1.25).
Step-2: A thin layer of silicon dioxide SiO2 is grown over the N-type layer by exposing the
wafer of an oxygen atmosphere at about 1000C. The thickness of silicon dioxide SiO2 layer
is generally in the range of 0.02 to 2 m. This layer is commonly called an insulating layer or
oxide layer. This process is called oxidation as shown in Figure (1.26).
Step-3: After oxidation again, the wafer is coated with a uniform film of a photosensitive
emulsion or etching solution. This process is called photolithography. A layout of the desired
ice pattern to opens the windows is made. This negative or stencil of the required dimensions
is placed as a mask over the photoresist. By exposure of the emulsion to ultraviolet light
through the mask, the photoresist becomes polymerized under the transparent regions of the
stencil. The mask is now removed and the wafer is developed by using a chemical called
trichloroethylene. This chemical dissolves the unexposed portions of the photoresist film and
leaves the surface pattern.
The wafer is now immersed in an etching solution by hydrofluoric acid. This acid removes
the oxide from the areas through which the impurities are to be diffused.
The next step is to introduce impurities such boron in the wafer by diffusion process to create
P-layer. In this process, the wafer is placed in a high temperature furnace (of about 100C)
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and P-type impurities are diffused into N-type layer as shown in Figure (1.27). The P-type
base of the transistor is now diffused in to the N-layer, which acts as a collector.
Step-4: After that the oxidation, the photoresist and masking process is repeated. This creates
windows in the silicon dioxide layer as shown in Figure (1.28). The next is to introduce
impurities such as phosphorus by similar diffusion process i.e., N-type emitter is now
diffused into the base of P-type layer as shown in Figure (1.28).
Step-5: After that the oxidation and open windows for base, emitter and collector contact.
Metallization is necessary, for making interconnections and providing bonding pads around
circumference of the chip for connection of wires. The metallization is done by vacuum
evaporation of aluminum and then selectivity etching away the aluminum over the entire
surface.
1.9 INTEGRATED DIODE
Figure (1.30) shows the cross section area of the integrated diode. Integrated diode is
constructed by bipolar transistor fabrication process. N-type epitaxial layer is grown on the P-
type substrate. A thin layer of silicon dioxide SiO
2
is grown over the N-type layer i.e. a N-
type which is greater in size is diffused into the P-type substrates which acts as a cathode and
a their oxide layer is grown. P-type impurities which are small in size are diffused into N-
type layer. Again the entire wafer is now covered with silicon dioxide. Using masking and
etching techniques, the, contact surfaces for the device terminals are defined. The entire
wafer is now covered by aluminum layer and final mask defines the desired interconnection
pattern. The excess aluminum is removed by etching technique. This completes the
fabrication process of diode.

Figure1.30.
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1.10TRANSISTOR CONNECTED AS DIODE
There are number of ways in which a transistor can be connected as a diode as shown in
Figure (1.31). They are obtained from a transistor structure by using; the emitter-base diode,
with the collector shorted to the base the emitter-base diode with the collector open; the
collector-base diode with the emitter open as shown in Figure (g) respectively.

Figure1.31.
1.11 INTEGRATED CAPACITORS
The capacitors in monolithic integrated circuits are fabricated in two basic methods one is the
depletion-region (or junction0 by utilizing capacitance of a reverse biased PN junction, the
MOS transistor or their film deposition.

Figure1.32.
As in the case of diodes and resistors, it is desirable to make junction capacitors during one
of the transistor diffusion steps. The base-collector junction of a transistor, without emitter
diffusion can be used as a capacitor. The emitter-base junction can also be used, or on N+
region can be diffused into one of the P isolation region during an emitter diffusion. Figure
(1.32) shows the structure of a junction capacitor utilizing the base-collector junction of a
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transistor Figure (1.33) shows a MOS non-polarized parallel plate (b) capacitor. This
capacitor utilizes silicon dioxide layer as a dielectric. A Thin film of aluminum acts as a top
plate. The bottom plate consists of heavily doped N+ region, which is formed during either
the emitter diffusion in bipolar, process or the implantation of the drain and source regions in
MOS process.

Figure1.33.
The junction capacitor type has a drawback that the value of capacitance varies with the
voltage. The capacitance of MOS or junction capacitor is up to about 100 pF. The use of
tantalum films can increase its capacitance.
1.12 INTEGRATED RESISTOR
The resistors in monolithic ICs are usually obtained by utilizing the bulk resistivity of one of
transistor region. Most of to the resistor are made during the diffusion of base as shown in
Figure (1.34) because base is high resistivity. The resistor can also be made using resistivity
of any diffusion areas. Most resistor uses P-type base diffusion region. However emitters
diffusion can also be used. Since resistivity of emitter region is very low and hence to make
low resistance values emitter region are used.

Figure1.34.
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In order to make integrated resistor first of all N-type epitaxial layer is grown on the P-type
substrate and then a P-type impurities which in to N-type layer. Figure (1.34) Shows the
structure of diffused resistor. The resistance of P-region depends upon its length, width, depth
of diffusion and resistivity of the diffused material. The resistance of diffused layer is given
by
R = (L/A) = (L/W.t)
Where
= Average resistivity of diffused layer
L = Length of diffused layer
W = Width of diffused layer
t = Thickness of diffused layer and
A = Cross-sectional area of diffused layer
The range values obtainable with diffused resistors are limited by the size of the area
required by the resistor. Practical range of resistance is 20 to 30 k for an emitter diffused
resistor.
1.13 PACKAGING
The earliest integrated circuits were packaged in ceramic flat packs, which continued to be
used by the military for their reliability and small size for many years. Commercial circuit
packaging quickly moved to the dual in-line package (DIP),[Figure1.35] first in ceramic and
later in plastic.

Figure1.35.
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In the 1980s pin counts of VLSI circuits exceeded the practical limit for DIP packaging,
leading to pin grid array (PGA) [Figure1.36]

Figure1.36.
and leadless chip carrier (LCC) packages. [Figure1.37]

Figure1.37.
Surface mount packaging appeared in the early 1980s [fig 1.38]

Figure1.38.
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and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-
wing or J-lead, as exemplified by small-outline integrated circuit a carrier which occupies
an area about 3050% less than an equivalent DIP, with a typical thickness that is 70% less.
This package has "gull wing" leads protruding from the two long sides and a lead spacing of
0.050 inches.In the late 1990s, plastic quad flat pack (PQFP) [Figure1.39]

Figure1.39.

and thin small-outline package (TSOP) [Fig 1.40]

Figure1.40.

packages became the most common for high pin count devices, though PGA packages are
still often used for high-end microprocessors. Intel and AMD are currently transitioning from
PGA packages on high-end microprocessors to land grid array (LGA) packages. [Fig 1.41]
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Figure1.41.

Ball grid array (BGA) packages have existed since the 1970s. [Fig 1.42]

Figure1.42.
Flip-chip Ball Grid Array packages, [Figure 1.43] which allow for much higher pin count
than other package types, were developed in the 1990s. In an FCBGA package the die is
mounted upside-down (flipped) and connects to the package balls via a package substrate that
is similar to a printed-circuit board rather than by wires. FCBGA packages allow an array of
input-output signals (called Area-I/O) to be distributed over the entire die rather than being
confined to the die periphery. Traces out of the die, through the package, and into the printed
circuit board have very different electrical properties, compared to on-chip signals. They
require special design techniques and need much more electric power than signals confined to
the chip itself.
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Figure1.43.
When multiple dies are put in one package, it is called SiP, for System In Package. When
multiple dies are combined on a small substrate, often ceramic, it's called an MCM, or Multi-
Chip Module. The boundary between a big MCM and a small printed circuit board is
sometimes fuzzy.

1.14 DESIGN RULES ARISES DUE TO MANUFACTURING PROBLEMS
Photo resist shrinkage, tearing.
Variations in material deposition, temperature and oxide thickness.
Impurities.
Variations across a wafer.

These lead to various problems like:
1. Transistor problems:
Variations in threshold voltage: This may occur due to variations in oxide thickness,
ion-implantation and poly layer.
Changes in source/drain diffusion overlap.
Variations in substrate.
2. Wiring problems:
Diffusion: There is variation in doping which results in variations in resistance, capacitance.
Poly, metal: Variations in height, width resulting in variations in resistance, capacitance.
Shorts and opens.
3. Oxide problems:
Variations in height.
Lack of planarity.
4. Via problems:
Via may not be cut all the way through.
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Undersize via has too much resistance.
Via may be too large and create short.
To reduce these problems, the design rules specify to the designer certain geometric
constraints on the layout artwork so that the patterns on the processed wafers will preserve
the topology and geometry of the designs. This consists of minimum-width and minimum-
spacing constraints and requirements between objects on the same or different layers. Apart
from following a definite set of rules, design rules also come by experience.

1.15 DIODE & TRANSISTOR FABRICATION

Figure1.44.
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1.16 FET, CAPACITANCE & RESISTOR FABRICATION

Figure1.45.

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1.17 CMOS & MOSFET FABRICATION

Figure1.46.


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1.18 Monolithic IC:

Figure1.47.
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EXAMPLE PROBLEMS
Fabricate the following circuit in a substrate

Solution: