EUV mask technology and economics will impact patterning strategies for the 7nm node and beyond. Key challenges include developing a high power light source, improved resists, and defect-free masks. While EUV mask infrastructure is being established, the cost of EUV masks must be less than 3 times the cost of equivalent ArF masks for EUV lithography to be economically viable. Adopting EUV lithography could enable simpler designs through 2D routing and fewer mask layers, but these benefits depend on lowering EUV mask costs to drive earlier insertion.
EUV mask technology and economics will impact patterning strategies for the 7nm node and beyond. Key challenges include developing a high power light source, improved resists, and defect-free masks. While EUV mask infrastructure is being established, the cost of EUV masks must be less than 3 times the cost of equivalent ArF masks for EUV lithography to be economically viable. Adopting EUV lithography could enable simpler designs through 2D routing and fewer mask layers, but these benefits depend on lowering EUV mask costs to drive earlier insertion.
EUV mask technology and economics will impact patterning strategies for the 7nm node and beyond. Key challenges include developing a high power light source, improved resists, and defect-free masks. While EUV mask infrastructure is being established, the cost of EUV masks must be less than 3 times the cost of equivalent ArF masks for EUV lithography to be economically viable. Adopting EUV lithography could enable simpler designs through 2D routing and fewer mask layers, but these benefits depend on lowering EUV mask costs to drive earlier insertion.
EUV mask technology and economics will impact patterning strategies for the 7nm node and beyond. Key challenges include developing a high power light source, improved resists, and defect-free masks. While EUV mask infrastructure is being established, the cost of EUV masks must be less than 3 times the cost of equivalent ArF masks for EUV lithography to be economically viable. Adopting EUV lithography could enable simpler designs through 2D routing and fewer mask layers, but these benefits depend on lowering EUV mask costs to drive earlier insertion.
BRYAN KASPROWICZ PHOTRONICS, INC. MAIN INDUSTRY CHALLENGES Long term, reliable, high-power source • Demonstrating >100 WPH and >1500 WPD
Improved resists M. Van den Kerkhof., 2017 SPIE AL • Resolution and LWR to meet patterning requirements • Increased sensitivity can help enable throughput
Defect free blanks/masks
• Infrastructure and capability solutions for blank, pattern and mask image inspection Meyers, S., 2016 EUVL Workshop EUV MASK PROGRESS SNAPSHOT
Blank Defects • Blank inspection not gating factor – ABI is available • Defect compensation and phase defect repair Courtesy of Lasertec techniques
FEOL Module • Patterning capability is not limiting for N7
Mask Border Leakage
• Optimization of dark border process Courtesy of Mentor Graphics • Absorber and flare interactions EUV BLANK IS KEY TO SIMPLIFIED INTEGRATION
0 defects @ 23nm SEVD
Demonstrated in 1Q16 Blank defect trend at 23nm solidly in single-digit range, making 132 x 104mm mitigation effective for some levels
Still need engineering work to define blank fiducial strategy
compatible with low defects and placement accuracy Onuoe, EUVL Symposium 2016, Hoya EUV FRONT END MASK MAKING IS ACHIEVABLE Isolated Line Isolated Space Dense L/S Isolated Contact Design Actual Design Actual Design Actual Design Actual 50nm 55.2nm 40nm 31.8nm 40nm 35.6nm 50nm 32.1nm 60nm Abs 50nm CD
PCAR
Isolated Line Isolated Space Dense Line Isolated Dot
Design Actual Design Actual Design Actual Design Actual 30nm 41.6nm 50nm 43.6nm 50nm 40.2nm 60nm 66.1nm
NCAR IMPACT OF BLACK BORDER ON OOB AND REG
Simulation
Pre Post
Std BB Actual
Target spec <2%
LOOKING AT EUV INFRASTRUCTURE SEMATECH EMI launched AIMS program in 2012 • 1st tool under installation Courtesy of Zeiss
• Multiple companies participating
EIDEC ABI program launched in 2011
• In regular use, allows sampling at 20nm SEVD • Defect location accuracy approaching 10nm target
Actinic Pattern inspection
• APMI is missing in action (MIA) • Will it be too late if it ever arrives? Xiong, Y., BACUS Panel 2015 WHY EUV? COMPLEXITY OF PRODUCT DESIGN & TECH DEVELOPMENT Three primary challenges 1. Design • Learning double patterning (mask coloring) • MP impacts on parasitic extraction and variation • Implementation rules for place and route • DRC/MRC 2. Manufacturing • Fins with consistent height during etch • 2D/3D structures impact on metrology and inspection 3. Cost • Avg design cost for N28 planar ~ $40M (+ 60% for embedded s/w and masks) • Avg design cost for N14ff SOC ~ $100M (+ 60% for embedded s/w and masks) • High End SOC ~ $200M (+ ~$100M) • Low End SOC with IP reuse ~$60M (+ ~$40M)
Semi-Engineering, various EDA, 2015
DESIGN PERSPECTIVE N28 required ~100 Engineer Years to bring out design • Team of 50 engineers 2 years to complete design to tapeout • + ~9-12 months for proto, test and qual • Typical design is 11-Metal process with ~ 52 masks • @80% fab utilization mfg cost ~$3500 / 300mm wafer • @ ~1.3 layers / day, cycle time ~70 days (min 2.5 months from start to delivery)
N14 required ~200 Engineer Years to bring out design
• Team of 50 engineers 4 years to complete design to tapeout • + ~9-12 months for proto, test and qual • Typical design is 11-Metal process with 66 masks • @80% fab utilization mfg cost ~$4800 / 300mm wafer • @ 1.3 layers / day, cycle time is ~90 days (min 3 months from start to delivery)
N7 early projections ~300 Engineer Years
• Team of 50 engineers 6 years to complete design to tapeout • + ~9-12 months for proto, test and qual • Typical design is 11-Metal process with >80 masks (optical only) • NCAR processing on BEOL, low pattern density • LELELE or SAQP are options Gartner, April 2015 DESIGN COST FOR SOC $15M Mask set ~2.5% of cost!
Reduced # vias (better yield) Better freedom for Reduced MOL Less min. length (area) wires redundant via insertion complexity by 2D M1 Able to connect to neighbor wire
Esin Terzioglu, Qualcomm, 2014 EUVL
EUV POTENTIAL DESIGN BENEFITS IN N7 Reduced wafer/die cost due to reduced mask count and better shrink • Reducing MOL complexity by using 2D M1 routing – Is 2D back in vogue? • Replacing repetitive litho/dep/etch steps with ArF
Potential yield gains
• Reduced mask count • Reduced number of required vias, more redundancy
Potential area gains due to less restrictions in layout
• Aggressive pitch scaling to improve die cost by area scaling • Chance to put more functionality in the same area EUV ON THE CUSP? >20 NXE3400 systems forecasted for delivery in 2017/18, HVM 2019? • > 1M wafers exposed on NXE33xx systems
Technical and Economic Drivers for adoption
• EPE, ability to keep all cuts on one layer • Reconsider 2D layouts with SE • 3:1 ArF:EUV cost ratio is the industry target Mulkens, J., Proc. SPIE 9422, EUV Lithography2015 IMPORTANCE OF EUV MASK COST ON ADOPTION General industry consensus: • Cost of EUV mask <= Cost of 3x ArFi masks
Lercel, M. Proc. SPIE 9985, Photomask Technology 2016
150% • As volumes 100% increase, cost of blanks will take 50% over • Does not include process 0% yield or blank inspection 12 48 120 240 (ABI) Masks per year REMAINING KEY ISSUES LIST SUMMARY Continuous improvement on actinic inspection tools • ABI already bearing fruit; AIMS getting started
Pattern mask inspection is a game changer for EUV
• EBMI is showing progress though speed improvements are required • Innovate equipment and processes to allow for use with 193nm masks • APMI is late and will be expensive but worth the costs for pattern and post pellicle inspection – who will step up to support?
Yield and Utilization are primary factors in reducing product cost
• Need critical mass to foster quality learning cycles, maximize use • End user commitment to mask output is key for model SUMMARY Masks are key to the success of EUV - Significant improvements made • Mask manufacturing is maturing, approaching HVM readiness, BEOL focus • Blank defect reduction is required to help improve mitigation process • Infrastructure showing progress – ABI is good benchmark for success, AIMS in early stages in the field, APMI needed but lacks owner
EUV can be cost competitive to ArF with modest scanner throughput
• Cost model validates cost parity between one EUV mask and three high-end ArFi masks • Reverses scaling trends, improves chip density; should allow for more chips/field and reduce cost
Modest EUV volumes are required to manage EUV Mask cost
• Earlier adoption will help drive crossover from ArF multi-patterning • Blank cost is largest driver for HVM ACKNOWLEDGMENTS Henry Kamberian and the Photronics Nanofab team
