Modified LDICA Lab R20 Ready To Print

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K. S. R. M. COLLEGE OF ENGINEERING
(UGC-AUTONOMOUS)
Kadapa, Andhra Pradesh, India– 516 003
Approved by AICTE, New Delhi & Affiliated to JNTUA, Ananthapuramu.

An ISO 14001:2004 & 9001: 2015 Certified Institution
LINEAR & DIGITAL IC APPLICATIONS

(2004406)
LABORATORY MANUAL
UG R20 Regulations
DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

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LINEAR & DIGITAL IC APPLICATIONS

LABORATORY MANUAL
By
Miss Shaik Jabeen

Assistant Professor
Department of ECE
&
Sri S. Munwar Ali

Assistant Professor
Department of ECE

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Linear and Digital IC Applications Lab (2004406)
VISION and MISSION of the College
VISION
KSRMCE seeks to be recognized as one of the best engineering colleges in India in providing high
standards of academics with most productive, creative learning environment by including research,
innovation thoughts and producing graduates with human values and leadership qualities to serve
nation.
MISSION
M1: To provide high quality education in Engineering & Technology in order to bring out
knowledgeable engineers.
M2: To create a collaborative environment with stakeholders to take up need-based research and
industry specific programs.
M3: To organize co-curricular and extracurricular activities for character and personality development
to produce highly competent and motivated engineers and professionals to serve and lead the society.
VISION and MISSION of the Department
VISION
To emerge the Electronics and Communication Engineering Department as a value based globally
recognized center ensuring academic excellence, fostering research innovation and entrepreneurial
attitude.
MISSION
M1: To be a student centric institute imbibing experiential, innovative and lifelong learning skills,
addressing industrial and societal problems.
M2: To promote all-inclusive research and development.
M3: To inculcate entrepreneurial attitude and values amongst the learners.
M4: To strengthen National and International, Industrial and Institutional collaborations for symbiotic
relations.
Program Educational Objectives (PEOs)
PEO1: To provide students with a strong foundation in mathematics, science and engineering.
PEO2: To provide students with sufficient technical and programming skills to meet the industry
demands.
PEO3: To provide students with sufficient leadership, entrepreneurship qualities, professional and
ethical attitude for a successful professional career.

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PEO4: To generate graduates with a multidisciplinary approach and an ability to relate engineering
issues to broader social context.
Program Outcomes
PO1 - Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO2 - Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
PO3 - Design/Development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.
PO4 - Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5 - Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
PO6 - The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO7 - Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO8 - Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of engineering practice. An understanding of professional and ethical responsibility and norms
of electrical engineering practices.
PO9 - Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO10 - Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
PO11 - Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one's own work, as a member and leader in
a team, to manage projects and in multidisciplinary environments.
PO12 - Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

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Program Specific Outcomes (PSOs)
PSO 1: An ability to design and conduct experiments, as well as to analyze and interpret data.
PSO 2: An ability to design a system, component, or process to meet desired needs within realistic
constraints such as economic, environmental, social, political, ethical, health and safety,
manufacturability, and sustainability.
PSO 3: The broad education necessary to understand the impact of engineering solutions in a global,
economic, environmental and societal context.
PSO 4: An ability to use the techniques, skills, and modern engineering tools necessary for engineering
practice.
GENERAL INSTRUCTIONS
Rough record and Fair record are needed to record the experiments conducted in the laboratory. Rough
records are needed to be certified immediately on completion of the experiment. Fair records are due
at the beginning of the next lab period. Fair records must be submitted as neat, legible, and complete.
INSTRUCTIONS TO STUDENTS FOR WRITING THE FAIR RECORD
In the fair record, the index page should be filled properly by writing the corresponding experiment
number, experiment name, date on which it was done and the page number.
On the right side page of the record following has to be written:
1. Title: The title of the experiment should be written in the page in capital letters.
2. In the left top margin, experiment number and date should be written.
3. Aim: The purpose of the experiment should be written clearly.
4. Apparatus/Tools/Equipments/Components used: A list of the Apparatus/Tools/ Equipments
/Components used for doing the experiment should be entered.
5. Theory: Simple working of the circuit/experimental set up/algorithm should be written.
6. Procedure/Code: steps for doing the experiment and recording the readings should be briefly
described(flow chart/programs in the case of computer/processor related experiments)
7. Results: The results of the experiment must be summarized in writing and should be fulfilling the aim.
8. Inference: Inference from the results is to be mentioned.
On the Left side page of the record following has to be recorded:
1. Circuit/Program: Neatly drawn circuit diagrams/experimental set up.
2. Design: The design of the circuit/experimental set up for selecting the components should be clearly
shown if necessary.
3. Observations:
i) Data should be clearly recorded using Tabular Columns.
ii) Unit of the observed data should be clearly mentioned

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iii) Relevant calculations should be shown. If repetitive calculations are needed, only show a sample
calculation and summarize the others in a table.
4. Graphs: Graphs can used to present data in a form that show the results obtained, as one or more of the
parameters are varied. A graph has the advantage of presenting large amounts of data in a concise
visual form. Graph should be in a square format.
GENERAL RULES FOR PERSONAL SAFETY
1. Always wear tight shirt/lab coat, pants and shoes inside workshops.
2. REMOVE ALL METAL JEWELLERY since rings, wrist watches or bands, necklaces, etc. make
excellent electrodes in the event of accidental contact with electric power sources.
3. DO NOT MAKE CIRCUIT CHANGES without turning off the power.
4. Make sure that equipment working on electrical power is grounded properly.
5. Avoid standing on metal surfaces or wet concrete. Keep your shoes dry.
6. Never handle electrical equipment with wet skin.
7. Hot soldering irons should be rested in its holder. Never leave a hot iron unattended.
8. Avoid use of loose clothing and hair near machines and avoid running around inside lab.
TO PROTECT EQUIPMENT AND MINIMIZE MAINTENANCE:
DO:
1. SET MULTIRANGE METERS to highest range before connecting to an unknown source.

2. INFORM YOUR INSTRUCTOR about faulty equipment so that it can be sent for repair.
DO NOT:
1. Do not MOVE EQUIPMENT around the room except under the supervision of an instructor.
Equipment required for Laboratories:
1. Regulated Power supplies (RPS) - 0-30v.
2. Op-Amp Power Supplies
3. CROs - 0-20M Hz.
4. Function Generators - 0-1 M Hz.
5. Multimeters
6. Decade Resistance Boxes/Rheostats
7. Micro Ammeters (Analog or Digital) - 0-20 μA, 0-50 μA, 0-100 μA, 0-200 μA.
8. Electronic Components – ICs (IC 741, IC 555, IC 566, IC 723, IC 7805, IC 7905), Resistors,
Capacitors, BJTs, Diodes (Ge & Si type), Germanium and Silicon transistors (NPN & PNP).

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LABORATORY COURSE ASSESSMENT GUIDELINES
1. The number of experiments in each laboratory course shall be as per the curriculum in the scheme of
instructions provided by College Academic Council. Mostly the number of experiments is 10 in each
laboratory course under semester scheme.
2. The students will maintain a separate note book for observations in each laboratory course.
3. In each session the students will conduct the allotted experiment and enter the observations in the
observation book.
4. The students will then complete the calculations and obtain the results. The course coordinator will
certify the result in the same session.
5. The students will submit the record in the next laboratory class. The evaluation will be continuous
and not cycle-wise.
6. The internal marks of 40 are awarded in the following manner:

i) Evaluation as per the rubrics - Maximum Marks 30
ii) Regularity and Viva-Voce - Maximum Marks 10
The rubric parameters are as follows:
a) Write up format - Maximum Marks 10
b) Observations and Calculations - Maximum Marks 10
c) Results, Graphs and Discussion - Maximum Marks 10
While (a) and (c) are assessed at the time of record submission, (b) is assessed during the session based
on the observations and calculations. Viva Voce is conducted at the end of the semester for each
students and based on the performance Viva voce marks (Maximum 10) are allotted and based on the
attendance of the student regularity marks (Maximum 10) are allotted.
CO-PO Mapping
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3 PSO4
CO216.1 3 3 1 3 1 3 1 3 2 2
CO216.2 3 3 1 3 1 3 1 3 2 2
CO216.3
3 3 1 3 1 3 1 3 2 2
CO216.4
3 3 1 3 1 3 1 3 2 2
CO216.5 2 2 1 2 1 2 1 2 1 1

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Hardware Lab Rubrics
Excellent Good Satisfactory Poor

Criteria
(10 Marks) (7.5 Marks) (5 Marks) (2.5 Marks)
Aim, Apparatus, material The report follows the

requirement, theoretical basis, specified format but a
The write up follows the
procedure of experiment, few of the formats are The write up does not follow
specified format but a
Write up format sketch of the experimental
couple of the specified
missing and the the specified format and the
setup etc. is demarcated and experimental sketch is presentation is shabby.
parameters are missing.
presented in clearly labeled and not included in the
neatly organized sections. report
The experimental
The experimental
observations and
The experimental observations observations and The experimental
calculations are
and calculations are recorded in calculations are recorded observations and results are
recorded neatly but
Observations neatly prepared table with in neatly prepared table recorded carelessly. Correct
correct units and
correct units and significant with correct units and units significant figures are
and Calculations figures. One sample calculation significant figures but
significant figures are
not followed and sample
not used. Sample
is shown. sample calculation is not calculations not shown
calculation is also not
shown
shown
Results obtained are

Results obtained are correct within
Results obtained are correct Results obtained are not
correct within reasonable reasonable limits.
within reasonable limits. correct within reasonable
limits. Graphs are drawn Graphs are not drawn
Graphs are drawn neatly with limits. Graphs are not drawn
neatly with labeling of neatly and or labeling
labeling of the axes. Relevant neatly and or labeling is not
the axes. Relevant is not proper. No
Results, Graphs and calculations are performed proper. No calculations are
calculations from the calculations are done
Discussion from the graphs. done from the graphs.
graphs are complete. from the graphs.
All relevant points of the result All relevant points of the
All relevant points of the All relevant points of
are discussed and justified in result are discussed and not
result are discussed and the result are discussed
light of theoretical justified in light of theoretical
not justified in light of and not justified in
expectations. expectations.
theoretical expectations. light of theoretical
expectations.

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Software Lab Rubrics
Excellent Good Satisfactory Poor

Criteria
(10 Marks) (7.5 Marks) (5 Marks) (2.5 Marks)
Student is able to
Student is able to understand Student is able to Student is unable to
understand the
the question and able to understand the question understand the question and
Logical skills question and unable to
develop multiple logics to and able to develop logic unable to develop logic to
develop logic to write
write program to write program write program
program
Student followed the Student has the

instructions difficulty with some of
With no assistance, student Student followed the instructions in the Student has the difficulty in
instructions in the procedure and needed reading the procedure and
performed additional
Ability to follow procedure with little or clarification from the following the directions.
experiments or tests beyond instructor.
procedure and/or no assistance. If procedure was provided,
those required in instructions. If procedure was If procedure was
design a procedure student was not capable to
If procedure to accomplish an provided, the student was provided, the student
for experiment implement it and satisfy
objective in not provided, the needed some direction given lab objective.
able to implement and
student developed a systematic satisfy the lab objectives. to perform and to
set of tests to accomplish satisfy the lab
objective objective.
Student able to use

Ability to use Student able to use
Student able to use software software well and Student unable to use
software software well and able to
well and able to troubleshoot unable to troubleshoot software well and unable to
and to troubleshoot troubleshoot minor errors
Major errors in errors in troubleshoot Major errors in
logic/code/circuit in logic/code/circuit
logic/code/circuit diagram logic/code/circuit logic/code/circuit diagram
diagram diagram
diagram

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Course LINEAR AND DIGITAL IC APPLICATIONS

B. Tech. ECE IV Sem
Title LAB
Course
Category Hours/Week Credits Maximum Marks
Code
Continuous Internal End
L T P C Total
2004406 PC Assessment Exams
-- -- 3 1.5 40 60 100
End Exam Duration: 3Hrs
Course Objectives:
 To verify various op-amp applications.
 To verify the applications of different ICs.
 To write Verilog HDL programs for different logic circuits.
Course Outcomes: On successful completion of this course, the students will be able to
CO 1 Demonstrate the circuits with analog IC’s (741, 555, 78XX/79XX, 723).
CO 2 Apply IC’s (741, 555, 78XX/79XX, 723) in electronic applications.
CO 3 Design a digital system with Verilog to meet required specifications.
CO 4 Test the functionality of system design with Verilog Test Benches.
CO 5 Test the results of designed digital system using FPGA.
Part A: Analog IC Application Lab:

1. Design and verify the OP AMP – Adder, Subtractor, and Comparator Circuits.
2. Design and verify active filters LPF, HPF (first order).
3. Design and verify Function Generator using OP AMPs.
4. Design and verify IC 555 Timer – Monostable and Astable Operation Circuit.
5. Design and verify IC 566 – VCO Applications.
6. To verify the characteristics of Voltage Regulator using IC 723.
7. Design and verify 4 bit DAC using OP AMP.
8. To verify the characteristics of Precision Diodes.
Part B: Digital IC Applications:

(Simulate the internal structure of the following Digital IC’s using Verilog HDL)
1. Logic Gates- 74XX.
2. Half Adder, Half Subtractor, Full Adder, Full Subtractor & Ripple Carry Adder.
3. 3-8 Decoder -74138 & 8-3 Encoder- 74X148.
4. 8 x 1 Multiplexer -74X151 and 2x4 Demultiplexer-74X155.
5. 4 bit Comparator-74X85.
6. D Flip-Flop 74X74.
7. JK Flip-Flop 74X109.
8. Decade counter-74X90.
Software Required -- Xilinx Vivado
Hardware Required -- FPGA Trainer Kits

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CONTENTS
Part A: Linear IC Applications Lab
S. No. Experiment Name Page No.
INTRODUCTION - STUDY OF IC741, IC555, IC565 & 1

IC 566
1 OP-AMP APPLICATIONS – ADDER, SUBTRACTOR, 4
COMPARATOR
2 ACTIVE FILTER APPLICATIONS 8
a) LPF (INTEGRATOR) USING IC741 OP-AMP
b) HPF (DIFFERENTIATOR) USING IC741 OP-AMP
3 FUNCTION GENERATOR USING IC741 16
4 IC555 TIMER – MONOSTABLE AND ASTABLE 18

MULTIVIBRATORS
5 IC 566 – VCO Application 23
6 VOLTAGE REGULATOR USING IC 723 25
7 4-BIT DAC USING IC 741 OP-AMP 28
8 PRECISION RECTIFIERS USING OP-AMP IC 741 30
Experiments beyond the syllabus

9 THREE TERMINAL VOLTAGE REGULATORS – 7805, 33
7809
10 SCHMITT TRIGGER USING OP-AMP IC 741 36

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CONTENTS
Part B: Digital IC Applications Lab

(Simulate the internal structure of the following Digital IC’s using Verilog/VHDL)
S. No. Experiment Name Page No.
INTRODUCTION 1
1 LOGIC GATES- 74XX. 27
2 HALF ADDER, HALF SUBTRACTOR, FULL ADDER, FULL 34

SUBTRACTOR & RIPPLE CARRY ADDER.
3 3-8 DECODER -74138 & 8-3 ENCODER- 74X148. 40
4 8 X 1 MULTIPLEXER -74X151 AND 2X4 DEMULTIPLEXER- 45

74X155.
5 4 BIT COMPARATOR-74X85. 50
6 D FLIP-FLOP 74X74. 53
7 JK FLIP-FLOP 74X109. 56
8 4. DECADE COUNTER-74X90. 58
Experiments beyond the syllabus

9 4-BIT BINARY COUNTER - 7493 60
10 SHIFT REGISTER 7495 62

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Part A
Linear IC Applications Lab

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INTRODUCTION
Pin configuration, Parameters and Specifications of
IC 741, IC 555, IC 565 and IC 566
IC A 741 OP-AMP
1. Supply voltage:
A 741A, A 741, A 741E -------------------------------------------------- 22V
A 741C ------------------- 18 V
2. Internal power dissipation
DIP package ---------------------- 310 MW
3. Differential input voltage ---------------- 30 V
4. Operating temperature range
Military (A 741A, A 741) ------------------------------------------- 550 to +1250 C
Commercial (A 741E, A 741C) --------------------------------------- 00 C to +700 C
5. Input offset voltage ------------ 1.0 mV
6. Input Bias current ---------------------------------------- 80 nA
7. PSSR -------------- --------------------------- 30 V/V
8. Input resistance ------------- ---------------------------- 2M
9. CMMR -------------- ----------------------------90
10. Output resistance 75
11. Bandwidth ----------- -------------------------------1.0 MHz
12. Slew rate ------------ ------------------------------0.5 V/ sec
APPLICATIONS:
Non-inverting amplifier Inverting amplifier Integrator, Differentiator
Low Pass, High Pass, Band pass and Band Reject Filters

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NE / SE 555 / SE 555C
1. Supply voltage ------------ 4.5 V to 18 V

2. Supply current ----------- 3 mA.
3. Output voltage (low)-------------- 0.1 V
4. Output voltage (high)--------12.5 V (15 V Vcc) & 3.3 V (5V Vcc)
5. Maximum operating frequency ------------500 KHz
6. Timing from  sec to hours
APPLICATIONS:
1. Astable Multivibrator, Schmitt trigger, Free running ramp Generator, etc.,

2. Monostable Multivibrator, Frequency divider, Pulse structure
Phase Locked Loop NE / SE 565
1. Maximum supply voltage 26 V

2. Input Voltage 3 V(P-P)
3. Power dissipation 300Mw
4. Operating temperature NE 565- 00 C to 700C (SE 565-55 to +1250 C
5. Supply voltage 12 V
6. Supply current 8 mA
7. Output current- (sink) 1 mA
(Source) 10 mA
APPLICATIONS:
1. Modems
2. FSK Demodulation
3. FM Demodulation
4. Frequency Synthesizers etc.

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Voltage Controlled Oscillator IC 566
The NE/SE566 Function Generator is a voltage-controlled oscillator of exceptional linearity with

buffered square wave and triangle wave outputs. The frequency of oscillation is determined by an
external resistor and capacitor and the voltage applied to the control terminal. The oscillator can be
programmed over a ten-to-one frequency range by proper selection of an external resistance and
modulated over a ten-to-one range by the control voltage, with exceptional linearity
Specifications:
1. Operating supply voltage 12V to 24V
2. Operating supply current 12.5 mA
3. Input voltage 3Vp-p
4. Operating temperature 0 to 70°C
5. Power dissipation 30mw
Applications of VCO: Frequency modulation, Voltage to frequency converter
REVIEW QUESTIONS:
1. What is the symbol of op-amp?

2. Draw the pin diagram of op-amp.
3. What is the supply voltage range that an op-amp can with stand?
4. What is the input voltage range that an op-amp can with stand?
5. What are the available package types of IC741?
6. What is a virtual ground? What are the differences between the physical ground and thevirtual ground?
7. What is the current flowing through the input terminals of an Ideal op-amp?
8. Which loop voltage gain is larger, closed or open?
9. Mention a few applications of op-amp.
10. Mention some features of op-amp.
11. What is the main purpose of IC555 timer?
12. Draw the pin diagram of op-amp.
13. Draw the functional diagram of IC555 timer.
14. How many comparators are present in IC555 timer?
15. What are the trigger voltages of UC and LC?
16. What is the functionality of power amplifier in the output stage of IC555 timer?
17. Which is the Flip-Flop used in IC555 timer?
18. What is the use of RESET pin in IC555 timer?
19. What are the available package types of IC555 timer?
20. Mention a few applications of IC555 timer.
21. What is IC565?
22. What is IC566?

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EXPERIMENT NO: 1
OP-AMP APPLICATIONS – ADDER, SUBTRACTOR, COMPARATOR
AIM: To study the working of op- amp as adder, subtractor and comparator using IC 741.
EQUIPMENTS/COMPONENTS:
S.No. Name of the Quantity

component/equipment
1. Op amp 741 IC 1
2. Resistance R =1KΩ 3
3. Resistance R=10KΩ 3
4. Dual Regulated Power supply 1
5. Bread Board 1
6. Multimeter 1
7. Function Generator 1
8. Oscilloscope 1
9. Connecting wires and probes As required
THEORY:
ADDER: Let V1 and V2 are two inputs applied to the inverting terminal of op-amp through R1, and
R2 resistors as shown in fig.1. A feedback resistor Rf is connected between o/p and inverting i/p. Then
the o/p will be the summation of i/p voltages.
Vo = - (Rf/R1) (V1+V2) where Ri = R1 = R2
SUBTRACTOR: Let V1 and V2 are two inputs applied to the inverting and non inverting terminals of
the two op -amps through R1 and R2 resistors as shown in the subtractor circuit diagram. Feedback
resistor is connected between o/p and inverting i/p. Then the o/p will be the difference of two i/p
voltages.
Vo = - (Rf/R1) (V1 –V2) where Ri = R1 = R2
Here Rf = R1 = R2.
COMPARATOR: Comparator is a non-linear application of an op-amp in open loop configuration. A

Comparator circuit compares the input signal voltage with a reference voltage at the terminals of an
open loop op amp. An inverting comparator circuit shown in fig 3 with input voltage applied to
terminal and Vref to input terminal.
PROCEDURE:
ADDER
1. Connect the circuit as shown in figure.
2. Apply +V =+15V and –V = – 15V to Pin 7 and 4 of IC741
3. Apply the input voltages V1 and V2.
4. Measure the output voltage using Multi meter.
5. Verify with theoretical value.
6. Repeat the above for different values of V1 and V2.

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SUBTRACTOR

2. Apply +V = +15V and –V = – 15V to Pin 7 and 4 of 741IC
3. Apply the input voltages V1 and V2.
4. Measure the o/p voltage using Multi meter.
5. Verify with theoretical value.
6. Repeat the above for different values of V1 and V2.
COMPARATOR
1. Connect the circuit as shown in the figure.

2. Apply the supply voltages of +12V to pin7 and -12V to pin4 of IC 741 respectively.
3. Set the reference voltage as 1V DC.
4. Apply a sine wave of 5V p-p with 1 KHz frequency from the function generator.
5. Check the output on CRO. Calculate the amplitude of output wave as shown in fig.
6. Plot the waveforms on graph sheets.
CIRCUIT DIAGRAM:
ADDER
SUBTRACTOR

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COMPARATOR
OBSERVATIONS:
Adder
V1 in volts V0 (Theoretical) = −(𝑽𝟏 + 𝑽𝟐 ) V0 (Practical)

V2 in volts
Subtractor
V1 in volts V0 (Theoretical) = −(𝑽𝟏 − 𝑽𝟐 ) V0 (Practical)

V2 in volts
Comparator
Vin = _______
Vref = 0.5 V
VO =
Vref = -0.5V
VO =
Time period of output waveform = _________________

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MODEL GRAPH:
RESULT:
REVIEW QUESTIONS:
1. Draw the circuit diagram of 3 input adder.

2. What is the other name for adder?
3. Draw the circuit diagram of a Subtractor.
4. Which amplifier acts as a Subtractor?
5. How many basic input parameters are required for a comparator?
6. Draw the circuit diagram of a non-inverting comparator and inverting comparator.
7. What is the output of a non-inverting comparator and inverting comparator if the input is sinusoidal?
8. What are the differences between the Inverting and Non–Inverting comparator?
9. What is the name of the comparator if the reference voltage is 0V?
10. Draw the circuit diagram and the output waveform of a Zero Crossing Detector if the input is
sinusoidal?
11. What is the name of a regenerative comparator?
12. Draw an op- amp circuit whose output Vo is V1+ V2 – V3 –V4.

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EXPERIMENT NO: 2
ACTIVE FILTER APPLICATIONS
2a) LPF (INTEGRATOR) USING IC741 OP-AMP
AIM: To design and setup an integrator circuit using OP AMP 741C and plot its pulse response.
Sl. No Name and Specification Quantity required

1 Dual power supply +/- 15V 1
2 Function generator (0-1MHz) 1
3 Oscilloscope 1
4 Bread board 1
5 IC 741C 1
6 Resistor 47 KΩ (1), 100 KΩ (1)
7 Capacitor 0.1 µF (1), 0.01 µF (1), 0.001 µF (1)
8 Probes and connecting wires As required.
THEORY:
A simple low pass RC circuit can also work as an integrator when time constant is very large.
The components R and C cannot be made very large because of practical limitations.
The gain Av is infinite for an ideal op-amp. So that effective capacitance existing at the input terminals
will be very high. So the effective time constant of integrator becomes very large which results perfect
integration.
Nodal equation at ‘a’ is

Vi dV0
Cf 0
Ri dt
1
Ri C f 
V0  Vi dt
1
Thus the output voltage is times the integral of input and R1Cf is time constant of the integration
Ri C f
– domain.
1
V0 (s)  Vi (s)
Ri C f .S

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1
Hence the gain A 
wRi C f
At ω=0, |A| =
Hence at lower frequencies the gain will be very high & the op-amp will saturate.
In order to overcome op-amp saturation at lower frequencies we use practical Integrator circuit using
nodal equations.
Vi V0 dV0
 Cf 0
Ri R f dt
Vi ( s) V0 ( s)
  s.C f .V0 ( s)  0
Ri Rf
 R f / Ri
 V0 ( s )  Vi
(1  SR f C f
R f / Ri
Gain A  , thus when w=0 |A| = Rf /Ri
1  ( wC f R f ) 2
PROCEDURE:
1. Check the components.

2. Setup the circuit on the breadboard and check the connections.
3. Switch on the power supply.
4. Give Vi= 10Vpp, 1KHz square wave.
5. Keep the oscilloscope in AC coupling mode.
6. Observe input and output on two channels of the oscilloscope simultaneously.
7. Draw the input and output waveforms for different time constants on the graph.
8. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding output
voltage of the filter and tabulate the results.
9. Calculate the gain of the filter from the experimental results.
10. Plot the frequency response curve of the low pass filter with the experimental results obtained.
CIRCUIT DIAGRAM:

10
Design:
Given f =1 KHz So T = 1/f = 1ms
T = 2πRfC
Let C = 0.01µF
Then Ri = 47KΩ
Take Rf = 100KΩ
TABULAR COLUMN
Vin = 10 V
Gain in dB
S. No. Frequency (Hz) V0 (Volts)
20 log (Vo / Vin )
1 10
2 100
3 500
4 800
5 1k
6 3k
7 5k
8 10k
9 15k
10 30k
11 50k
12 70k
13 100k
14 300k
15 500k
MODEL GRAPH:

11
FREQUENCY RESPONSE:
RESULT:
REVIEW QUESTIONS:
1. What is an Integrator?
2. Draw the circuit of the Integrator using op-amp IC741.
3. Write down the expression for Vo of an Integrator.
4. Draw the frequency response of the Integrator and explain.
5. Draw the output waveform of the Integrator when the input is a Square wave.
6. What is the purpose behind the connection of Rf in the feedback path of Integrator?
7. What are the applications of Integrator?
8. Why Rcomp is used in both Integrator and Differentiator circuits?
9. What is a Differentiator?
10. Draw the circuit of the Differentiator using op-amp IC741.
11. Write down the expression for Vo of a Differentiator.
12. Draw the output waveform of the Differentiator when the input is a Sine wave.
13. Why R1 and Cf are connected in the circuit of the Differentiator?
14. What are the applications of Differentiator?

12
2b) HPF (DIFFERENTIATOR) USING IC741 OP-AMP

AIM: To design and setup a Differentiator circuit using OP AMP 741C and plot their pulse response.
Sl. No Name and Specification Quantity required
2 Function generator (0- 1MHz) 1
3 Oscilloscope 1
4 Bread board 1
5 IC 741C 1
6 Resistor 47 KΩ (1), 100 KΩ (1)
7 Capacitor 0.1 µF (1), 0.01 µF (1), 0.001 µF (1)
8 Probes and connecting wires As required.
THEORY:
One of the simplest op-amp circuits that contain capacitor is the differentiator circuit. As the name
suggests, the circuit performs mathematical operation of differentiation. In the ideal differentiator
circuit the nodal equation at node ‘N’ is
dVi V0i
C1  0
dt R f
dVi
 V0   R f C1
dt
Thus, the output voltage is constant, (-Rf C1) times the derivative of the input voltage Vi. The minus
sign indicates 1800 phase shift of the waveform V0 with right to input signal.
The phasor equivalent of above equation is
V0(s) = - Rf C1 S. Vi(S). Putting S = Jω

V
A  0   JùR f C1  ù f C1
Vi
ω
Above equation can be written as A = f/fa
Where fa = ½ RfC1At
At f = fa; |A| = 1
i.e., 0 dB and the gain increases at the rate of +20 db/decade; thus at high frequencies
differentiator may become unstable and break into oscillations. The input impedance decreases with
increase in frequency, thereby making the circuit sensitive to high frequency noise.

13
A practical differentiator of the type shown eliminates the above problems. The transfer function for
this circuit is
V0 ( s )  Z f  sR f C1
 
Vi ( s ) Zi (1  SR f C f )(1  SR1C1 )
for Rf Cf =R1C1 we get
V0 ( s)  sR f C1  sR f C1
 
Vi ( s) (1  SR1C1 ) 2 (1  Jf / f b ) 2
fb = 1 / 2R1C1
The values of fb should be selected such that fa < fb < fc, where fc is the unity gain bandwidth of the op-
amp in open loop configuration. For good differentiation one must ensure that the time period T of the
input signal is larger than or equal to RfC1,
i.e., T  RfC1
PROCEDURE:

2. Setup the circuit on the breadboard and check the connections.
4. Keep the oscilloscope in AC coupling mode.
5. Give Vi= 10Vp-p, 1KHz square wave.
6. Observe input and output on two channels of the oscilloscope simultaneously.
7. Draw the input and output waveforms for different time constants on the graph.
8. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding output
voltage of the filter and tabulate the results.
9. Calculate the gain of the filter from the experimental results.
10. Plot the frequency response curve of the high pass filter with the experimental results obtained.
CIRCUIT DIAGRAM:
C = 0.1 μF
= 0.01 μF
= 0.001 μF

14
Design:
Given f = 1 KHz So T = 1/f = 1ms
Design equation is T = 2πRfC
Let C = 0.1µF or 0.01µF or 0.001µF
Rf = 100KΩ ; Ri = 4 7 KΩ
TABULAR COLUMN
Vin = 10 V
Frequency V0 Gain in dB
S.No.
(Hz) (Volts) 20 log (Vo / Vin )
1 10
2 100
3 500
4 800
5 1k
6 3k
7 5k
8 10k
9 15k
10 30k
11 50k
12 70k
13 100k
14 300k
15 500k
MODEL GRAPH:

15
FREQUENCY RESPONSE:
RESULT:
QUESTIONS:
1. How filters are classified? Give one example for each classification.
2. What is an active filter and why it is called so?
3. How an active filter differs from a passive filter?
4. What are the advantages of active filters over passive filters?
5. Draw the frequency response of all filters (LPF, HPF, BPF, BRF and All-pass).
6. What is the formula for cut-off frequency?
7. What is a 3 dB frequency and why it is called so?
8. What are the other names for 3 dB frequency?

16
EXPERIMENT NO: 3
FUNCTION GENERATOR USING IC741
AIM: To set up and design function generator using Op-Amp IC 741.
EQUIPMENTS/COMPONENTS
Sl. No. Name specification Quantity

2 Resistors 10 KΩ, 20 KΩ 2+1
3 Capacitor 0.1 µF 1
4 IC 741 2
5 Oscilloscope 1
6 Bread board 1
7 Connecting wires and probes As required
THEORY:
This circuit uses two operational amplifiers. Op-amp A1 functions as a comparator and the op-amp A2
as an integrator. Comparator compares the voltage at point P continuously with respect to the voltage at
the inverting input; which as at ground potential. When the voltage at P goes slightly below zero, the
output of A1 will switch to negative saturation. Suppose the output of A1 is at positive saturation +V sat.
Since this voltage is the input of the integrator, the output of A2 will be a negative going ramp. Thus,
one end of the voltage divider R1-R2 is at +Vsat and the other at the negative going ramp. At time t = t 1,
when the negative going ramp attains value of –Vramp the effective voltage at point P becomes slightly
less than 0 V. This switches output of A1 from positive saturation to negative saturation level –Vsat.
During the time when the output of A1 is at –Vsat, the output of A2 increases in positive direction. At
the instant t = t 2, the voltage at point P becomes just above 0 V, thereby switching the output of A1
from –Vsat to +Vsat. The cycle repeats and generates a triangular waveform.
PROCEDURE:
2. Setup the function generator circuit on the breadboard and check the connections.
4. Observe the output waveforms at pin 6 of two ICs in different channels of the oscilloscope
simultaneously and note down their amplitudes and frequencies.
5. Draw the waveforms on the graph.
OBSERVATIONS:
Square waveform
Triangular waveform

17
CIRCUIT DIAGRAM:
MODEL WAVEFORMS
RESULT:
REVIEW QUESTIONS:
1. What is a Function Generator?

2. What are the different stages in a Function Generator and how they are connected?
3. Draw the output waveforms at different stages of Function Generator.
4. What is the relationship among the frequencies of output waveforms at different stages of Function
Generator?
5. Will there be any phase shift between the input and the output of any stage in the Function Generator
and what factor it depends on?
6. Why is Rcomp used in the circuit of Triangular wave generator?
7. Why is potentiometer used in the circuit of Wien Bridge Oscillator?

18
EXPERIMENT NO: 4
IC555 TIMER – MONOSTABLE AND ASTABLE MULTIVIBRATORS
4a) ASTABLE MULTIVIBRATOR USING IC 555
AIM: To design and setup astable multivibrator using IC 555.
Sl. No. Name and specification Quantity
1 Power Supply 10V 1
2 Resistors – 1KΩ, 47KΩ 4
3 Capacitor - 0.01µF, 0.1µF 2
4 IC 555 1
5 Oscilloscope 1
6 Bread board 1
THEORY:
The 555 timer is a highly stable device for generating accurate time delay .The internal structure of
555 is shown in which there are two comparators, a flip flop, an output stage, a voltage divider network
and a transistor. The comparator is a device whose output is high when the non-inverting input voltage
is greater than inverting input voltage and output is low when inverting input voltage is greater than
non-inverting input voltage. The voltage divider network consist of three 5KΩ resistors and provides a
trigger voltage level of 1/3VCC and threshold voltage level of 2/3VCC.The control voltage is used for
changing the threshold and trigger voltages externally.
555 as Astable multivibrator: Astable multivibrator means it has no stable states. It has two quasi
stable states (high and low).In the figure given, there are 2 external resistors R A and RB and a capacitor
C. When the power is given to the circuit the capacitor C will charge towards VCC through RA and RB
,when the capacitor voltage exceeds the level of 2/3VCC (threshold voltage) the output of the comparator
I goes high which resets the flip flop so the output Q of the flip-flop becomes low and becomes
high. Now the transistor which is connected to becomes ON. The capacitor C started to discharge
through RB and transistor exponentially.
When voltage across capacitor reaches just below of 1/3VCC (trigger voltage) the output of the
comparator II becomes high and sets the flip flop, turning OFF the transistor since it is connected to the
of the flip flop. The capacitor C will begin to charge towards V CC through RA and RB. When the
capacitor voltage exceeds the level of 2/3VCC, the output of the comparator I goes high which resets the
flip-flop so the output Q of the flip flop becomes low and becomes high. The cycle continues which
gives a square wave at the output (pin 3) and charging and discharging wave form across capacitor (pin
2&6).
555 as Symmetrical astable multivibrator: Symmetrical astable multivibrator means the
multivibrator has equal ON time & OFF time (duty cycle =50%).we can achieve this by making the
charging (towards 2/3 VCC) and discharging (towards 1/3VCC) process of capacitor through equal
resistance path. In the circuit diagram the diode (1N 4001) is connected across the resistor RB so the

19
charging of capacitor above threshold voltage (2/3VCC) takes place through the resistor RA and forward
biased diode. The discharging below trigger voltage (1/3VCC) is through the resistor RB. Since RA and
RB have same value, charging and discharging time of the capacitor will be same.
555 as Asymmetrical astable multivibrator: Asymmetrical astable multivibrator means the

multivibrator has unequal ON time & OFF time (duty cycle other than50%).In the circuit diagram the
charging of capacitor towards threshold voltage (2/3VCC) takes place through the resistor RA and RB,
discharging towards trigger voltage (1/3VCC) is through the resistor RB. Since charging and discharging
process of the capacitor takes place through different resistance path, the charging time and discharging
time of the capacitor will be different, which results in asymmetrical output wave.
PROCEDURE:
2. Setup the astable multivibrator circuit on the breadboard and check the connections.
4. Observe output and capacitor voltage on different channels of the oscilloscope simultaneously.
6. Measure the frequency of oscillation and duty cycle.
CIRCUIT DIAGRAM:
OBSERVATIONS:
T = 0.69 (RA + 2RB) C or f = 1.44 / {( RA+2RB) C}
Here T = t1 + t2
t1 = 0.69 (RA+RB)C (charging)
t2 = 0.69(RB)C (discharging)

20
GRAPH:
RESULT:
QUESTIONS:
What is the other name for Astable multivibrator (AMV)?

What is the formula for the time period of the waveform of AMV?
What is the formula for the % of Duty cycle?

21
4b) MONOSTABLE MULTIVIBRATOR USING IC 555
AIM: To design and construct a monostable multivibrator using 555 IC.
Objectives: Upon completion of this experiment the students are able to design and setup monostable
multivibrator using IC 555.
Sl. No. Name specification Quantity

1 Power Supply 10V 1
2 Resistors 1 KΩ 1
3 Capacitor 0.01µF ,0.1 µF 1 +1
4 IC 555 1
5 Oscilloscope 1
6 Function generator 0 – 1MHz 1
7 Bread board 1
THEORY
The monostable multivibrator has one stable state and one quasi stable state. Monostable multivibrator
produces an output pulse with defined time period for each external trigger pulse applied. It comes out
of the stable state only by use of an external signal called trigger.
When the output is low, that is, the circuit is in stable state. Upon application of trigger pulse to pin 2,
the output of the comparator II becomes high which sets the flip flop high. As the output is high, the
transistor becomes OFF since it is connected to the of the flip flop. Capacitor starts to charge
through R towards VCC, as soon as the capacitor voltage crosses 2/3 VCC (threshold voltage) the output
of the comparator I becomes high so the flip- flop will reset and out goes to low. At the same time
transistor turns ON and hence capacitor rapidly discharges through the transistor. The output of
this circuit remains low until a trigger pulse is again applied. The time during which the output
remains high is given by T = 1.1 RC.
PROCEDURE
2. Setup the monostable multivibrator circuit on the breadboard and check the connections.
4. Put the function generator output to square wave mode. Adjust the amplitude to 5V.
5. Observe trigger input, output and capacitor voltage on different channels of the oscilloscope
simultaneously.
7. Measure the time delay.

22
CIRCUIT DIAGRAM:
OBSERVATIONS:
Time period T = 1.1RC
MODEL GRAPH:
RESULT:
QUESTIONS:
1. What is the other name for monostable multivibrator (MSMV)?

2. When MSMV is in stable state, what is the output level?
3. Why trigger is required in the case of MSMV?
4. Which type of trigger pulse is required for MSMV?
5. What is the formula for the output pulse width of MSMV?
6. How long MSMV stays in unstable state?

23
EXPERIMENT NO: 5
VOLTAGE CONTROLLED OSCILLATOR (IC 566)
AIM: To construct and study the voltage controlled oscillator-using IC 566.
APPARATUS REQUIRED:
1. Function Generator.
2. C.R.O.
3. Bread Board
4. Connecting Patch chords.
COMPONENTS REQUIRED:
IC 566 - 1No
Resistors: 10kΩ - 1No
1.5kΩ - 1No
20kΩ - 1No
Capacitors: 1µf - 1No
0.1µf - 1No
0.01µf - 1No
THOERY:
This arrangement R1C1 combination determines the free running frequency and the control voltage V c
at terminal 5 is sent by the voltage divider formed with R2 and R3. The initial voltage Vc at terminal is
3/4 Vcc ≤ Vc ≤ Vcc Where +V is the total supply voltage.
PROCEDURE:
1. Connect the circuit as shown in fig.

2. Switch on the power supply of 12V DC & observe square wave output at pin no.3 & triangular wave
output at pin no.4.
3. Keep the product of R1 C1 as constant.
4. By varying the control voltage Vc, between ¾(Vcc) and Vcc observe the output frequency.
CIRCUIT DIAGRAM:

24
MODEL WAVEFORMS:
OBSERVATIONS:
Square wave Output signal
Amplitude = -------------
Time period = ---------------
Triangle wave Output signal
Amplitude = --------------
Time period = ------------------
RESULT:
REVIEW QUESTIONS:
1. Mention the applications of voltage-controlled oscillator.

2. How do you vary the VCO frequency?
3. Why it is called as Voltage controlled oscillator.
4. Draw the internal block diagram of IC 566 and explain.
5. Derive f0 of the voltage-controlled oscillator.
6. What is the voltage to frequency conversion factor Kv of IC 566?
7. Give the pin configuration of IC 566 and explain each pin.
8. List out the applications of VCO.

25
EXPERIMENT NO. 6
VOLTAGE REGULATOR USING IC723
AIM: To set up a low voltage regulator using IC723 and plot the regulation characteristics.
S. No. Name and specifications Quantity
1 Variable Power Supply (0- 30 V) 1
2 Resistors, rheostat 3
3 Capacitor 2
4 IC 723 1
5 Volt meter (0-30V) 1
Voltmeter (0-10V) 1
6 Ammeter (0-10 mA) 1
7 Bread board 1
8 Connecting Wires As required
THEORY:
Type 723 is the most versatile of the monolithic voltage regulators. It can be used to provide high and
low positive regulated voltages .Current can be boosted to provide 5A or more. It has short circuit
protection. The input voltage of IC723 vary from 9.5V to 40V and provide output voltage from 2V to
37V.
IC 723 regulator has two separate sections. One section provides a fixed voltage of 7.15v at the
terminal Vref, other section consists of an error amplifier. These two sections are not internally
connected. For constructing low voltage regulator using 723, Vref point is connected through a
resistance to the non-inverting terminal and the output is feedback to the inverting terminal of the error
amplifier. If the output voltage becomes low, the voltage at the inverting terminal of error amplifier also
goes down. Thus make the output of the error amplifier become more positive, there by driving
transistor more into conduction. This reduces the voltage across transistor and drives more current into
the load, causing voltage across the load to increase. Thus the initial decrease in the load voltage is
compensated. Similarly any increase in the load voltage gets regulated.
PROCEDURE:
1. Check all the components

2. Set up circuit on the breadboard and check the connections
3. Switch on the power supply
4. Vary the input dc voltage and measure the input and output voltages using voltmeter
5. Vary the load resistance potentiometer and measure output voltage and current
6. Plot line regulation and load regulation characteristics on the graph
7. Calculate percentage load regulation

26
CIRCUIT DIAGRAM:
Low voltage Regulator
IC 723 Pin details
OBSERVATIONS:
S.No Vi (volts) Vo (volts )

27
S.No RL (ohms) IL (mA) Vo (volts)
Percentage load regulation = {(VNL-VFL)/VNL} x 100 % = - - - - - - - - - - -
Graph:
Line regulation Load regulation
RESULT:
REVIEW QUESTIONS:
1. What is the function of a voltage regulator?

2. What is a voltage reference? Why is it needed?
3. Draw the functional block diagram of 723 regulators and explain.
4. Design a high voltage and low voltage regulator using IC 723.
5. Define line and load regulation of a regulator.
6. List the features of a voltage regulator IC 723.
7. List the different types of IC voltage regulators.
8. What are the applications of voltage regulator?

28
EXPERIMENT NO. 7
4-BIT DIGITAL TO ANALOG CONVERTER
AIM: To design a 4 bit R-2R ladder network DAC.
S.No. Name of the Quantity

component/equipment
1. Op amp 741 IC 1
2. Resistance R =10KΩ, 20 KΩ 4+5
3. Resistance RF=20KΩ 1
4. Dual Regulated Power supply 1
5. Bread Board 1
6. Multimeter 1
7. Connecting wires As required
CIRCUIT DIAGRAM:
THEORY:
The input is an n-bit binary word and is combined with a reference voltage V ref to give an analog
output signal. The output of DAC can be either voltage or current. For a voltage output DAC, the D/A
converter is mathematically described as
V0 = KVFS (d12 -1+d22 -2 + - - - - - - - -dN2 -n)
Where V0 = output voltage

VFS = full scale output voltage
K = Scaling factor usually adjusted to unity.
d1, d2, - - - - - - - -dn = n-bit binary fractional word with decimal point located at the left.
d1 = MSB with a weight of VFS/2
dn = MSB with a weight of VFS/2n

29
PROCEDURE:
Connect the circuit as shown in the circuit diagram and give digital input at the inputs
D1,D2,D3,D4 respectively and the analog output voltage is measured and tabulated. (D1=MSB)
𝐷 𝐷2 𝐷3 𝐷4
Output voltage Va = - VFS ( 21 + + + )
4 8 16
TABULAR COLUMN:
Digital Input
D1 D2 D3 D4 Analog Output theoretical Analog output practical Resolution
MODEL GRAPH:
RESULT:
QUESTIONS:
1. What is the drawback of weighted resistor DAC?

2. What is the drawback of R-2R ladder network DAC?
3. Define step size.
4. What is the resolution of this DAC?
5. What is the advantage of Inverted R-2R DAC?

30
EXPERIMENT NO: 8
PRECISION RECTIFIERS USING IC741 OP-AMP
AIM: To construct precision half wave rectifier and full wave rectifier using Op Amp.
APPARATUS REQUIRED:
1. IC µA 741 OP-Amp
2. Resistors
3. AFO
4. Diode IN 4001
5. Connecting wires
6. CRO
7. Bread board
THEORY:
The major limitation of ordinary diodes is that it cannot rectify voltage below 0.6v, the cut in
voltage of the diode. The precision rectifier, which is also known as a super diode, is a configuration
obtained with an operational amplifier in order to have a circuit behaving like an ideal diode and
rectifier. It can be useful for high-precision signal processing.
HALF WAVE RECTIFIER:
A half-wave rectifier is an electronic circuit. The rectifier circuit takes alternating current (AC)
from the wall outlet and converts it into a positive direct current (DC) output. The particular electronic
device that accomplishes this task is a semiconductor called a diode. The diode like all semiconductors
is a material which has a resistance in between that of a conductor or wire and an insulator like that of a
plastic.
FULL WAVE RECTIFIER:

A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating dc voltage using both
half cycles of the applied ac voltage. It uses two diodes of which one conducts during one half cycle
while the other conducts during the other half cycle of the applied ac voltage. During the positive half
cycle of the input voltage, diode D1 becomes forward biased and D2 becomes reverse biased. Hence
D1 conducts and D2 remains OFF. The load current flows through D1 and the voltage drop across R L
will be equal to the input voltage. During the negative half cycle of the input voltage, diode D1
becomes reverse biased and D2 becomes forward biased. Hence D1 remains OFF and D2 conducts.
The load current flows through D2 and the voltage drop across RL will be equal to the input voltage.
PROCEDURE:
Precision Half Wave Rectifier and Full wave rectifier

1. Connect the circuit as shown in the figures for half wave and full wave rectifier.
2. Set the input signal voltage using AFO.
3. Observe the output waveform in CRO and measure the output parameters.

31
CIRCUIT DIAGRAM:
1. Precision Half Wave Rectifier
Figure.1 Half wave Rectifier
2. Precision Full Wave Rectifier
Figure.2 Full wave Rectifier
TABULAR COLUMN:
INPUT OUTPUT FREQUENCY
Amplitude Time Amplitude Time

ON OFF

32
MODEL WAVEFORMS:
1. Precision Half Wave Rectifier
2. Precision Full Wave Rectifier
RESULT:
REVIEW QUESTIONS:
1. Draw the equivalent circuit of a full wave rectifier for input voltage less than zero volts(Vi<0)

33
EXPERIMENT NO. 9
THREE TERMINAL VOLTAGE REGULATORS – 7805, 7809
AIM: To construct a +5v, 1A Power supply using IC 7805
EQUIPMENTS /COMPONENTS:
Sl. No. Name and specifications Quantity

1 Multimeter 1
2 Capacitor 2
3 IC 7805, 7809 2
4 Bread board 1
5 Ammeter 1
6 Load resistor or Decade resistance box 1
7 Connecting Wires As required
THEORY:
The 78xx family is commonly used in electronic circuits where a regulated power supply is required
due to their ease of use and low cost. IC 7805 has a 5volt output.The78xx series are positive voltage
regulator, while 79xx devices are negative voltage regulators. IC 7805 has 3 terminals.7805 can deliver
up to 1.5A current. The device may get damaged if there is any deviation from the rated voltage, A
regulated power supply is very much essential for several electronics devices. The AC power gets
converted into constant DC by these circuits. The circuit is made up of linear voltage regulator 7805
along with capacitors and resistors with a full wave rectifier. A regulator is employed with capacitor
connected in parallel to the input terminal and the output terminal. The capacitor C2 is bypass capacitor
and is employed to bypass extremely tiny duration spikes to ground. C1 is the filter capacitor employed
in thecircuit to steady the slow alterations in the voltage.

34
PROCEDURE:
1. Check all the components

2. Set up circuit on the breadboard and check the connections
3. Switch on the AC supply
4. Measure input AC and output DC voltages using multimeter.
CIRCUIT DIAGRAM:
TABULAR COLUMN:
Fixed positive voltage regulator:
Load Resistance RL Load Current IL Load Voltage VL
Fixed negative voltage regulator:

35
Load Resistance Load Current IL Load Voltage VL

RL
MODEL GRAPHS:
Line Regulation for 78XX Load Regulation for 78XX
Line Regulation for 79XX Load Regulation for 79XX
RESULT:
REVIEW QUESTIONS
1. What are the draw backs of series voltage regulators?
2. Name any adjustable series voltage regulator IC.
3. What is the purpose of connecting CI and C0 in the circuit?
4. What are the output voltage options of 78XX/79XX series?
5. Define line regulation
6. Define load regulation
7. What is the current limit protection?
8. What are the ideal values of load and line regulations?

36
EXPERIMENT NO. 10
SCHMITT TRIGGER CIRCUIT USING IC 741
AIM: To study the Schmitt trigger characteristics by using IC 741 and compare theoretical & Practical
values of the Upper Threshold voltage, VUT and the Lower Threshold voltage, VLT.
EQUIPMENTS AND COMPONENTS:
EQUIPMENTS
1. DC power supply 1 No.
2. CRO 1 No.
3. Bread Board 1 No.
4. Function Generator 1 No.
COMPONENTS:
27 KΩ Resistor – 1 No
1 KΩ Resistor – 1No
IC 741- 1 No
THEORY:
If positive feedback is added to the comparator circuit, gain can be increased greatly. Regenerative
Comparator is also known as Schmitt Trigger .The input voltage is applied to the –ve input terminal
and feedback voltage to the +ve input terminal .The input voltage Vi triggers the output Vo every to me
it exceeds certain voltage levels. These voltage levels are called upper threshold (V UT) and Lower
threshold voltage (VLT).The hysteresis width is the difference between VUT and VLT.
PROCEDURE:

2. Apply +Vcc =+15V and –Vcc = – 15V to Pin 7 and 4 of 741 IC.
3. Connect the o/p of the oscillator to CRO and observe the waveform.
4. Calculate upper trigger potential and Lower trigger potential..
5. Verify with theoretical value VUT = +Vsat (R2/R1+R2) and VLT = –Vsat (R2/R1+R2).
CIRCUIT DIAGRAM

37
MODEL WAVEFORMS:
RESULT:
QUESTIONS:
1. Which is type of comparator called Schmitt trigger using IC741?

2. What is the output wave of Schmitt trigger if the input is sine wave?
3. What type of waveform is obtained when triangular or ramp waveforms are applied to Schmitt trigger
circuit?
4. Explain how a square wave is obtained at the output of timer when sine wave input is given?
5. What is the Threshold voltage?
6. How do you calculate the theoretical values of VUT and VLT in the case of IC741?
7. What is the Hysteresis width?
8. What is the minimum amplitude of the input sine wave in the case of Schmitt trigger using IC741?

Part B
Digital IC Application Lab
1
INTRODUCTION
VLSI: Very-large-scale integration (VLSI) is the process of creating an integrated circuit by combining
thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The microprocessor is a VLSI device. Before the
introduction of VLSI technology most ICs had a limited set of functions they could perform. An
electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC makers add
all of these into one chip. VLSI Design chiefly comprises of Front End Design and Back End design
these days. While front end design includes digital design using HDL, design verification through
simulation and other verification techniques, the design from gates and design for testability, backend
design comprises of CMOS library design and its characterization. It also covers the physical design
and fault simulation.
XILINX ISE Vivado: Xilinx ISE (Integrated Software Environment) Vivado is a software tool
produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize
("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction
to different stimuli, and configure the target device with the programmer. HDL: Hardware description
languages have been developed for modeling and simulating hardware functions. Only a part of the
language elements can be used for design implementation. Difference between standard programming
languages And hardware description languages: Standard programming languages: sequential HDLs:
describe parallel and concurrent behavior Two important HDLs: – 1) Verilog 2) VHDL
VHDL: VHDL is a hardware description language which uses the syntax of ADA. Like any hardware
description language, it is used for many purposes, for describing hardware as a modeling language, for
simulation of hardware, for early performance estimation of system architecture, for synthesis of
hardware, for fault simulation, test and verification of designs.
Microwind: Microwind is a tool for designing and simulating circuits at layout level. The tool features
full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross
section, 3D process viewer), and an analog simulator. The MICROWIND program allows the student
to design and simulate an integrated circuit. The package itself contains a library of common logic and
analog ICs to view and simulate. MICROWIND includes all the commands for a mask editor as well as
new original tools never gathered before in a single module. You can gain access to Circuit Simulation
by pressing one single key. The electric extraction of your circuit is automatically performed and the
analog simulator produces voltage and current curves immediately. A specific command displays the
characteristics of pMOS and nMOS, where the size of the device and the process parameters can be
very easily changed. Altering the MOS model parameters and, then, seeing the effects on the Vds and
Ids curves constitutes a good interactive tutorial on devices. The Process Simulator shows the layout in
a vertical perspective, as when fabrication has been completed.
The Logic Cell Compiler is a particularly sophisticated tool enabling the automatic design of a CMOS
circuit corresponding to your logic description in VERILOG. The DSCH software, which is a user-
friendly schematic editor and a logic simulator presented in a companion manual, is used to generate
this Verilog description.

2
Verilog Theory: Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware

description language is a language used to describe a digital system: for example, a network switches, a
microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL, one can
describe any (digital) hardware at any level. Verilog HDL is case sensitive
Design Styles: The traditional method of electronic design is bottom-up. Each design is performed at
the gate-level using the standard gates. With the increasing complexity of new designs this approach is
nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of
thousands of transistors. These traditional bottom-up designs have to give way to new structural,
hierarchical design methods. Without these new practices it would be impossible to handle the new
complexity.
Bottom-Up Design: The desired design-style of all designers is the top-down one. A real top-down
design allows early testing, easy change of different technologies, a structured system design and offers
many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most
designs are a mix of both methods, implementing some key elements of both design styles.
History of Verilog: When Cadence gave OVI the LRM, several companies began working on Verilog
simulators. In 1992, the first of these were announced, and by 1993 there were several Verilog
simulators available from companies other than Cadence. The most successful of these was VCS, the
Verilog Compiled Simulator, from Chronologic Simulation. This was a true compiler as opposed to an
interpreter, which is what Verilog-XL was. As a result, compile time was substantial, but simulation
execution speed was much faster.
Various stages of ASIC/ FPGA IC design flow.  Specification  High Level Design  Micro
Design/Low level design  RTL Coding  Simulation  Synthesis  Place  & Route Post Silicon
Validation
Simulation: It is the process of verifying the functional characteristics of models at any level of
abstraction. We use simulators to simulate the Hardware models, to test if the RTL code meets the
functional requirements of the specification. To achieve this we need to write a test bench, which
generates clk, reset and the required test vectors. A sample test bench for a counter is shown below.
Normally we spend 60-70% of time in design verification.
Synthesis: It is the process in which synthesis tools like design compiler take RTL in Verilog or
VHDL, target technology, and constrains as input and maps the RTL to target technology primitives.
Synthesis tool, after mapping the RTL to gates, also do the minimal amount of timing analysis to see if
the mapped design is meeting the timing requirements. (Important thing to note is, synthesis tools are
not aware of wire delays, they only know of gate delays). After the synthesis there are a couple of
things that are normally done before passing the netlist to backend (Place and Route).
Place and Route: The gate level netlist from the synthesis tool is taken and imported into place and
route tool in Verilog netlist format. All the gates and flip-flops are placed; clock tree synthesis and reset
is routed. After this each block is routed. The PAR tool output is a GDS file, used by foundry for
fabricating the ASIC. Backend team normally dumps out SPEF (standard parasitic exchange format)
/RSPF (reduced parasitic exchange format)/DSPF (detailed parasitic exchange format) from layout
tools like ASTRO to the frontend team, who then use the read_parasitic command in tools like Prime
3
Time to write out SDF (standard delay format) for gate level simulation purposes.
Module: In Verilog, we call our "black boxes" module. This is a reserved word within the program
used to refer to things with inputs, outputs, and internal logic workings. wire data type is used for
connecting two points. reg data type is used for storing values. Here we have only two types of ports,
input and output. In real life, we can have bidirectional ports as well. Verilog allows us to define bi-
directional ports as "inout."
Operators: Nearly all operators are exactly the same as their counterparts in the C programming
language.
Control Statements: If-else statements check a condition to decide whether or not to execute a portion
of code. If a condition is satisfied, the code is executed. Else, it runs this other portion of code. One
could use any operator in the condition checking, as in the case of C language. If needed we can have
nested if else statements; statements without else are also ok, but they have their own problem, when
modeling combinational logic, in case they result in a Latch (this is not always true). Case statements
are used where we have one variable which needs to be checked for multiple values. like an address
decoder, where the input is an address and it needs to be checked for all the values that it can take.
Instead of using multiple nested if-else statements, one for each value we're looking for, we use a single
case statement: this is similar to switch statements in languages like C++.
A while statement executes the code within it repeatedly if the condition it is assigned to check returns
true. While loops are not normally used for models in real life, but they are used in test benches. As
with other statement blocks, they are delimited by begin and end. For loops in Verilog are almost
exactly like for loops in C or C++. The only difference is that the ++ and -- operators are not supported
in Verilog. Repeat is similar to the for loop. Instead of explicitly specifying a variable and incrementing
it when we declare the for loop, we tell the program how many times to run through the code, and no
variables are incremented.
 While, if-else, case (switch) statements are the same as in C language.
 If-else and case statements require all the cases to be covered for combinational logic.
 For-loop is the same as in C, but no ++ and -- operators.
 Repeat is the same as the for-loop but without the incrementing variable.
 Combinational elements can be modeled using assign and always statements.
 Sequential elements can be modeled using only always statement.
 There is a third block, which is used in test benches only: it is called Initial statement.
 An initial block, as the name suggests, is executed only once when simulation starts. This is useful
in writing test benches. If we have multiple initial blocks, then all of them are executed at the beginning
of simulation.
always: As the name suggests, an always block executes always, unlike initial blocks which execute
only once (at the beginning of simulation). A second difference is that an always block should have a
sensitive list or a delay associated with it.
The sensitive list is the one which tells the always block when to execute the block of code. The @
symbol after reserved word ' always', indicates that the block will be triggered "at" the condition in
parenthesis after symbol @. One important note about always block: it cannot drive wire data type, but
can drive reg and integer data types.

4
An assign statement is used for modeling only combinational logic and it is executed continuously. So
the assign statement is called 'continuous assignment statement' as there is no sensitive list
The layout design rules are the link between the circuit designer and the technology constraints
which the former must fulfill so that the fabricated integrated circuits may achieve a sufficiently
high yield. ECAD tools always provide a Design Rule Checker (DRC) to inform the designer
whether they are being correctly considered or not. Aside those rules the circuit designer is usually
not concerned with technology related aspects, as in the ECAD environment these are encapsulated
in simple parameters like the sheet resistance of one layer, or capacitance per unit area between two
layers. This makes the actual thickness of the layers of little importance. For the active devices,
circuit simulator models as the SPICE Level 3 model are employed. They must be calibrated for a
given technology and afterwards need only relatively few layout-dependent parameters. For
integrated circuits with millions of transistors, similarly to what happens in its description, a
circuit-level simulation is not practical and ECAD tools provide logic-level and register level
simulators as well. A very important aspect in future integrated circuit design is testability. ECAD
frameworks include also tools to support the design for testability. In this lab we will Simulate the
internal structure of the different Digital ICs (like D Flip-Flop 7474, Decade counter-7490, shift
registers-7495 7 ,3-8 Decoder -74138 ,4 bit Comparator-7485 ,8 x 1 Multiplexer -74151 and 2x4
Demultiplexer-74155 RAM (16x4)-74189 (Read and Write operations) using VHDL / VERILOG
and verify the operations of the Digital IC’s (Hardware) in the Laboratory. The prototyping of the
designed systems will be done by using FPGA Hardware boards like Spartan3, Spartan6 and
Vertex5
Tasks and Functions: When repeating the same old things again and again, Verilog, like any
other programming language, provides means to address repeated used code, these are called
Tasks and Functions. Functions and tasks have the same syntax; one difference is that tasks can
have delays, whereas functions can not have any delay. This means that function can be used for
modeling combinational logic. A second difference is that functions can return a value, whereas
tasks cannot.
Module Instantiation: Modules are the building blocks of Verilog designs

 You create the design hierarchy by instantiating modules in other modules.
 You instance a module when you use that module in another, higher-level module
 Ports: Ports allow communication between a module and its environment.
 All but the top-level modules in a hierarchy have ports.
 Ports can be associated by order or by name.
 Registers: store the last value assigned to them until another assignment statement changes
their value. Registers represent data storage constructs.
 We can create regs arrays called memories.
 Register data types are used as variables in procedural blocks.
 Register data type is required if a signal is assigned a value within a procedural block
 Procedural blocks begin with keyword initial and always.

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Gate level primitives: Verilog has built in primitives like gates, transmission gates, and switches.
These are rarely used in design (RTL Coding), but are used in post synthesis step for modeling the
ASIC/FPGA cells; these cells are then used for gate level simulation, or what is called as SDF
simulation. Also the output netlist format from the synthesis tool, which is imported into the place
and route tool, is also in Verilog gate level primitives. Ex: and , or etc:
There are six different switch primitives (transistor models) used in Verilog, nmos, pmos and
cmos and the corresponding three resistive versions rnmos, rpmos and rcmos. The cmos types of
switches have two gates and so have two control signals.
Transmission gates tran and rtran are permanently on and do not have a control line. Tran can be
used to interface two wires with separate drives, and rtran can be used to weaken signals. Resistive
devices reduce the signal strength which appears on the output by one level. All the switches only
pass signals from source to drain; incorrect wiring of the devices will result in high impedance
outputs.
Delays: In real circuits, logic gates have delays associated with them. Verilog provides the
mechanism to associate delays with gates
Rise, Fall and Turn-off delays.
 Minimal, Typical, and Maximum delays.
 In Verilog delays can be introduced with #'num' as in the examples below, where # is a special
character to introduce delay, and 'num' is the number of ticks simulator should delay current
statement execution
The rise delay is associated with a gate output transition to 1 from another value (0, x, z).
The fall delay is associated with a gate output transition to 0 from another value (1, x, z).
The Turn-off delay is associated with a gate output transition to z from another value (0, 1, x).
The min value is the minimum delay value that the gate is expected to have.
The typ value is the typical delay value that the gate is expected to have.
The max value is the maximum delay value that the gate is expected to have.
User Defined Primitives (UDP): Verilog has built-in primitives like gates, transmission gates,
and switches. This is a rather small number of primitives; if we need more complex primitives,
then Verilog provides UDP, or simply User Defined Primitives. Using UDP we can model.
Combinational Logic and Sequential Logic. UDP begins with reserve word primitive and ends with
end primitive. Ports/terminals of primitive should follow. This is similar to what we do for module
definition. UDPs should be defined outside module and endmodule.
Abstraction Levels:
Behavioral Models: Higher level of modeling where behavior of logic is modeled.
RTL Models: Logic is modeled at register level
Structural Models: Logic is modeled at both register level and gate level.
Procedural Blocks: Verilog behavioral code is inside procedure blocks, but there is an exception:
some behavioral code also exist outside procedure blocks.
initial: initial blocks execute only once at time zero (start execution at time zero).
always: always blocks loop to execute over and over again; in other words, as the name suggests, it
executes always.

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Procedural Assignment Statements: Procedural assignment statements assign values to reg, integer,
real, or time variables and cannot assign values to nets (wire data types)
Procedural Group Statements: If a procedure block contains more than one statement, those
statements must be enclosed within
Sequential begin - end block

Parallel fork - join block
When using begin-end, we can give name to that group. This is called named blocks
begin - end
 Group several statements together.
 Cause the statements to be evaluated sequentially (one at a time)
 Any timing within the sequential groups is relative to the previous statement.
 Delays in the sequence accumulate (each delay is added to the previous delay)
 Block finishes after the last statement in the block
fork – join
 Group several statements together.
 Cause the statements to be evaluated in parallel (all at the same time).
 Timing within parallel group is absolute to the beginning of the group.
 Block finishes after the last statement completes (Statement with highest delay, it can be the
first statement in the block).
Blocking and Non blocking Assignment Statements:
Blocking assignments are executed in the order they are coded, hence they are sequential. Since
they block the execution of next statement, till the current statement is executed, they are called
blocking assignments. Assignment are made with "=" symbol. Example a = b;
Non blocking assignments are executed in parallel. Since the execution of next statement is not
blocked due to execution of current statement, they are called non blocking statement.
Assignments are made with "<=" symbol. Example a <= b;
assign and deassign: The assign and deassign procedural assignment statements allow
continuous assignments to be placed onto registers for controlled periods of time. The assign
procedural statement overrides procedural assignments to a register. The deassign procedural
statement ends a continuous assignment to a register.
force and release: Another form of procedural continuous assignment is provided by the force
and release procedural statements. These statements have a similar effect on the assign - deassign
pair, but a force can be applied to nets as well as to registers. One can use force and release while
doing gate level simulation to work around reset connectivity problems. Also can be used insert
single and double bit errors on data read from memory.

7
Casex and casez: Special versions of the case statement allow the x ad z logic values to be used
as "don't care".
Looping statements: Appear inside procedural blocks only; Verilog has four looping statements
like any other programming language. The forever loop executes continually, the loop never ends.
Normally we use forever statements in initial blocks.
The repeat loop executes < statement > a fixed < number > of times
The while loop executes as long as an < expression > evaluates as true. This is the same as in any
other programming language.
The for loop is the same as the for loop used in any other programming language.
Continuous assignment statements drive nets (wire data type). They represent structural
connections.
Conclusion: Thus we have studied the introduction of vlsi, softwares Xilinx and microwind; languages
like VHDL and Verilog.

8
Vivado Tutorial
Introduction
This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital
circuit using Verilog HDL. A typical design flow consists of creating model(s), creating user constraint
file(s), creating a Vivado project, importing the created models, assigning created constraint file(s),
optionally running behavioral simulation, synthesizing the design, implementing the design, generating
the bitstream, and finally verifying the functionality in the hardware by downloading the generated
bitstream file. You will go through the typical design flow targeting the Artix-100 based Nexys4 board.
The typical design flow is shown below. The circled number indicates the corresponding step in this
tutorial.
Figure 1. A typical design flow
Objectives
After completing this tutorial, you will be able to:
 Create a Vivado project sourcing HDL model(s) and targeting a specific FPGA device located on the
Nexys4 board
 Use the provided partially completed Xilinx Design Constraint (XDC) file to constrain some of the pin
locations
 Add additional constraints using the Tcl scripting feature of Vivado
 Simulate the design using the XSim simulator
 Synthesize and implement the design
 Generate the bitstream
 Configure the FPGA using the generated bitstream and verify the functionality
 Go through the design flow in batch mode using the Tcl script
Procedure
This tutorial is broken into steps that consist of general overview statements providing information on
the detailed instructions that follow. Follow these detailed instructions to progress through the tutorial.
Design Description
The design consists of some inputs directly connected to the corresponding output LEDs. Other inputs
are logically operated on before the results are output on the remaining LEDs as shown in Figure 1.

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Figure 2. Completed Design
General Flow for this tutorial

 Create a Vivado project and analyze source files
 Simulate the design using XSim simulator
 Synthesize the design
 Implement the design
 Perform the timing simulation
 Verify the functionality in hardware using the Nexys4 board
 Run the tools in batch mode using the provided Tcl script
Create a Vivado Project using IDE Step 1
1-1. Launch Vivado and create a project targeting the XC7A100TCSG324C-1 device and using the
Verilog HDL. Use the provided tutorial.v and tutorial.xdc files from the sources directory.
1-1-1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2013.3 > Vivado
2013.3
1-1-2. Click Create New Project to start the wizard. You will see Create A New Vivado Project dialog box.
Click Next.
1-1-3. Click the Browse button of the Project location field of the New Project form, browse to
c:\xup\digital, and click Select.
1-1-4. Enter tutorial in the Project name field. Make sure that the Create Project Subdirectory box is
checked. Click Next.
1-1-5. Select RTL Project option in the Project Type form, and click Next.
1-1-6. Select Verilog as the Target language and Simulator language in the Add Sources form.
1-1-7. Click on the Add Files… button, browse to the c:\xup\digital\sources\tutorial directory, select
tutorial.v, click Open, and then click Next.

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Figure 3. Project Name and Location entry
Figure 4. Part Selection
1-1-8. Click Next to get to the Add Constraints form.
1-1-9. Click Next if the entry is already auto-populated, otherwise click on the Add Files… button,
browse to the c:\xup\digital\sources\turorial directory and select tutorial.xdc, and click Open.
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This Xilinx Design Constraints file assigns the physical IO locations on FPGA to the switches and LEDs
located on the board. This information can be obtained either through a board’s schematic or board’s
user guide.
1-1-10. In the Default Part form, using the Parts option and various drop-down fields of the Filter
section, select the XC7A100TCSG324-1 part. Click Next.
1-1-11. Click Finish to create the Vivado project.
Use the Windows Explorer and look at the c:\xup\digital\tutorial directory. You will find that the
tutorial.data and tutorial.srcs directories and the tutorial.xpr (Vivado) project file have been created.
The tutorial.data directory is a place holder for the Vivado program database. Two more directories,
constrs_1 and sources_1, are created under the tutorial.srcs directory; deep down under them, the
copied tutorial.xdc (constraint) and tutorial.v (source) files respectively are placed.
Figure 5. Generated directory structure
1-2. Open the tutorial.v source and analyze the content.
1-2-1. In the Sources pane, double-click the tutorial.v entry to open the file in text mode.
Figure 6. Opening the source file
1-2-2. Notice in the Verilog code that the first line defines the timescale directive for the simulator. Lines 2-5
are comment lines describing the module name and the purpose of the module.
1-2-3. Line 7 defines the beginning (marked with keyword module) and Line 19 defines the end of the
module (marked with keyword endmodule).
1-2-4. Lines 8-9 define the input and output ports whereas lines 12-17 define the actual functionality.

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1-3. Open the tutorial.xdc source and analyze the content.
1-3-1. In the Sources pane, expand the Constraints folder and double-click the tutorial.xdc entry to open the
file in text mode.
Figure 7. Opening the constraint file
1-3-2. Lines 1-14 define the pin locations of the input switches [6:0] and lines 16-29 define the pin locations
of the output LEDs [6:0]. The swt[7] and led[7] are deliberately not defined so you can learn how to
enter them using other methods in Step 1-5
1-4. Perform RTL analysis on the source file.
1-4-1. Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator
pane and click on Schematic.
The model (design) will be elaborated and a logic view of the design is displayed.
Figure 8. A logic view of the design
Notice that some of the switch inputs go through gates before being output to LEDs and the rest go
straight through to LEDs as modeled in the file.
1-5. Add I/O constraints for the missing LED and switch pins.
1-5-1. Once RTL analysis is performed, another standard layout called the I/O Planning is available.
Click on the drop-down button and select the I/O Planning layout.
Figure 9. I/O Planning layout selection

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Notice that the Package view is displayed in the Auxiliary View area, Device Constraints tab is
selected, and I/O ports tab is displayed in the Console View area. Also notice that design ports (led and
swt) are listed in the I/O Ports tab with both having multiple I/O standards.
Move the mouse cursor over the Package view, highlighting different pins. Notice the pin site number is
shown at the bottom of the Vivado GUI, along with the pin type (User IO, GND, VCCO…) and the I/O
bank it belongs to.
Figure 10. I/O Planning layout view
1-5-2. Expand the led and swt ports by clicking on the + box and observe that led [6:0] and swt[6:0] use the
LVCMOS33 I/O standard whereas led[7] and swt[7] use defaults to LVCMOS18; hence you can see
multiple I/O standard in the collapsed view.
1-5-3. Click under the I/O Std column across the led[7] row and select LVCOMS33. This assigns the
LVCMOS33 standard to the site.
1-5-4. Similarly, click under the Site column across led[7] row to see a drop-down box appear. Type U in the
field to jump to Uxx pins, scroll-down until you see U6, select U6 and hit the Enter key to assign the
pin. Notice after selecting the pin U6, the Site column automatically places led[7] lower down in the
column since it alphabetically arranges the site/pin names.
Figure 11. I/O Ports tab

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Figure 12 Assigning I/O standard
1-5-5. You can also assign the pin constraints using tcl commands. Type in the following two commands in
the Tcl Console tab to assign the V5 pin location and the LVCSMOS33 I/O standard to swt[7] hitting the
Enter key after each command.
set_property package_pin V5 [get_ports {swt[7]}] set_property iostandard LVCMOS33 [get_ports [list

{swt[7]}]]
Observe the pin and I/O standard assignments in the I/O Ports tab.
You can also assign the pin by selecting its entry (swt[7]) in the I/O ports tab, and dragging it to the
Package view, and placing it at the V5 location. You can assign the LVCMOS33 standard by selecting
its entry (swt[7]), selecting Configure tab of the I/O Port Properties window, followed by clicking the
drop-down button of the I/O standard field, and selecting LVCMOS33.
1-5-6. Select File > Save Constraints and click OK to save the constraints in the tutorial.xdc file.
1-5-7. Click Update followed by OK to update the existing constraint file.
Note that the constraints are updated in the tutorial.xdc file under the tutorial project directory and not
under the sources directory.
Figure 13. Assigning I/O standard through the I/O Port Properties form

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Simulate the Design using the XSim Simulator Step 2
2-1. Add the tutorial_tb.v testbench file.
2-1-1. Click Add Sources under the Project Manager tasks of the Flow Navigator pane.
Figure 14. Add Sources
2-1-2. Select the Add or Create Simulation Sources option and click Next.
2-1-3. In the Add Sources Files form, click the Add Files… button.
2-1-4. Browse to the c:\xup\digital\sources folder and select tutorial_tb.v and click OK. 2-1-5. Click
Finish.
2-1-6. Select the Sources tab and expand the Simulation Sources group.
The tutorial_tb.v file is added under the Simulation Sources group, and tutorial.v is automatically
placed in its hierarchy as a tut1 instance.
2-1-7. Using the Windows Explorer, verify that the sim_1 directory is created at the same level as
constrs_1 and sources_1 directories under the tutorial.srcs directory, and that a copy of tutorial_tb.v is
placed under tutorial.srcs > sim_1 > imports > sources.
2-1-8. Double-click on the tutorial_tb in the Sources pane to view its contents.
The testbench defines the simulation step size and the resolution in line 1. The testbench module
definition begins on line 5. Line 15 instantiates the DUT (device/module under test). Lines 17 through
26 define the same module functionality for the expected value computation. Lines 28 through 39
define the stimuli generation and compares the expected output with what the DUP provides. Line 41
ends the testbench. The $display task will print the message in the simulator console window when the
simulation is run.
Figure 15. Selecting Simulation Sources option

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Figure 16. Simulation Sources hierarchy
2-2. Simulate the design for 200 ns using the XSim simulator.
2-2-1. Select Simulation Settings under the Project Manager tasks of the Flow Navigator pane.
A Project Settings form will appear showing the Simulation properties form.
2-2-2. Select the Simulation tab, and set the Simulation Run Time value to 200 ns and click OK.
2-2-3. Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of
the Flow Navigator pane.
Figure 17. The self-checking testbench
You will see four main views: (i) Scopes, where the testbench hierarchy as well as glbl instances are
displayed, (ii) Objects, where top-level signals are displayed, (iii) the waveform window, and
(iv) Tcl Console where the simulation activities are displayed. Notice that since the testbench used is
self-checking, the results are displayed as the simulation is run.

17
Figure 18. Simulator output
Notice that the tutorial.sim directory is created under the tutorial directory, along with several lower-
level directories.
Figure 19. Directory structure after running behavioral simulation
2-2-4. Click on the Zoom Fit button ( ) located left of the waveform window to see the entire waveform.
Notice that the output changes when the input changes.
You can also float the simulation waveform window by clicking on the Float button on the upper right
hand side of the view. This will allow you to have a wider window to view the simulation waveforms.
To reintegrate the floating window back into the GUI, simply click on the Dock Window button.
Figure 20. Float Button

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Figure 21. Dock Window Button
2-3. Change display format if desired.
2-3-1. Select i[31:0] in the waveform window, right-click, select Radix, and then select Unsigned Decimal
to view the for-loop index in integer form. Similarly, change the radix of switches[7:0] to Hexadecimal.
Leave the leds[7:0] and e_led[7:0] radix to binary as we want to see each output bit.
2-4. Add more signals to monitor lower-level signals and continue to run thesimulation for 500 ns.
2-4-1. Expand the tutorial_tb instance, if necessary, in the Scopes window and select the tut1
instance.
The swt[7:0] and led[7:0] signals will be displayed in the Objects window.
Figure 22. Selecting lower-level signals
2-4-2. Select swt[7:0] and led[7:0] and drag them into the waveform window to monitor those lower- level
signals.
2-4-3. On the simulator tool buttons ribbon bar, type 500 in the time window, click on the drop-down button
of the units field and select ns, and click on the ( ) button. The simulation will run for an additional
500 ns.
2-4-4. Click on the Zoom Fit button and observe the output.
Figure 23. Running simulation for additional 500 ns
2-4-5. Close the simulator by selecting File > Close Simulation.
2-4-6. Click OK and then click No to close it without saving the waveform.

19
Synthesize the Design Step 3
3-1. Synthesize the design with the Vivado synthesis tool and analyze the Project Summary output.
3-1-1. Click on Run Synthesis under the Synthesis tasks of the Flow Navigator pane.
The synthesis process will be run on the tutorial.v file (and all its hierarchical files if they exist). When
the process is completed a Synthesis Completed dialog box with three options will be displayed.
3-1-2. Select the Open Synthesized Design option and click OK as we want to look at the synthesis output
before progressing to the implementation stage.
Click Yes to close the elaborated design if the dialog box is displayed.
3-1-3. Select the Project Summary tab (Select default layout if the tab Is not visible) and understand the
various windows.
Figure 24. Project Summary view
Click on the various links to see what information they provide and which allows you to change the
synthesis settings.
3-1-4. Click on the Table tab in the Project Summary tab.
Notice that there are an estimated three LUTs and 16 IOs (8 input and 8 output) that are used.
Figure 25. Resource utilization estimation summary
3-1-5. Click on Schematic under the Open Synthesized Design tasks of Synthesis tasks of the Flow
Navigator pane to view the synthesized design in a schematic view.

20
Figure 26. Synthesized design’s schematic view
Notice that IBUF and OBUF are automatically instantiated (added) to the design as the input and
output are buffered. The logical gates are implemented in LUTs (1 input is listed as LUT1, 2 input is
listed as LUT2, and 3 input is listed as LUT3). Four gates in RTL analysis output is mapped into four
LUTs in the synthesized output.
Using the Windows Explorer, verify that tutorial.runs directory is created under tutorial. Under the
runs directory, synth_1 directory is created which holds several temporary sub-directories.
Figure 27. Directory structure after synthesizing the design
Implement the Design Step 4
4-1. Implement the design with the Vivado Implementation Defaults (Vivado Implementation 2013)
settings and analyze the Project Summary output.
4-1-1. Click on Run Implementation under the Implementation tasks of the Flow Navigator pane.
The implementation process will be run on the synthesis output files. When the process is completed an
Implementation Completed dialog box with three options will be displayed.
4-1-2. Select Open implemented design and click OK as we want to look at the implemented design in a
Device view tab.

21
4-1-3. Click Yes to close the synthesized design. The implemented design will be opened.
4-1-4. In the Netlist pane, select one of the nets (e.g. n_0_led_OBUF[1]_inst_i_1) and notice that the net
displayed in the X1Y1 clock region in the Device view tab (you may have to zoom in to see it).
Figure 28. Viewing implemented design
4-1-5. Close the implemented design view and select the Project Summary tab (you may have to change to
the Default Layout view) and observe the results.
Notice that the actual resource utilization is three LUTs and 16 IOs. Also, it indicates that no timing
constraints were defined for this design (since the design is combinatorial). Select the Post-
implementation tabs under the Timing and Utilization windows.
Figure 29. Implementation results
Using the Windows Explorer, verify that impl_1 directory is created at the same level as synth_1
under the tutorial_runs directory. The impl_1 directory contains several files including the report files.
4-1-6. Select the Reports tab, and double-click on the Utilization Report entry under the Place Design
section. The report will be displayed in the auxiliary view pane showing resources utilization. Note that
since the design is combinatorial no registers are used.

22
Perform Timing Simulation Step 5
5-1. Run a timing simulation.
5-1-1. Select Run Simulation > Run Post-Implementation Timing Simulation process under the
Simulation tasks of the Flow Navigator pane.
The XSim simulator will be launched using the implemented design and tutorial_tb as the top- level
module..
Using the Windows Explorer, verify that timing directory is created under the tutorial.sim > sim_1 >
impl directory. The timing directory contains generated files to run the timing simulation.
5-1-2. Click on the Zoom Fit button to see the waveform window from 0 to 200 ns.
5-1-3. Right-click at 50 ns (where the switch input is set to 0000000b) and select Markers > Add
Marker.
5-1-4. Similarly, right-click and add a marker at around 55.000 ns where the leds changes.
5-1-5. You can also add a marker by clicking on the Add Marker button ( ). Click on the Add
Marker
button and left-click at around 60 ns where e_led changes.
Figure 30. Timing simulation output
Notice that we monitored the expected led output at 10 ns after the input is changed (see the testbench)
whereas the actual delay is about 5.000 ns.
5-1-6. Close the simulator by selecting File > Close Simulation without saving any changes.
Generate the Bitstream and Verify Functionality Step 6
6-1. Connect the board and power it ON. Generate the bitstream, open a hardware session, and
program the FPGA.
6-1-1. Click on the Generate Bitstream entry under the Program and Debug tasks of the Flow Navigator
pane.
The bitstream generation process will be run on the implemented design. When the process is
completed a Bitstream Generation Completed dialog box with three options will be displayed.
This process will have tutorial.bit file generated under impl_1 directory which was generated under the
tutorial.runs directory.

23
6-1-2. Make sure that the power supply source is jumper to USB and the provided Micro-USB cable is
connected between the board and the PC. Note that you do not need to connect the power jack and the
board can be powered and configured via USB alone
6-1-3. Power ON the switch on the board.
6-1-4. Select the Open Hardware Manager option and click OK.
The Hardware Session window will open indicating “unconnected” status.
6-1-5. Click on the Open a new hardware target link.
Figure 31. Board settings
You can also click on the Open Recent Hardware Target link if the board was already targeted before.
Figure 32. Opening new hardware target
6-1-6. Click Next to see the Vivado CSE Server Name form.
6-1-7. Click Next with the localhost port selected.
The JTAG cable will be searched and the Xilinx_tcf should be detected and identified as e hardware
target. It will also show the hardware devices detected in the chain.
Figure 33. New hardware target detection

24
6-1-8. Click Next twice and Finish.

The Hardware Session status changes from Unconnected to the server name and the device is
highlighted. Also notice that the Status indicates that it is not programmed.
Figure 34. Opened hardware session
6-1-9. Select the device and verify that the tutorial.bit is selected as the programming file in the General tab.
Figure 35. Programming file
6-1-10. Right-click on the device and select Program Device… to program the target FPGA device.
6-1-11. Click OK to program the FPGA with the selected bitstream.
The DONE light will lit when the device is programmed. You may see some LEDs lit depending on the
switches position.
6-1-12. Verify the functionality by flipping switches and observing the output on the LEDs.
6-1-13. Close the hardware session by selecting File > Close Hardware Manager. 6-1-14. Click OK
to close the session.
6-1-15. Power OFF the board.
6-1-16. Close the Vivado program by selecting File > Exit and click OK.

25
Figure 36. Selecting to program the FPGA
Run the Tools in Batch Mode Using Tcl Script Step 7
7-1. Open a Vivado 2013.3 Tcl Shell window, Change the directory to c:\xup\digital\sources\tutorial
(using cd: /xup/digital/sources/tutorial command). Run the tools in a batch mode using the
provided tcl script fileby executing the following command.
source tutorial_tcl_with_sim.tcl
7-1-1. Select Start > All Programs > Xilinx Design Tools > Vivado 2013.3 > Vivado 2013.3 Tcl
Shell
to open the Tcl shell.
7-1-2. In the Tcl prompt window, change the working directory to c:\xup\digital\sources\tutorial by
executing the following command.
cd c:/xup/digital/sources/tutorial
7-1-3. Run the provided Tcl script in the batch mode by executing the following command source
tutorial_tcl_with_sim.tcl
The tools will be run and various directories will be created. The Tcl script file is shown below.
7-1-4. Close the Tcl Shell window when the execution is completed.
7-1-5. Using the Windows Explorer, browse through the generated project directory and verify that the
bitstream file is generated in the impl_1 directory.
7-1-6. Go to the tutorial_tcl_with_sim.sim > sim_1 > behave directory and view the content of the
tutorial_tb_behav.log file. Note that it contains the simulator output.

26
Figure 37. The Tcl source file
Line 1 sets the output directory path

Line 2 creates the project directory tutorial_tcl_with_sim under the c:\xup\digital\($outDir) directory
targeting Artix-7 100 part.
Line 3 adds the source file.
Line 4 imports the constraints files in which all except two I/O pins are defined Line 5 sets the top
module file
Line 6 executes the rtl analysis command
Lines 7 through 10 adds the missing I/O pins constraints
Lines 11 through 13 saves the constraints in the target xdc file located under the created project
directory
Line 14 through 17 sets up, reads, and compiles the testbenchLine 18 runs the behavioral simulation
Line 19 through 22 synthesizes and implements the design Line 23 generates the bitstream
Note that wait_on_run on lines 20 and 22 are essential as the tools run in multi-thread mode, and
since the following command uses the results generated by the previous command, the previous
command should be completed.
Figure 38. Generated directory structure
7-1-7. Close the command window.
Conclusion
The Vivado software tool can be used to perform a complete design flow. The project was created
using the supplied source files (HDL model and user constraint file). A behavioral simulation was
done to verify the model functionality. The model was then synthesized, implemented, and a
bitstream was generated. The timing simulation was run on the implemented design using the same
testbench. The functionality was verified in hardware using the generated bitstream. The design
flow was also carried out in the batch mode using the provided Tcl script.

27
EXPERIMENT NO: 01
LOGIC GATES
AIM: To Simulate and synthesize the logic Gates using Verilog code.
APPARATUS: Xilinx ISE Vivado
THEORY:
AND gate ( IC 7408) Definition:
A Logic AND Gate is a type of digital logic gate that has an output which is normally at logic level
"0" and only goes "HIGH" to a logic level "1" when ALL of its inputs are at logic level "1". The
output of a Logic AND Gate only returns "LOW" again when ANY of its inputs are at a logic level
"0". The logic or Boolean expression given for a logic AND gate is that for Logical Multiplication
which is denoted by a single dot or full stop symbol, ( . ) giving us the Boolean expression
of: A.B = Q.
Logic Diagram:
Pin Diagram:
Truth Table:
OR gate (IC 7432) Definition:
Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an output which is
normally at logic level "0" and only goes "HIGH" to a logic level "1" when one or more of its inputs
are at logic level "1". The output, Q of a Logic OR Gate only returns "LOW" again when ALL of its
inputs are at a logic level "0". The logic or Boolean expression given for a logic OR gate is that for
Logical Addition which is denoted by a plus sign, ( + ) giving us the Boolean expression of: A+B =
Q.

28
Logic Diagram:
Pin Diagram:
Truth Table:
NOT gate (IC 7404) Definition:
The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes referred to as
an Inverting Buffer or simply a Digital Inverter. It is a single input device which has an output level
that is normally at logic level "1" and goes "LOW" to a logic level "0" when its single input is at
logic level "1", in other words it "inverts" (complements) its input signal. The output from a NOT
gate only returns "HIGH" again when its input is at logic level "0" giving us the Boolean expression
of: A = Q.
Logic Diagram:
Pin Diagram:

29
Truth Table:
NAND gate (IC 7400) Definition:
The Logic NAND Gate is a combination of the digital logic AND gate with that of an inverter or
NOT gate connected together in series. The NAND (Not - AND) gate has an output that is normally
at logic level "1" and only goes "LOW" to logic level "0" when ALL of its inputs are at logic level
"1". The Logic NAND Gate is the reverse or "Complementary" form of the AND gate we have seen
previously.
Logic Diagram:
Pin Diagram:
7400
Truth Table:
NOR gate (IC 7402) Definition:
The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic OR gate with that
of an inverter or NOT gate connected together in series. The NOR (Not - OR) gate has an output
that is normally at logic level "1" and only goes "LOW" to logic level "0" when ANY of its inputs
are at logic level "1". The Logic NOR Gate is the reverse or "Complementary" form of the OR gate
we have seen previously.

30
Logic Diagram:
Pin Diagram:
Truth Table:
XOR gate (IC 7486) Definition:
Previously, we have seen that for a 2-input OR gate, if A = "1", OR B = "1", then the output from
the digital gate must also be at a logic level "1" and because of this, this type of logic gate is known
as an exclusive-OR function. If the two inputs are equal, then the output will be “0”.
Logic Diagram:
Pin Diagram:
Truth Table:

31
XNOR gate (IC 74266) Definition:
The Exclusive-NOR Gate function or Ex-NOR for short, is a digital logic gate that is the reverse or
complementary form of the Exclusive-OR. The Exclusive-NOR gate is a combination of the
Exclusive-OR gate and the NOT gate. It has an output that is normally at logic level "0" when ANY
of its inputs are at logic level "1".
Logic Diagram:
Pin Diagram:
Truth Table:
PROGRAM:
Verilog Code: Dataflow Model
module logicgates (a,b,c);

input a;
input b;
output [6:0]c;
assign c[0] = a & b;
assign c[1] = a | b;
assign c[2] = a ^ b;
assign c[3] = ~(a & b);
assign c[4] = ~(a | b);
assign c[5] = ~(a ^ b);
assign c[6] = ~a;
end module

32
Verilog Code: Behavioral Model – AND gate
module AND_behavioral (output reg Y, input A, B);

always @ (A or B) begin
if (A = = 1'b1 & B = = 1'b1) begin
Y <= 1'b1;
end
else
Y <= 1'b0;
end
end module
Verilog Code: Behavioral Model – OR gate
module OR_behavioral (output reg Y, input A, B);

if (A = = 1'b0 & B = = 1'b0) begin
Y <= 1'b0;
end
else
Y <= 1'b1;
end
end module
Verilog Code: Behavioral Model – XOR gate
module XOR_behavioral (output reg Y, input A, B);

if (A = = 1'b0 & B = = 1'b0) begin
Y <= 1'b0;
end
else if (A = = 1'b1 & B = = 1'b1) begin
Y <= 1'b0;
end
else
Y <= 1'b1;
end
end module
TIMING WAVEFORMS:
AND gate

33
OR gate
NOT gate
NAND gate
NOR gate
XOR gate
XNOR gate
RESULT:

34
EXPERIMENT NO: 02
ADDERS & SUBTRACTORS
AIM: To Simulate and synthesize Verilog code for Half-adder, full-adder, half-subtractor and full-
subtractor.
THEORY:
HALF ADDER
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
FULL ADDER
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

35
HALF SUBTRACTOR
A B Diff Borro
w
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
FULL SUBTRACTOR
A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

36
PROGRAM:
HALF ADDER – Dataflow Model
module half_adder (a,b);

input a,
input b,
output sum,
output carry );
assign sum=a ^ b ;
assign carry=a & b;
endmodule
HALF SUBTRACTOR – Dataflow Model
module Half_Subtractor(output D, B, input X, Y);

assign D = X ^ Y;
assign B = ~X & Y;
endmodule
FULL ADDER – Dataflow Model
module fulladder(
input a,
input b,
input cin,
output sum,
output carry );
assign x=a ^ b;
assign sum=x ^ cin;
assign y=x & cin;
assign z=a & b;
assign carry= y | z;
endmodule
FULL SUBTRACTOR – Dataflow Model
module full_subtractor ( a ,b ,c ,diff ,borrow );

output diff ;
output borrow ;
input a ;
input b ;
input c ;
assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule

37
RIPPLE CARRY ADDER: (4 BIT) – Structural Model

module rippe_adder(X, Y, S, Co);
input [3:0] X, Y;
output [3:0] S;
output Co;
wire w1, w2, w3;
fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3);
fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule
HALF ADDER – Structural Model

module Add_half (sum, c_out, a, b);
input a, b;
output c_out, sum;
xor (sum, a, b);
and (c_out, a, b);
endmodule
FULL ADDER – Structural Model

module full_adder(
input a,
input b,
input cin,
output s,
output cout,
wire p,q,r
);
xor(p,a,b);
and(r,a,b);
xor(sum,p,cin);
and(q,p,cin);
or(cout,q,r);
endmodule

38
HALF SUBTRACTOR – Structural Model

module half_subtractor(a, b, difference, borrow);
input a, b;
output difference, borrow;
wire x;
xor_gate u1(a, b, difference);
and_gate u2(x, b, borrow);
not_gate u3(a, x);
endmodule
FULL SUBTRACTOR – Structural Model
module full_subtractor(A, B, Bin, D, Bout);

input A, B, Bin;
output D, Bout;
wire p, q, r;
half_subtractor u4(A, B, p, q);
half_subtractor u5(p, Bin, D, r);
or_gate u6(q, r, Bout);
endmodule
TIMING DIAGRAMS:
HALF ADDER
FULL ADDER

39
RIPPLE CARRY ADDER
HALF SUBTRACTOR
FULL SUBTRACTOR
RESULT:

40
EXPERIMENT NO: 03
8-to-3 Encoder & 3-to-8 Decoder
AIM: To Simulate and synthesize 3 to 8 Decoder- 74138 & 8-3 Encoder- 74X148 using Verilog.
THEORY:
3 to 8 Decoder – IC 74138
A decoder is a multiple-input, multiple output logic circuit that converts coded inputs
into coded outputs, where the input and output codes are different. The input code generally
has fewer bits than the output code.
PIN DIAGRAM:
LOGIC DIAGRAM

41
TRUTH TABLE
8-to-3 Encoder
Pin diagram & logic diagram
Truth table
INPUTS OUTPUTS
P7 P6 P5 P4 P3 P2 P1 P0 Y(2) Y(1) Y(0)

0 0 0 0 00 01 0 0 0
0 0 0 0 00 10 0 0 1
0 0 0 0 01 00 0 1 0
0 0 0 0 10 00 0 1 1
0 0 0 1 00 00 1 0 0
0 0 1 0 00 00 1 0 1
0 1 0 0 00 00 1 1 0
1 0 0 0 00 00 1 1 1

42
PROGRAM:
3-to-8 Decoder - Dataflow Model
module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(~a&~b&~c);
assign d1=(~a&~b&c);
assign d2=(~a&b&~c);
assign d3=(~a&b&c);
assign d4=(a&~b&~c);
assign d5=(a&~b&c);
assign d6=(a&b&~c);
assign d7=(a&b&c);
endmodule
3-to-8 Decoder - Behavioral Model
module decoder3to8 (Data_in, Data_out);
input [2:0] Data_in;

output [7:0] Data_out;
reg [7:0] Data_out;
always @ (Data_in)
case (Data_in)
3'b000 : Data_out = 8'b00000001;

3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;
3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;
default : Data_out = 8'b00000000;
endcase
endmodule

43
3-to-8 Decoder - Structural Model
module decoder (din, dout);

input [2:0] din;
output [7:0] dout;
reg [7:0] dout;
wire w1,w2,w3;
not g1(w1,din[0]);
not g2(w2,din[1]);
not g3(w3,din[2]);
and g4(dout[0],w1,w2,w3);
and g5(dout[1],w1,w2, din[2]);
and g6(dout[2],w1,din[1], w3);
and g7(dout[3],w1,din[1], din[2]);
and g8(dout[4], din[0], w2,w3);
and g9(dout[5], din[0], w2, din[2]);
and g10(dout[6], din[0], din[1], w3);
and g11(dout[7], din[0], din[1], din[2]);
endmodule
8-to-3 Encoder - Dataflow Model
module encoder (din, dout);

input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
assign dout[0] = (din[1] | din[3] | din[5] |din[7]);
endmodule
8-to-3 Encoder - Behavioral Model

input [7:0] din;
output reg [2:0] dout;
always @ (din)
begin
if (din ==8'b00000001) dout <=3'b000;
else if (din==8'b00000010) dout <=3'b001;
else if (din==8'b00000100) dout<=3'b010;
else if (din ==8'b00100000) dout<=3'b101;
else dout<=3'bX;
end
endmodule

44
8-to-3 Encoder - Structural Model
input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
Or g1(dout[0],din[1],din[3],din[5],din[7]);
Or g2(dout[1],din[2],din[3],din[6],din[7]);
Or g3(dout[2],din[4]4,din[5],din[6],din[7]);
endmodule
Timing Diagrams:
3-to-8 Decoder
8-to-3 Encoder
RESULT:

45
EXPERIMENT NO: 04
8 x 1 Multiplexer -74X151 & 2x4 Demultiplexer-74X155
AIM: To Simulate and synthesize Verilog code for 8 x 1 Multiplexer-74151 and 2 x 4 De-
multiplexer-74155.
SOFTWARE REQUIRED: Xilinx ISE Vivado
THEORY:
The 151 selects one-of-eight data sources. The 151A have a strobe input which must be at a low
logic level to enable these devices. A high level at the strobe forces the W output high and the Y
output (as applicable) low.
8X1 MUX

46
1X4 DEMUX

47
PROGRAM:
8X1 MUX - Dataflow Model

module m81(output out, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
assign S1bar = ~S1;
assign S0bar = ~S0;
assign S2bar = ~S2;
assign out = (D0 & S2bar & S1bar & S0bar) | (D1 & S2bar & S1bar & S0) | (D2 & S2bar & S1 &
S0bar) | (D3 & S2bar & S1 & S0) | (D4 & S2 & S1bar & S0bar) | (D5 & S2 & S1bar & S0) | (D6 &
S2 & S1 & S0bar) | (D7 & S2 & S1 & S0);
endmodule
8X1 MUX - Behavioral Model

module Multiplexer(d0,d1,d2,d3,d4,d5,d6,d7,sel,out);
input d0,d1,d2,d3,d4,d5,d6,d7;
input [2:0] sel;
output reg out;
always@(sel)
begin
case(sel)
3'b000:out=d0;
3'b001:out=d1;
3'b010:out=d2;
3'b011:out=d3;
3'b100:out=d4;
3'b101:out=d5;
3'b110:out=d6;
3'b111:out=d7;
end case
8X1 MUX - Structural Model

module m81(out, D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
output out;
input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;
wire s0bar, s1bar, s2bar, T1, T2, T3, T4, T5, T6, T7, T8;
not_gate u1(s1bar, S1);
and_gate u4(T1, D0, s0bar, s1bar, s2bar);
and_gate u5(T2, D1, S0, s1bar, s2bar);
and_gate u6(T3, D2, s0bar, S1, s2bar);
and_gate u7(T4, D3, S0, S1, s2bar);
and_gate u8(T5, D4, s0bar, s1bar, S2);
and_gate u9(T6, D5, S0, s1bar, S2);
and_gate u10(T7, D6, s0bar, S1, S2);
and_gate u11(T8, D7, S0, S1, S2);
or_gate u12(out, T1, T2, T3, T4, T5, T6, T7, T8); endmodule

48
1X4 DEMUX - Dataflow Model
module demux_1_to_4(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3);
assign s1n = ~ s1;
assign s0n = ~ s0;
assign y0 = d& s0n & s1n;
assign y1 = d & s0 & s1n;
assign y2 = d & s0n & s1;
assign y3 = d & s0 & s1;
endmodule
1X4 DEMUX - Behavioral Model

module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din);
always @ (Y, A) begin
case (A)
2'b00 : begin Y[0] = din; Y[3:1] = 0; end
2'b01 : begin Y[1] = din; Y[0] = 0; end
2'b10 : begin Y[2] = din; Y[1:0] = 0; end
2'b11 : begin Y[3] = din; Y[2:0] = 0; end
endcase
end
endmodule
1X4 DEMUX - Structural Model
module demux_1_to_4(
input d,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);
Wire s1n, s0n;
not u1(s1n,s1);
not u2(s0n,s0);
and u3(y0,d,s0n,s1n);
and u4(y1,d,s0,s1n);
and u5 (y2,d,s0n,s1);
and u6 (y3,d,s0,s1);
endmodule

49
TIMING DIAGRAMS:
8X1 MUX
2X4 DEMUX
RESULT:

50
EXPERIMENT NO: 05
4 bit Comparator-74X85
AIM: To simulate and synthesize 4-bit comparator (7485) using Verilog code.
THEORY:
These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three
fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three
outputs. These devices are fully expandable to any number of bits without external gates. Words of
greater length may be compared by connecting comparators in cascade. The A < B, A > B, and A =
B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the
next stage handling more-significant bits. The stage handling the least-significant bits must have a
high-level voltage applied to the A = B input.
PIN DIAGRAM:
FUNCTION TABLE:
COMPARING INPUTS OUTPUTS
A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B

A3>B3 X X X 1 0 0
A3<B3 X X X 0 1 0
A3=B3 A2>B2 X X 1 0 0
A3=B3 A2<B2 X X 0 1 0
A3=B3 A2=B2 A1>B1 X 1 0 0
A3=B3 A2=B2 A1<B1 X 0 1 0
A3=B3 A2=B2 A1=B1 A0>B0 1 0 0
A3=B3 A2=B2 A1=B1 A0<B0 0 1 0

51
LOGIC DIAGRAM:
PROGRAM:
Behavioral Model:
module 4_Mag_Comp(
input [3:0]a,b,
output equal, greater, lower
);
reg greater, equal, lower;
initial greater = 0, equal = 0, lower = 0;
always @ (a or b)
begin
if (a < b)
begin
greater = 0; equal = 0; lower = 1;
end
else if (a == b)
begin
end
else
begin
end
end
endmodule
Dataflow model
module comparator_4_bit (a_gt_b, a_lt_b, a_eq_b, a,b);
input [3 : 0] a,b;
output a_gt_b, a_lt_b, a_eq_b;
assign a_gt_b = (a > b);
assign a_lt_b = (a < b);
assign a_eq_b = (a = = b);
endmodule

52
Timing Diagrams:
RESULT:

53
Experiment No: 06
D-FLIP FLOP
AIM: To simulate and synthesize D Flip-Flop (7474) using Verilog code.
THEORY:
This device contains two independent D-type positive edge triggered flip-flops. A low level at the
preset or clear inputs set or resets the output regardless of the levels of the other inputs. When preset
and clear are inactive, data at the D flip-flop input are transferred to the output on the positive going
edge of the clock pulse.
PIN DIAGRAM:
FUNCTION TABLE:
LOGIC DIAGRAM:

54
PROGRAM:
Dataflow Model
module dflipflop (q, qb, din, clkin);

input clkin, din ;
output reg q, qb;
assign q = clkin & din;
assign qb = ~q;
endmodule
Behavioral Model
module D_FF(
input D,clock,reset,
output q, qb
);
reg q;
assign qb = ~q;
always @ (posedge (clock))
begin
if (reset)
q <= 1'b0;
else
q <= D;
end
endmodule
Structural Model
module d_ff_struct(q,qbar,d,clk);
input d,clk;
output q, qbar;
not_gate not1(dbar,d);
nand_gate nand1(x,clk,d);
nand_gate nand2(y,clk,dbar);
nand_gate nand3(q,qbar,y);
nand_gate nand4(qbar,q,x);
endmodule

55
Timing Diagrams:
RESULT:

56
EXPERIMENT NO: 07
JK-FLIP FLOP
AIM: To simulate & synthesize JK Flip-Flop (74X109) using Verilog code.
THEORY:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a
clock input.

57
PROGRAM:
Behavioral Model
module JK_FF (J, K, CLK, Q, Qnot);

output Q, Qnot;
input J,K,CLK;
reg Q;
assign Qnot = ~ Q ;
always @(posedge CLK)
case({J,K})
2'b00: Q = Q;
2'b01: Q = 1'b0;
2'b10: Q = 1'b1;
2'b11: Q = ~ Q;
endcase
endmodule
TIMING DIAGRAM:
RESULT:

58
EXPERIMENT NO: 08
DECADE COUNTER
AIM: To simulate and synthesize decade counter (7490) using Verilog.
THEORY:
Each of these monolithic counters contains four master slave flip-flops and additional
gating to provide a divide-by two counter and a three-stage binary counter for which the count cycle
length is divide-by-five for the DM74LS90. All of these counters have a gated zero reset and
the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s complement
applications. To use their maximum count length (decade or four bit binary), the B input is
connected to the QA output. The input count pulses are applied to input A and the outputs are
as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained
from the DM74LS90 counters by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square wave at output QA.

59
PROGRAM:
Behavioral Model
module decade_counter(
input clock,
input reset,
output reg [3:0] q );
always@(posedge clock)
begin
if(reset)
q <=4'b0000;
else if(q<=4'b1000)
q <= q+1'b1;
else
q <= 4'b0000;
end
endmodule
Timing Diagram
RESULT:

60
EXPERIMENT NO: 09
4-BIT BINARY COUNTER 7493
AIM: To simulate and synthesize 4-bit binary counter (7493) using Verilog code.
THEORY:
The counter contains four master slave flip-flops and additional gating to provide a
divide-by two counter and a three-stage binary counter for which the count cycle length is
divide-by-eight for the 93A. All of these counters have a gated zero reset.
To use their maximum count length (decade or four-bit binary), the B input is connected
to the QA output. The input count pulses are applied to input A and the outputs are as
described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained
from the 90A counters by connecting the QD output to the A input and applying the input count
to the B input which gives a divide-by-ten square wave at output QA.
PIN DIAGRAM:
TRUTH TABLE:

61
LOGIC DIAGRAM:
PROGRAM:
module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule
Timing Diagram:
RESULT:

62
EXPERIMENT NO: 10
SHIFT REGISTER 7495
AIM: To simulate and synthesize shift register (7495) using Verilog code.
THEORY:
Shift registers area type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip -flops connected in a chain so that the output from one flip -flop
becomes the input of the next flip -flop. Most of the registers possess no characteristic internal
sequence of states. All flip - flop is driven by a common clock, and all are set or reset
simultaneously.
The basic types of shift registers are
 Serial In -Serial Out
 Serial In -Parallel Out
 Parallel In –Serial Out
 Parallel In -Parallel Out and bidirectional shift registers.
Serial In -Serial Out Shift Registers The serial in/serial out shift register accepts data serially
–that is, one bit at a time on a single line. It produces the stored information on its output also in
serial form.
PIN DIAGRAM:

63
LOGIC DIAGRAM:
PROGRAM:
Structural Model:
module ic7495(q0,q1,q2,q3,cp1,cp2,s,ds,p0,p1,p2,p3);
input cp1,cp2,s,ds,p0,p1,p2,p3;
output q0,q1,q2,q3;
wire w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
not n1(w3,s);
not n2(w7,w3);
and and1(w5,w3,cp1);
and and2(w6,cp2,s);
or or1(w8,w5,w6);
aoi a1(w9,ds,w3,w7,p0);
aoi a2(w10,q0,w3,w7,p1);
aoi a3(w11,q1,w3,w7,p2);
aoi a4(w12,q2,w3,w7,p3);
srff ff1(q0,~w9,w9,w8);
endmodule
aoi(o,a,b,c,d); //code for module aoi

input a,b,c,d;
output o;
wire w1,w2;
and(w1,a,b);
and(w2,c,d);
nor(o,w1,w2);
endmodule

64
module srff(q,s,r,clk); //code for module srff
input s,r,clk;
output reg q;
always@(negedge clk)
begin
case({s,r})
2'b00: q=q;
2'b01: q=1'b0;
2'b10: q=1'b1;
2'b11: q=1'bx;
endcase
end
endmodule
TIMING DIAGRAM:
RESULT:

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Kadapa, Andhra Pradesh, India– 516 003

Approved by AICTE, New Delhi & Affiliated to JNTUA, Ananthapuramu.

LINEAR & DIGITAL IC APPLICATIONS

DEPARTMENT OF ELECTRONICS & COMMUNICATION

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

LINEAR & DIGITAL IC APPLICATIONS

Miss Shaik Jabeen

Sri S. Munwar Ali

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

Linear and Digital IC Applications Lab (2004406)

VISION and MISSION of the College

VISION and MISSION of the Department

Program Educational Objectives (PEOs)

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

PO1 - Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

PO10 - Communication: Communicate effectively on complex engineering activities with the

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

Program Specific Outcomes (PSOs)

INSTRUCTIONS TO STUDENTS FOR WRITING THE FAIR RECORD

On the right side page of the record following has to be written:

On the Left side page of the record following has to be recorded:

1. Circuit/Program: Neatly drawn circuit diagrams/experimental set up.

ii) Unit of the observed data should be clearly mentioned

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

GENERAL RULES FOR PERSONAL SAFETY

TO PROTECT EQUIPMENT AND MINIMIZE MAINTENANCE:

1. SET MULTIRANGE METERS to highest range before connecting to an unknown source.

Equipment required for Laboratories:

1. Regulated Power supplies (RPS) - 0-30v.

2. Op-Amp Power Supplies

3. CROs - 0-20M Hz.

4. Function Generators - 0-1 M Hz.

6. Decade Resistance Boxes/Rheostats

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

LABORATORY COURSE ASSESSMENT GUIDELINES

6. The internal marks of 40 are awarded in the following manner:

The rubric parameters are as follows:

a) Write up format - Maximum Marks 10

b) Observations and Calculations - Maximum Marks 10

c) Results, Graphs and Discussion - Maximum Marks 10

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

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LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

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LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

Course LINEAR AND DIGITAL IC APPLICATIONS

Part A: Analog IC Application Lab:

Part B: Digital IC Applications:

LDICA Lab Manual Dept. of E. C. E K. S. R. M. C. E

Part A: Linear IC Applications Lab

S. No. Experiment Name Page No.

INTRODUCTION - STUDY OF IC741, IC555, IC565 & 1