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    CIAT - 1 - QP - IV ECE - DSP - Architecture

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    CIAT - 1 - QP - IV ECE - DSP - Architecture

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    Kala
    7 views2 pages

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    CIAT_1_QP_IV ECE_DSP_Architecture

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    CIAT - 1 - QP - IV ECE - DSP - Architecture

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    Kala

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    of 2

    Prince Shri Venkateshwara Padmavathy Engineering College, Ponmar, Chennai-127

    CONTINUOUS INTERNAL ASSESSMENT TEST-1


    Branch/Year/Semester: ECE/IV/VIII Date:
    EC8011 – DSP ARCHITECTURE AND
    Subject Code/Name: Regulation: 2017
    PROGRAMMING
    Max.Marks: 100 Duration: 3 hrs

    Course Outcomes:
    CO1 : Analyse the concepts of Programmable Digital Signal Processors.
    CO2 : Understand and program TMS320C5X PROCESSOR.
    CO3 : Understand and program TMS320C6X PROCESSOR.
    CO4 : Discuss, compare and select the suitable Advanced DSP Processors for real-time signal
    processing applications.
    CO5 : Understand and program Advanced Programmable DSP Processors.
    K1 – Remember K2 – Understand K3 – Apply K4 – Analyze K5 – Evaluate K6 – Create

    Answer ALL Questions.


    PART A – (10 x 2 = 20 marks)
    1. Compute the time required to execute the N instructions through four stage 2 CO-1 K-2
    pipelined and non pipelined DSP architecture.
    2. What is meant by bit I/O ports? 2 CO-1 K-1
    3. What are two types architectures commonly used to access the program & 2 CO-1 K-1
    Data memory?
    4. List out the four memory accesses/clock period required for MACD 2 CO-1 K-1
    5 How to calculate the 16 bit address for DMA? 2 CO-2 K-2
    6. Give the bit assignment format of Status register 0 2 CO-2 K-2
    7. List out the registers of serial port in C5X 2 CO-2 K-1
    8. Mention the need for AIC23 CODEC. 2 CO-3 K-2
    9. How many functional units do C6x processor 2 CO-3 K-2
    10. What is an interpolation filter? 2 CO-3 K-1

    PART B – (05 x 13 = 65 marks)


    11.a) What is pipelining and also explain how pipelining increases the 13 CO-1 K-3
    throughput efficiency?
    OR
    11.b) i) Determine the relative merits and demerits of RISC and CISC 7 CO-1 K-3
    Processors.
    6
    ii)Summarize key points of ALU and Shift registers used in PDSP
    12.a) i)Explain why the P-DSP have multiple address and data buses for internal 7 CO-1 K-3
    memory and peripherals but have only a single address and data bus for
    external memory peripherals and also explain the methods to increase the
    Memory access/clock cycle.
    ii) Compare the difference between Von Neumann and Harvard
    6
    architecture for the computer? Which architecture is preferred for DSP
    applications?
    OR
    12.b) Illustrate about the peripherals commonly available in P DSP and explain 13 CO-1 K-4
    its function individually.
    13.a) Analyze the details of C50 based DSP starter kit with necessary diagrams 13 CO-2 K-4
    OR
    13.b) Discuss how the AIC is configured in C5X with its block diagram 13 CO-2 K-4

    14.a) With a neat diagram, explain the Internal architecture of TMS320C5X,its 13 CO-2 K-3
    bus structure along with components of CPU.
    OR
    14.b) i) Classify and explain the Addressing modes of C5X with example. 7 CO-2 K-4
    i) Develop the pipelining structure of C5X with the execution of following
    program.
    ZAP 6
    BD PGM1250h
    ADD*
    SACL*-
    MAC 4500H,25H
    PGM1250H LACC*+

    15.a) Explain the C6X Pipeline operation with an example 13 CO-3 K-3
    OR
    15.b) i) Explain how a program may run using CCS environment. 7 CO-3 K-3
    ii)Explain the Instruction set in TMS320C6X Processor
    6

    PART C – (01 x 15 = 15 marks)


    16.a) (i)Explain the I/O peripherals of C6X with neat diagram in detail. 8 CO-3 K-5
    (ii)Explain the different addressing modes used in C6X performed by each
    7
    of them.
    OR
    16.b) Explain the C6X Architecture and how it is different from those of C5X 15 CO-3 K-6
    and C4X

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