Vlsi QP 21,22

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Anna University | Polytechnic | Schools
Reg. No.
Question Paper Code : X10348
B.E./B.Tech. DEGREE EXAMINATIONS NOVEMBER/ DECEMBER 2020 AND APRIL / MAY 2021
Sixth /Seventh Semester
Electronics and Communication Engineering
EC8095- VLSI DESIGN
(Common to: Electronics and Telecommunication Engineering/ Electrical and Electronics

Engineering/ Electronics and Instrumentation Engineering)
(Regulations 2017)
Time: 3 Hours Answer ALL Questions Max. Marks 100
PART- A (10 x 2 = 20 Marks)
1. Sketch a complementary CMOS gate computing Y = (AB + BC)′.

2. What is body effect?
3. What is the logical effort for two input NOR gate? (Assume the required values)
4. What is the use of transmission gates?
5. List the timing classification of Digital system.
6. Differentiate latches and flip-flops.
7. Draw the dot diagram for Wallace tree multiplier.
8. List the categories of memory arrays.
9. What is the significance of field programmable gate arrays?
10. Identify the ways to optimize the manufacturability, to increase yield.
PART- B (5 x 13 = 65 Marks)
11. a) i) Differentiate static and dynamic latches and registers. 6

ii) Obtain the first-order model relating the current and voltage for an nMOS 7
transistor in three regions of MOS operation.
OR
b) i) Explain the DC transfer characteristics of CMOS inverter. 6
ii) Estimate the delay of CMOS logic gates as the RC product of the effective 7
driver resistance and the load capacitance.
12. a) Sketch a combinational function Y = (A(B+C+D)+ E.F.G)′ using

i. Pseudo-nMOS logic 4
ii. Domino logic 4
iii. Cascode voltage switch logic. 5
OR
b) Explain the pass transistor logic and show how complementary pass 13
transistor logic and double pass transistor logic are applied for 2: 1
multiplexer.
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13.
a) i. Illustrate the circuit designs for basic latches, then build the flip-flops and 7
pulsed latches.
ii. Design the pulse registers suitable for sequential CMOS circuits. 6
OR
b) i) Describe the concept of pipelining in sequential circuits with a suitable 7
example.
ii) Sketch and explain the Monostable sequential circuits based on CMOS 6
logic.
14. a) i) Explain the carry-propagate adder and show how the generation and 6
propagation signals are framed.
ii) List the several commonly used shifters. Design the shifter that can 7
perform all the commonly used shifters.
OR
b) Illustrate the building blocks of Memory architectures and memory 13
peripheral circuitry adapted to operate for non-volatile memory.
15. a) i) Show how routing is performed in FPGA interconnect. 6

ii) Illustrate the basic building block architectures of FPGA. 7
OR
b) Explain the three main approaches commonly used for design for testability 13
(DFT).
PART- C (1 x 15 = 15 Marks)
16. a) i) Differentiate static and dynamic power in CMOS circuits. 7

ii) Sketch the 4:1 multiplexer using transmission gates. 8
OR
b) Generate the partial products using radix-4 booth encoded multiplier to 15
compute 011102 x 011012. For the same multiplier apply radix-8 booth
encoding and justify the advantages between radix-4 and radix-8 booth
multiplier.
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Reg. No. :
Question Paper Code : 40431
B.E./B.Tech. DEGREE EXAMINATIONS, NOVEMBER/DECEMBER 2021.
Sixth/Seventh Semester
Electronics and Communication Engineering
EC 8095 – VLSI DESIGN
(Common to : B.E. Electrical and Electronics Engineering/B.E. Electronics and

Instrumentation Engineering/B.E. Electronics and Telecommunication Engineering/
B.E. Instrumentation and Control Engineering/B.E. Robotics and Automation)
(Regulations 2017)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
1.
www.binils.comPART A — (10  2 = 20 marks)
How does a transmission gate produce fully restored logic output?
2. Define low noise margin and high noise margin of a CMOS inverter.
3. State the operations performed during pre charge and evaluate phase of
dynamic circuits.
4. List the sources of power dissipation in CMOS circuits.
5. What is meant by bistability?
6. Define clock skew in digital circuits.
7. Draw the circuit diagram of 1-bit binary shifter using MOS transistor.
8. State the need of a sense amplifier in a memory cell.
9. List the common techniques for ad hoc testing.
10. What are the limitations of IDDQ testing?
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Anna University, Polytechnic & Schools
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PART B — (5  13 = 65 marks)
11. (a) Derive the expression for current in cutoff, linear and saturation region
in long channel I-V characteristics.
Or
(b) Draw and explain the equivalent RC circuit for an Inverter.
12. (a) Compare the circuit implementation of 2-input multiplexer using static
CMOS, domino and dual-rail domino logic.
Or
(b) Describe how dynamic voltage scaling can reduce dynamic power
dissipation.
13. (a) Explain the circuit and working of CMOS implementation of schmitt
trigger.
www.binils.com Or
(b) Discuss the timing parameters that characterize the timing of sequential
circuit.
14. (a) Elaborate on rotate right and rotate left operations using barrel shifters.
Or
(b) Draw the NOR and NAND implementation of 4-word, 4-bit ROM.
15. (a) Describe the built-in self-test procedure.
Or
(b) Explain the factors to be considered to optimize circuits for

manufacturability.
2 40431
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PART C — (1  15 = 15 marks)
16. (a) Design a 4-bit incrementer / decrementer using the CMOS design for
1-bit incrementer / decrementer. The 1-bit logic cell designed has a
control input to control the increment or decrement operation. The truth
table for 1-bit incrementer cell is as shown in Table 1.
Table 1. Truth table for 1-bit incrementer cell
Inputs Output
Clock Ci Qn-1 Ci+1 Qn
0 0 0 0 0
1 0 0 0 0
0 1 0 0 0
1 1 0 0 1
1 1 0 0 1
0 0 1 0 0
1 0 1 0 1
0 1 1 0 0
1 1 1 1 0
Or
(b) Design a circuit described by the Boolean Function Y  A. B  C  D  E 
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using CMOS logic. Calculate the equivalent CMOS inverter circuit for
w
simultaneous switching of all inputs assuming that    5 for pMOS
L
w 
transistor and    2 for all nMOS transistor.
L
—————————
3 40431
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www.binils.

Question Paper Code : X10348

Sixth /Seventh Semester

Electronics and Communication Engineering

EC8095- VLSI DESIGN

(Common to: Electronics and Telecommunication Engineering/ Electrical and Electronics

1. Sketch a complementary CMOS gate computing Y = (AB + BC)′.

11. a) i) Differentiate static and dynamic latches and registers. 6

12. a) Sketch a combinational function Y = (A(B+C+D)+ E.F.G)′ using

15. a) i) Show how routing is performed in FPGA interconnect. 6

16. a) i) Differentiate static and dynamic power in CMOS circuits. 7

Question Paper Code : 40431

B.E./B.Tech. DEGREE EXAMINATIONS, NOVEMBER/DECEMBER 2021.

Electronics and Communication Engineering

EC 8095 – VLSI DESIGN

(Common to : B.E. Electrical and Electronics Engineering/B.E. Electronics and

Time : Three hours Maximum : 100 marks

Answer ALL questions.

How does a transmission gate produce fully restored logic output?

4. List the sources of power dissipation in CMOS circuits.

5. What is meant by bistability?

6. Define clock skew in digital circuits.

8. State the need of a sense amplifier in a memory cell.

9. List the common techniques for ad hoc testing.

10. What are the limitations of IDDQ testing?

(b) Draw and explain the equivalent RC circuit for an Inverter.

15. (a) Describe the built-in self-test procedure.

(b) Explain the factors to be considered to optimize circuits for

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