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    Vlsi Model 4-QP

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    santhosh
    This document contains a model examination for a VLSI Design course with 5 parts testing various concepts: Part A contains 10 short answer questions testing transistor channel modulation, delay models, logic gates, registers, clocking, and testing techniques. Part B has 5 long answer questions choosing between topics on delay models, differential logic, bistability, adders, decoders, and registers. Part C is a single long question choosing between a CMOS inverter analysis or FPGA building blocks. The examination covers 5 course outcomes including digital circuits, combinational/sequential logic design, arithmetic blocks, memory, and FPGA implementation testing various VLSI design concepts.

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    Vlsi Model 4-QP

    Uploaded by

    santhosh
    40 views2 pages
    This document contains a model examination for a VLSI Design course with 5 parts testing various concepts: Part A contains 10 short answer questions testing transistor channel modulation, delay models, logic gates, registers, clocking, and testing techniques. Part B has 5 long answer questions choosing between topics on delay models, differential logic, bistability, adders, decoders, and registers. Part C is a single long question choosing between a CMOS inverter analysis or FPGA building blocks. The examination covers 5 course outcomes including digital circuits, combinational/sequential logic design, arithmetic blocks, memory, and FPGA implementation testing various VLSI design concepts.

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    VLSI MODEL 4-QP-converted

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    This document contains a model examination for a VLSI Design course with 5 parts testing various concepts: Part A contains 10 short answer questions testing transistor channel modulation, delay models, logic gates, registers, clocking, and testing techniques. Part B has 5 long answer questions choosing between topics on delay models, differential logic, bistability, adders, decoders, and registers. Part C is a single long question choosing between a CMOS inverter analysis or FPGA building blocks. The examination covers 5 course outcomes including digital circuits, combinational/sequential logic design, arithmetic blocks, memory, and FPGA implementation testing various VLSI design concepts.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    40 views2 pages

    Vlsi Model 4-QP

    Uploaded by

    santhosh
    This document contains a model examination for a VLSI Design course with 5 parts testing various concepts: Part A contains 10 short answer questions testing transistor channel modulation, delay models, logic gates, registers, clocking, and testing techniques. Part B has 5 long answer questions choosing between topics on delay models, differential logic, bistability, adders, decoders, and registers. Part C is a single long question choosing between a CMOS inverter analysis or FPGA building blocks. The examination covers 5 course outcomes including digital circuits, combinational/sequential logic design, arithmetic blocks, memory, and FPGA implementation testing various VLSI design concepts.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    2129 ST.

    JOSEPH COLLEGE OF ENGINEERING


    DEPARTMENT OF ECE
    MODEL EXAMINATION
    YEAR : III ECE SEMESTER : VI
    EC8095 – VLSI DESIGN
    (REGULATION 2017)
    TIME : 3 HOURS DATE : 02/06/2021 MAX MARKS : 100
    ANSWER ALL QUESTIONS
    PART-A (10*2=20 MARKS)
    1 Write the equation for describing the channel length modulation effect in nMOS (CO1)
    transistor.
    2 Draw a RC ladder for Elmore delay with its propagation delay time, tpd. (CO1)
    3 Sketch the Source follower Pull-up logic. (CO2)
    4 Draw the footed and unfooted Inverter, NAND2 and NOR2 (CO2)
    5 Outline the working of dynamic positive edge-triggered register when clk=0. (CO3)
    6 Enumerate the scenarios of positive and negative clock skew (CO3)
    7 Discuss the inverting property of full adder. (CO4)
    8 State the Concept of large SRAMs (CO4)
    9 Point out the common techniques of adhoc testing. (CO5)
    10 List out the different approaches of Design for testability (CO5)
    PART-B (5*13=65 MARKS)
    11 a.Apply and explain briefly about the impact of RC Delay model and Elmore delay (CO1)
    model in CMOS design? (13) (or)
    b. Evaluate the Multistage Logic Networks with delay and formulate the expression (CO1)
    with an example. (13)
    12 a Assess the design of Differential Cascode Voltage Switch with Pass Gate (CO2)
    (DCVSPG). (13) (or)
    b Classify the types of power dissipation and drive the equation each parameter. (13) (CO2)
    13 a. State Bistability principle and explain in detail about the two different approaches (CO3)
    used in this. (or)
    b.Analyze and explain about True Single-Phase Clocked Register (TSPCR) and (CO3)
    TSPC Edge-Triggered register. (13)
    14 a Analyze the concept of carry look ahead adder and discuss its types. (13) (CO4)
    (or)
    b. Illustrate the concepts of faster decoder and sum-addressed decoder circuit. (13) (CO4)
    15 a Explain the manufacturing test principle with an example of digital logic circuits. (CO5)
    (13) (or)
    b. With neat sketch explain the CLB, IOB and programmable interconnects of an (CO5)
    FPGA device. (13)
    PART-C (1*15=15 MARKS)
    16 a.Design and analysis a CMOS inverter and explain the beta ratio effects and noise (CO1)
    margin. (or)
    b. Analyze and explain the building blocks of FPGA with different fusing (CO4)
    technologies. (15)

    Course Outcomes:
    CO1 Concepts of digital building blocks using MOS transistor

    CO2 Design combinational MOS circuits and power strategies


    CO3 Design and construct sequential circuits and timing systems
    CO4 Design arithmetic building blocks and memory subsystems
    CO5 Apply and implement FPGA design flow and testing

    PREPARED BY VERIFIED BY APPROVED BY

    R.SINDHUJHA AP/ECE HOD-ECE PRINCIPAL

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