Cell-Based APR Design Flow

NCTU-EE IC LAB Spring-2018

 Recall: Design Flow

✓ Cell-based Design Flow

System
System
RTL Synthesis Physical Design Integration &
Architecture
Software Test

StandardCell.lib
StandardCell.lib
design.v Synthesis tool StandardCell.lef
StandardCell.gds

Physical
Implementation Chip Layout
design_SYN.v tool

Apollo, Silicon Ensemble, IC Compiler

SoC Innovus, Magma…

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 import
floorplan
APR Design Flow powerplan
placement
CTS

✓ SoC Innovus Design Flow routing

Netlist (verilog)
IO, P/G Placement IO constraint
Timing constraint (sdc)
Specify floorplan

Power Planning

Standard Cell Placement

Timing Analysis

Pre-CTS Optimization

Clock Tree Synthesis

Timing analysis

Post-CTS Optimization

SI Driven Route

Timing/SI analysis
Output GDS,
Post-Route Optimization
Netlist

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Data Preparation

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 Tips for SoC Innovus
✓ Do not use background execution !!
✓ The executed commands are saved in innovus.cmd#
✓ The executed log files are saved in innovus.log#
✓ Save design after finishing each step !
✓ Restart from each step by freeing/reloading design
– Save Design
• innovus > saveDesign xxx.inn
– Free Design
• innovus > freeDesign
– Restore Design
• innovus > restoreDesign xxx.inn.dat CHIP
Newest
✓ Online document reference
– unix% /usr/EDI/tools/bin/cdnshelp &

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 0. Data Preparation
✓ Library files – GDSII layout
– Timing libraries (LIB) • NangateOpenCellLibrary.macro.gds
• NangateOpenCellLibrary_fast.lib • tpz.gds
• NangateOpenCellLibrary_slow.lib • HardMacro.gds
• tpz_fast.lib ✓ Timing constraint files (User Data)
• tpz_slow.lib – Generate timing constraint files from Design
• HardMacro.lib Complier
– Physical libraries (LEF) • dc_shell-t> write_sdc design_SYN.sdc
• NangateOpenCellLibrary.macro.lef ✓ Design netlist files (User Data)
• NangateOpenCellLibrary.tech.lef – Synthesized design netlist
• tpz.lef • designName_SYN.v
• HardMacro.vclef – Chip design netlist
– RC extraction (combine core_syn.v&chip_shell.v)
• best.captbl • CHIP_SYN.v
• worst.captbl – Uniquified design netlist
• best.tch (from chip_syn.v)
• worst.tch • CHIP_unique.v
– CeltIC libraries – IO pad location file
• fast.cdb • CHIP.ioc
• slow.cdb
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 0. Data Preparation - Libraries
✓ LEF Library : physical process and cell information
– Layer definition, width and spacing, default direction
– Cell size, pin position, pin metal layer

✓ LIB Library : timing information

– Operating condition, pin capacitance
– path delay, transition delay, timing constraints (ex: setup/hold)

✓ CeltIC Library (*.cdb)

– cdB model (noise model for each cell used in SI optimization phase)

✓ RC Extraction (*.captbl)
– Capacitance table
– RC extraction for further power analysis, simulation etc

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 0. Data Preparation - Design Netlist
✓ Chip design netlist: CHIP_SYN.v
– Add pad cells to synthesized design netlist
– Combine design_SYN.v and CHIP_SHELL.v
➢ cat CHIP_SHELL .v CORE_SYN.v > CHIP_SYN.v
– CHIP_SHELL.v contains I/O pads information
✓ Uniquified design netlist : CHIP_unique.v
– Uniquifies the design netlist (CHIP_SYN.v)
and writes the uniquified design to a netlist file (CHIP_unique.v)
➢ uniquifyNetlist -top CHIP CHIP_unique.v CHIP_SYN.v
– The chip design netlist must be unique for running Clock Tree Synthesis (CTS),
Scan Reorder, and In-Placement Optimization(IPO)
– When you uniquify a netlist, you create a unique module definition for every
module in the netlist.

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 0. Data Preparation – I/O File
✓ IO pad location file: CHIP.ioc
– Edit IO pad location file
• CHIP.ioc
– Syntax
• Pad: pad_instance_name direction [pad_type]
– Categories
Field Usage
Corresponding instance name of pad
pad_instance_name
in the chip netlist
S (southern pads)
E (eastern pads)
direction Specify pad location
W (western pads)
N (northern pads)
PADCORNER (corner pads)
Specify pad type PADIOVDD (IO power pads)
PADIOVSS (IO power pads)
pad_type (corner pad, IO power pad,
core power pad, and pad PADVDD (core power pads)
filler) PADVSS (core power pads)
PADFILLER (pad fillers)
PADIOVDDPOC 9
 0. Data Preparation – I/O File
Note:
✓ CHIP.ioc 1. It’s recommended to put at least one power pad pairs on each direction
2. PADIOVDDPOC must be included once in each power domain
pad
Pad: instance dir. [pad_type]
name
N
Pad: PCNR0 NW PADCORNER
Pad: PIOVDD0 N PADIOVDD

PIOVDD0

PIOVSS0
Pad: IN_CLK N

IN_CLK
Pad: PIOVSS0 N PADIOVSS PCNR0 ⋯ PCNR1
…
Pad: PCNR1 NE PADCORNER
Pad: PIOVDD3 E PADIOVDD

⋯
⋯
Pad: P_POC E PADIOVDDPOC
Pad: PIOVSS3 E PADIOVSS
… PADVSS1 PIOVSS3
Pad: PCNR2 SW PADCORNER W CORE E
Pad: PADVDD2 S PADVDD POUT P_POC
Pad: PIN1 S
Pad: PADVSS2 S PADVSS
… PADVDD1 PIOVDD3
Pad: PCNR3 SE PADCORNER

PADVDD2

PADVSS2
Pad: PADVDD1 W PADVDD

PIN1
Pad: POUT W PCNR2 ⋯ PCNR3
Pad: PADVSS1 W PADVSS
…

S
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Import Design

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 1. Invoke SoC Innovus
✓ Command to start an Encounter session
– unix% innovus

Toolbar
Tool Design views
V: visibility toggles
S: selectability toggles

Layer control
Design display area

Status

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 1. Invoke SoC Innovus

✓ Design Views
– Floorplan View: displays the hierarchical module and block
guides, connection flight lines and floorplan objects
– Amoeba View: displays the outline of modules after placement
– Physical View: displays the detailed placements of cells, blocks.

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 import
floorplan
2. Import Design powerplan
placement
CTS
✓ Import design files into Encounter environment routing

Files: CHIP_unique.v
2 Top Cell: ◆ By user: CHIP

3 Specify LEF files

4 Fill in power/GND nets

5
Set MMMC configuration
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 import
floorplan
2. Import Design - MMMC powerplan
placement
CTS
routing
✓ Multi-mode multi-corner (MMMC) timing analysis and optimization
– Multi-mode

– Multi-corner
Example
A design is required to meet 3 operating corners:
• Corner 1 - 1.1V, 0°C
• Corner 2 – 0.9V, 100°C
• Corner 3 – 1.1V, 100°C

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 import
floorplan
2. Import Design - MMMC powerplan
placement
CTS
routing
✓ Multi-mode multi-corner (MMMC) timing analysis and optimization
– In MMMC environment you must specify the lower-level information first

6 1

3
• Max Timing Libraries:
containing the worst-case conditions
for setup-time analysis

• Min Timing Libraries: 2

containing the best-case conditions for 4
hold-time analysis

5
Note:
You can save the settings to CHIP_mmmc.view by clicking save
bottom, then you can load it by using load bottom next time without
configuration set up again
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 import
floorplan
2. Import Design - Result powerplan
placement
CTS
routing

Pad

Core Area

Top-Level Module

Hard Macro

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Floorplan

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 import

3. Floorplan – Intro. floorplan

powerplan
placement
CTS
✓ Core size determination routing

– When calculating core size of standard cells, the core utilization must be decided first.
Usually the core utilization is higher than 85%
– The core size can be calculated as follows
macro + standard cell area
Core Size of Standard Cell =
core utilization
– The recommended core shape is a square, i.e. Core Aspect Ratio = 1. Hence the width
and height can be calculated as
Width = Height = Core Size of Standard Cell

• Note: because stripes and macros will be added, width and height are
usually set larger than the value calculated above
– E.g.
• No mStandard cell area = 2,000,000
• Core utilization demanded = 85% Core
Core Height
• acros
2,000,000
Core Size of Standard Cell = = 2,352,941
0.85
Core Width
Width = Height = 2,352,941 = 1534

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 import

3. Floorplan – Intro. floorplan

powerplan
placement
CTS
✓ Core margins routing

– When setup the floorplan, remember to leave enough space for power ring

✓ Core limited design or Pad limited design

– Die size determination
Stripe
• When pad width > (core width + core margin), Pad
Core
die size is determined by pads. Width

And it is called pad limited design Ring

• When pad width < (core width + core margin),
die size is determined by core.
And it is called core limited design Core Width
Core Margins

– Adding pad filler

• Provide power to pad
• There should be no spacing between pads.
Pad filler is necessary for core limited design Core limited design

Space between pads

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 import

3. Floorplan – Intro. floorplan

powerplan
placement
CTS
✓ Floorplan Purposes routing

─ Develop early physical layout to ensure design objective can be achieved

• Minimum area for low cost
• Minimum congestion for routing
• Estimate parasitic capacitance for delay calculation
• Analysis power for reliability
─ Gain early visibility into implementation issues
─ Different floorplan, different performance

Bad floorplan Good floorplan

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 import
floorplan
3. Floorplan powerplan
placement
CTS
✓ Specify floorplan routing

Some space are remained for routing.

Set a demanded value of width and height

when Hard Macro takes most of the place.
2

Hard Macro
Standard
Cell
3

• Core Limited Design • Pad Limited Design

Some space are remained for power rings.

4 (design dependent)

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 import

3. Floorplan – Hard Macro floorplan

powerplan
placement
CTS
✓ Floorplan with Hard Macro routing

– Move macro blocks to proper positions

– Place macro around the corner to improve routability

✓ Add placement blockage for macros

– Prevent the placement of blocks and
cells to reduce congestion around a
block

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 import

3. Floorplan – Add Halo to Macro floorplan

powerplan
placement
CTS
routing

✓ Add Halo

Floorplan → Edit Floorplan → Edit Halo

3

5
2 Select macro
6

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 import
floorplan
3. Floorplan - Result powerplan
placement
CTS
routing

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Powerplan

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 import

4. Powerplan – Intro. floorplan

powerplan
placement
CTS
✓ Power issue routing

– IR drop
• IR drop is the problem of voltage drop of the power and ground due to high
current flowing through the power-ground resistive network
• When there are excessive voltage drops in the power network or voltage rises in
the ground network, the device will run at slower speed
• IR drop can cause the chip to fail due to
◆ Performance (circuit running slower than specification)
◆ Functionality problem (setup or hold violations)
◆ Unreliable operation (less noise margin)
◆ Power consumption (leakage power)
◆ Latch up (short circuit)
• Prevention: adding stripes to avoid IR drop on cell’s power line

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 import

4. Powerplan – Intro. floorplan

powerplan
placement
CTS
✓ Power issue routing

– Metal migration (electromigration)

• Under high currents, electron collisions with metal grains cause the metal to
move. The metal wire may be open circuit or short circuit.
• Prevention: sizing power supply lines to ensure that the chip does not fail
• Experience: make current density of power ring < 1mA/μm

Hillock
Void

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 import

4.1. Powerplan – Global Nets floorplan

powerplan
placement
CTS
✓ 4.1 Connect global nets routing

– Connect all the 1’b1 to VDD and 1’b0 to VSS

– Add power nets and pins connection list
– Add ground nets and pins connection list

result Create 2 global nets connection list

2a
Fill in VDD VSS Connect ◆ Pins: VDD
3a 2 To Global Net: VDD
Connect ◆ Pins: VSS
3 To Global Net: VSS

2b 3b
2c
Fill in VDD VSS
3c

2d 3d
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 import

4.2. Powerplan – Power Ring floorplan

powerplan
placement
CTS
✓ 4.2 Core power ring routing
Create power ring

– Interleaving and Wire group

Without Wire group With Wire group

Without
Interleaving

Interleaving

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 import

4.2. Powerplan – Power Ring floorplan

powerplan
placement
CTS
1 routing

Power → Power Planning → Add Ring…

– In Basic tab
3 Field Fill In 2
Fill in VDD VSS
Top and Bottom Layer metal 5
Left and Right Layer metal 4
Width 8
Spacing 4

Create power ring

3

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 import

4.2. Powerplan – Power Ring floorplan

powerplan
placement
CTS
– In Advanced tab routing

6
Fill in the demanded value

Tip:
Click Apply then you can undo this step
Click OK then undo is not allowed

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 import

4.3. Powerplan – Core Power Pin floorplan

powerplan
placement
CTS
✓ 4.3 Core power pin routing

– Connect core power pads to power rings

Connect core power

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 import

4.3. Powerplan – Core Power Pin floorplan

powerplan
placement
CTS
✓ Connect core power pin routing

1
In Advanced tab
4
2 Fill in VDD VSS
5
3 Enable Pad Pins Only For Pad Pins

6 Choose All

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 import

4.4. Powerplan – Stripes floorplan

powerplan
placement
CTS
✓ 4.4 Stripes routing

– IR drop prevention

Note:
Stripes should not be mixed with core power pins

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 import

4.4. Powerplan – Stripes floorplan

powerplan
placement
CTS
1 routing

Power → Power Planning → Add Stripe…

Note: 2 Fill in VDD VSS

Use even metal for vertical stripe
Odd metal for horizontal stripe 3a 5a

3b 5b

3c 5c

4 6
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 import

4.5. Powerplan – Std. Cell Power Line floorplan

powerplan
placement
CTS
✓ Connect standard cell power line routing

Row Based PR
Standard Cell

VDD

VSS

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 import

4.5. Powerplan – Std. Cell Power Line floorplan

powerplan
placement
CTS
routing

2 Fill in VDD VSS

3 Enable Follow Pins Only

Std. cell power line

Std. cell ground line

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 import
floorplan
4.6. Add Pad Filler powerplan
placement
CTS
✓ 4.6 Add pad filler routing

– There should be no spacing between pads.

Therefore adding pad filler is necessary for core limited design
– Pad filler must be added before detailed routing, otherwise there may be
some DRC/LVS violations after pad filler insertion

Core limited design

Space between pads

Note: Only the smallest filler can
– Text command use –fillAnyGap option
innovus > addIoFiller –cell PADFILLER20 –prefix IOFILLER
From innovus > addIoFiller –cell PADFILLER10 –prefix IOFILLER
wider fillers innovus > addIoFiller –cell PADFILLER5 –prefix IOFILLER
to innovus > addIoFiller –cell PADFILLER1 –prefix IOFILLER
narrower ones innovus > addIoFiller –cell PADFILLER05 –prefix IOFILLER
innovus > addIoFiller –cell PADFILLER005 –prefix IOFILLER -fillAnyGap

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 import
floorplan
4.7. Routing Blockage and Verification powerplan
placement
CTS
✓ Add routing blockage routing

– To prevent wires routed on IO pads, we add routing blockage before routing

✓ Verify geometry
– Check if the layout so far does not violate technology design rules

✓ Verify wire connectivity

– Check if potential flaws with interconnects and pins exist

✓ Calibre DRC
– Design rule check with more rigorous rules
– For advanced process, the verifications provided by encounter may be
insufficient, so we must check Calibre DRC

Note:
It’s suggested to do the checks after powerplan

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 import
floorplan
4. Powerplan - Result powerplan
placement
CTS
✓ Tip: Save your design before adding std. cell power lines routing
Routing blockage
Power ring
stripe

Pad pin

Follow pin

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Placement

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 import
floorplan
5. Standard Cell Placement powerplan
placement
CTS
✓ Place standard cells 1
routing

Place → Place Standard Cells…

2
3
4

5 Specify your density

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 import
floorplan
5. Standard Cell Placement - Result powerplan
placement
CTS
routing

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Clock Tree Synthesis

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 import
floorplan
6. Pre-CTS Timing Analysis powerplan
placement
CTS
✓ Timing analysis routing

– Open Timing → Report Timing…

– Design Stage ◆ Pre-CTS

✓ Operations
– Trial route Negative slack should be fixed

– RC extraction
– Timing analysis

✓ Reports
– Generated reports are saved in ./timingReports/
• CHIP_preCTS.cap
• CHIP_preCTS.fanout
• CHIP_preCTS.tran
• CHIP_preCTS_all.tarpt
– Timing summary and DRVs (design rule violations)
– If the timing is MET, pre-CTS optimization can be skipped

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 import
floorplan
6. Pre-CTS Optimization powerplan
placement
CTS
✓ Optimize timing with ideal clocks routing

– Open Optimize → Optimize Design…

– Design Stage ◆ Pre-CTS
– Optimization Type ◆ Max Cap ◆ Max Tran ◆ Max Fanout

✓ Operation
– Repair Setup slack, Setup times
– Repair Design rule violations (DRVs)

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 import

7. Clock Tree Synthesis – Intro. floorplan

powerplan
placement
CTS
routing
✓ Clock problem
– Heavy clock net loading
– Long clock insertion delay
– Clock skew
– Skew across clocks
– Clock is power hungry
– Electromigration on clock net

CLK
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 import

7. Clock Tree Synthesis – Intro. floorplan

powerplan
placement
CTS
routing
✓ The process of clock tree synthesis includes
– Create clock tree spec file
– Build a buffer distribution network
– Route clock nets using CTS-NanoRoute

✓ In automatic CTS mode, Innovus will do the following things

– Build the clock buffer tree according to the clock tree specification file
– Balance the clock phase delay with appropriately sized, inserted clock buffers
FF1
delay1 buffer2

buffer1
FF2
P

delay2 buffer3 FF3

delay3 buffer4

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 import
floorplan
7. Clock Tree Synthesis powerplan
placement
CTS

✓ Update sdc constraint routing

– Add the set_propagated_clock command

✓ Generate clock spec. file

3 Add CLKBUFs

✓ Synthesize clock tree

– encounter > setCTSMode -engine ccopt_from_edi_spec
– encounter > ccopt_design -cts -ckSpec
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 import
floorplan
8. Post-CTS Timing Analysis powerplan
placement
CTS
✓ Timing analysis routing

– Open Timing → Report Timing…

– Design Stage ◆ Post-CTS
• CHIP_postCTS.cap
✓ Reports • CHIP_postCTS.fanout
– Generated reports are saved in ./timingReports/ • CHIP_postCTS.tran
– Timing summary and DRVs (design rule violations) • CHIP_postCTS_all.tarpt
– If the timing is MET, post-CTS optimization can be skipped

✓ Optimization
– Open Optimize → Optimize Design…
– Design Stage ◆ Post-CTS
– Optimization Type ◆ Max Cap ◆ Max Tran ◆ Max Fanout

✓ Operation
– Repair Setup slack, Setup times
– Repair Design rule violations (DRVs)

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 import
floorplan
9. Add Tie Hi/Lo Cell powerplan
placement
CTS
✓ Add Tie Hi/Lo Cell routing

– Connect to supply voltage or ground with resister

– Added for ESD protection
1
Place → Tie Hi/Lo Cell→ Add…

3 Select LOGIC0_X1 and LOGIC1_X1,

each shall be selected once

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Routing

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 import

10. NanoRoute – Signal Integrity floorplan

powerplan
placement
CTS
✓ Signals are subject to noise, distortion, loss and so forth in real world, routing

✓ Signal integrity is a set of measures of the quality of signal

✓ Signal Integrity (SI) Issue
– Crosstalk
– Charge sharing
– Supply noise
– Leakage
– Overshoot
– Under shoot

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 import

10. NanoRoute – Signal Integrity floorplan

powerplan
placement
CTS
routing

✓ Routing-based SI prevention

• Wiring Spacing • Layer Switching

• Parallel Wires Reducing • Net Re-ordering

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 import

10. NanoRoute – Antenna Effect floorplan

powerplan
placement
CTS
✓ Antenna Effect routing
– In a chip manufacturing process, metal is initially deposited so it covers the
entire chip
– Then, the unneeded portions of the metal are removed by etching, typically
in plasma (charged particles).
– The exposed metal collect charge from plasma and form voltage potential.
– If the voltage potential across the gate oxide becomes large enough, the
current can damage the gate oxide.

✓ Solution
– Add jumper (change metal layer)
– Add antenna cell (diode)
Jumper

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 import
floorplan
10. NanoRoute powerplan
placement
CTS
✓ NanoRoute 1
routing

Route → NanoRoute → Route…

2 NanoRoute

Routing Phase
2 ◆ Optimize Via
3 ◆ Optimize Wire
Concurrent Routing Features
◆ Fix Antenna
◆ Insert Diodes
3 Diode Cell Name: ANTENNA_X1
◆ Timing Driven
◆ SI Driven
◆ Post Route SI

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 import
floorplan
11. Post-Route Timing Analysis powerplan
placement
CTS
✓ Timing analysis (Setup) routing

– Open Timing → Report Timing…

– Design Stage ◆ Post-Route
– Analysis Type ◆ Setup

✓ Optimization (Setup)
– Open Optimize → Optimize Design…
– Design Stage ◆ Post-Route
– Optimization Type ◆ Max Cap ◆ Max Tran ◆ Max Fanout

✓ Timing analysis (Hold)

– Open Timing → Report Timing…
– Design Stage ◆ Post-Route
– Analysis Type ◆ Hold

✓ Optimization (Hold)
– Open Optimize → Optimize Design…
– Optimization Type ◆ Setup ◆ Hold
◆ Max Cap ◆ Max Tran ◆ Max Fanout
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 import
floorplan
12. Add Filler Cells powerplan
placement
CTS
✓ Add filler cells routing

– Fill all the gaps between standard cell instances

– Provide decoupling capacitances to complete connections in the standard
cell rows
1
Place → Physical Cells → Add Filler…

3 Select all FILLCELLs

(Add each cell once only)

✓ Metal filler inserted after routing, but before GDSII stream out
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Stream Out

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 13. Before Output: Verification
✓ Verify geometry
– Check if the layout so far does not violate technology design rules

Verify → Verify Geometry…

✓ Verify wire connectivity

– Check if potential flaws with interconnects and pins exist

Verify → Verify Connectivity…

✓ Calibre DRC
– Design rule check with more rigorous rules
– For advanced process, the verifications provided by encounter may be
insufficient, so we must check Calibre DRC

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 14. Stream Out Files
✓ The following files will be generated after APR design flow
– CHIP_pr.v
• Netlist file for post-layout gate-level simulation

– CHIP.sdf
• Design timing file for post-layout gate-level simulation

– CHIP.def
• Design exchange format relevant to physical layout

– CHIP.gds
• GDSII stream file for Calibre-DRC (Design Rule Check), LVS, and tape out

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