Establishing QoR Flow on Emerging Technology

Nodes
Pramod Sripathi
Sreenivasa Reddy Kasireddy
Xilinx India Technology Services
Raj Sekhar Bochkar
Synopsys India (EDA) Pvt. Ltd.

July 12-13, 2017

SNUG India

SNUG 2017 XILINX INTERNAL 1

 Agenda

Motivation
What’s New at 7nm ?
7nm Flow Implementation
7nm Congestion Challenges
7nm Timing Challenges
Summary

SNUG 2017 XILINX INTERNAL 2

 Motivation

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 Technology Nodes
Enabling The Next Generation

• 7-nm Enablement
Ramp up Readiness
for Next-Gen Node

• Maximize Flow QoR

Tune Flow To Meet Node
Promises

• Time-to-Results
Deploy Superior Technologies
to Accelerate Schedules

SNUG 2017 XILINX INTERNAL 4

 Overview of Xilinx P&R Flow
Default Flow & QoR Flow
dc_elaborate
• Default Flow

Synthesis
dc_compile
dc_dft
sf_logical_equivalence – Medium Complex blocks
promote_release
– For multiple trials
icc2_create_ndm – Netlist churns

Planning
dc_syn

Design
icc2_initialize_floorplan
icc2_dp_create_power – Early feasibility study
icc2_dp_insert_physical_cells
icc2_dp promote_icc2_dp

icc2_place_opt • QoR Flow

QoR Flow

Place &
icc2_cts_build

Route
– Timing and Congestion Critical
Default

icc2_pnr
Flow

icc2_cts_optimization
icc2_route_auto
icc2_route_opt
blocks
icc2_finish analyze_icc2 o For e.g. ARM Core
icc2_stdcell_fillers – Intensive tool optimizations
icc2_merge_gds

Finish
signoff_lvs_drc – Final & Best QoR results
smc_starrc_xtract
pt_dmsa – Runtime Intensive
analyze_icc2
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 What’s New at 7nm ?

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 What’s New in 7nm ?
• N7 is reusing some of the earlier FinFET technology features
• New Floorplan rules
– Routing tracks with Cut-Metal (CM) locations
– Macro alignment to FinFET Grid - Pin alignment to Tracks
– Special Route guide creation
• New Placement and Routing requirements
– Color-aware Placement and Legalization
• To improve pin access and routability
– Legal Index Rules
– Color-aware Routing
– Cut-metal aware M1 Routing with Metal Extension
• New Chip finishing requirements
– Colored Extraction
– Cut-Metal insertion, GDS stream-out with
SNUG 2017 XILINXCut-Metals
INTERNAL 7
 7nm Implementation Flow

SNUG 2017 XILINX INTERNAL 8

 Even Site Floorplan

• Horizontal Edge should be even multiple of site width

• Vertical Edge of core region should be even-row height

## Create floorplan area with even number of site, row

set_app_options –list {plan.flow.target_site_def
“site_def_name”}
set_app_options –list \
{plan.flow.segment_rule “horizontal_even vertical_even”}
initial_floorplan

H=Even Row H=Even Row ## Check standard cell placement area for PO layer
set_app_options –list \
{plan.flow.segment_rule “horizontal_even vertical_even”}
check_boundary_cells –precheck_segment_parity –error_view
“”

SNUG 2017 XILINX INTERNAL 9

 Routing Track Creation
• Cut-Metal (CM) handling and creating DPT layers
– Cut-Metal minimize line-end spacing
• Predefine M1 Cut locations

create_track -layer M1 -dir X -mask_pattern mask_one \

-end_grid_high_steps {$h_step1 $h_step2} \
-end_grid_low_steps {$l_step1 $l_step2} \
-end_grid_high_offset $high_offset -end_grid_low_offset $low_offset
create_track -layer M1 -dir X -mask_pattern mask_two \
-end_grid_high_steps {$h_step2 $h_step1} \
-end_grid_low_steps {$l_step2 $l_step1} \
SNUG 2017 -end_grid_high_offset $high_offset
XILINX-end_grid_low_offset
INTERNAL $low_offset 10
 Macro Alignment with FinFET Grid

• Macro’s origin must be on site horizontally

• Macro pins must be aligned with Routing tracks
• Automatic snapping & alignment for macro cells Identify
Macros

Define the FinFET Grid,

Snap settings for Macros

Snap Macros
with FinFET Grid

Check FinFET
grid violations

Flow for validating Macro Locations

SNUG 2017 XILINX INTERNAL 11
 Color-Aware P/G Routing, VIA creation

• Generate Colored P/G routes while P/G grid creation

create_pg_mesh_pattern mesh_pattern -layers \
{{vertical_layer: M1} {width: w} {pitch: p} {trim: false} \
{track_alignment: track} {mask: mask_two} {mask_constraint: M1_mc}}

• P/G Stripes pushed from Fullchip

• Automatic VIA creation at block-level
– VIA alignment with Tracks
• New stringent 7nm DRC rules
– Need DRC-Clean P/G grid
• VIA Creation trade-off
– Runtime vs DRC-clean

SNUG 2017 XILINX INTERNAL 12

 PNET Aware Placement

• Pre-Route Nets (PNET) are with lower Metal layers

– Helps in preventing IR/EM issues
• 7nm Standard cells designed with:
– High M1 Porosity
– Many Wider, Double-Height Cells
– Routing, VIA blockages
– Fat pins
• Placement and Legalization should be PNET-aware
• Xilinx Custom Cells posed many legalization issues
– Resolved with (7nm-specific) ICC2 settings

SNUG 2017 XILINX INTERNAL 13

 Color Aware Routing
• All shapes aligned to preferred location

Before Routing After Routing

SNUG 2017 XILINX INTERNAL 14
 Cut-Metal Aware Routing
• Lithography line-end Lithography line-end
– Larger EOL spacing
• Cut-Metal line-end
– Smaller EOL spacing
• Lithography & Cut-Metal line-end coexist
• Cut Metal layer reduces line-end spacing
requirement
• Zroute performs cut metal compliant Cut-Metal line-end
routing during Detail Route
First Mask Cut-Metal
Second Mask

SNUG 2017 XILINX INTERNAL 15

 Cut-Metal Handling

• Insert Metal Extension &

Cut-Metal
process_metal_extensions_cut_metals

• Remove Metal Extension &

Cut-Metal
remove_metal_extensions_cut_metals

After Routing After Cut-Metal Insertion

SNUG 2017 XILINX INTERNAL 16

 7nm Congestion Challenges

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 7nm Congestion Problem

• Routing congestion is a Non-Traditional challenge

– Power Grid with All Metal layers
– Strict Uni-Directional routing
– Colored Routing a must !
– VIA Transition - High Cost !!
• More than a Router Issue
• Address as early as Synthesis
• Explosion in number of design rules
• Physically aware Optimization
– Not sufficient to just have a space to put a cell
– Many Design rules involved with placing that cell

SNUG 2017 XILINX INTERNAL 18

 Congestion Driven Restructuring (CDR)

• New Approach for Congestion Reduction

*source: Synopsys
• Improvements
– Wirelength Reduction  Lower GRC  Fewer Route DRCs
– Lower Dynamic Power
– Neutral Total Flow Runtime

SNUG 2017 XILINX INTERNAL 19

 CDR Results
• Design Complexity
– High Density design
– High number of high fanin cells
• 4-6 input gates e.g. XOR/NAND/NOR gates
• AOI/OAI cells

Overflow (%):
Both Dirs: 134493 (4.2%)

H Routing: 81449 (3.62%)

V Routing: 53044 (2.50%)

Overflow (%):
Both Dirs: 113099 (1.82%)

H Routing: 67970 (1.16%)

V Routing: 53044 (0.86%)

Without CDR Feature With CDR Feature

SNUG 2017 XILINX INTERNAL 20
 CDR Results (2)
• Congestion benefit on large Interconnect-driven block

Layer | overflow | # GRCs has

Name | total | max | overflow (%) | max overflow
---------------------------------------------------------------
Without CDR Feature Both Dirs | 1844957 |
H routing | 1775196 |
7 | 1479390 (75.29990%) |
7 | 1412196 (143.75954%)
2

| 2
V routing | 69761 | 5 | 67194 ( 6.84025%) | 1

Layer | overflow | # GRCs has

Name | total | max | overflow (%) | max overflow
---------------------------------------------------------------
Both Dirs | 1542406 |
H routing | 1464691 |
7 | 1201817 (61.17163%) |
7 | 1128122 (114.84122%)
1 With CDR Feature
| 1
V routing | 77715 | 5 | 73695 ( 7.50205%) | 1

SNUG 2017 XILINX INTERNAL 21

 Design Closure - Congestion
Congestion Aware Optimizations
• Congestion Aware Buffering
– Global Routing enabled during place_opt
• Determines Topology for HFS nets, DRV violating nets
• Anchors buffers optimization based on Topology
– Settings
• place_opt.initial_drc.global_route_based -value 1
• Pin-Density aware Placement
– Placement done based on pin-density instead of cell-density
– Benefitted on designs with complex cells (*aoi*, *oai*, MBFF etc.)
– Eliminates the need for Cell-padding
– Settings
• place.coarse.pin_density_aware -value true

SNUG 2017 XILINX INTERNAL 22

 7nm Timing Challenges

SNUG 2017 XILINX INTERNAL 23

 7nm Timing Problem
• Interconnect resistance challenges
– Resistance increase on wires and vias
– Parasitic Variation for different color tracks
• Wires don’t scale at the same pace as cells
• Beyond Traditional optimization techniques
– Clock Uncertainty
– Multiple Modes, Multiple Corners
– Statistical analysis, extraction
– OCV-driven optimization
• Increased Parasitic & SI effects
– Interconnects thinner and run longer
– Switching at higher frequencies

SNUG 2017 XILINX INTERNAL 24

 Timing Optimization Techniques

• TNS Driven placement

– Controls the coarse placer to reduce TNS instead of optimizing WNS
– Automatically creates unique path groups on each end-point to minimize sum of worst
slacks
• place.coarse.tns_driven_placement -value high
• Global-Route based Layer Binning (GRLB)
– Enable timing driven Global-Route
– Nets are constrained with Min/Max layers for Pre-Route extraction
– Observed good improvement between Pre-Route and Post-Route timing correlation
• opt.common.use_route_aware_extraction -value true
• Two-Pass Placement
• place_opt.initial_place.two_pass -value true
• ICG Optimization
SNUG 2017 XILINX INTERNAL 25
 Placement Results

• Improved WNS by ~56% and TNS by ~24% w.r.t Default Flow

WNS Improvement (~56%) TNS Improvement (~38%)

0.25 250

0.23

228.77
0.2 200
0.21

0.2
0.18
0.17

165.95
0.15 150
0.16

0.15

0.15

0.14
0.12

116.89
0.1 100
0.11
0.1
0.09

0.09

88.07

74.6
0.05 50

62.95

57.78
47.69

45.22
42.57

35.17

30.55
19.18

14.26
0 0
func_1_ func_2_ func_3_ func_4_ func_5_ func_6_ func_7_ p p p p p p p
setup setup setup setup setup setup setup e tu e tu e tu e tu e tu e tu e tu
1 _s 2 _s _s _s _s _s _s
c_ c_ c _3 c _4 c_
5
c _6 _ 7
n n n n n n nc
Default Flow QoR Flow fu fu fu Defaultfu Flow fu QoR Flow
fu fu

Default and QoR flows have same place_opt settings

SNUG 2017 XILINX INTERNAL 26
 Advanced CCD Features
• Pre-Route Enhancements
– CCD @ Placement
place_opt.flow.enable_ccd -value true
place_opt.flow.enable_ccd_useful_skew_max|min_postpone -value skew_value
– Limit scope of skew adjustment
ccd.max_postpone -value skew_value
ccd.max_prepone -value skew_value
• Area, Power Recovery
– Enable power or area recovery from clock cells and registers
clock_opt.flow.enable_clock_power_recovery -value power|area
• Post-Route Enhacements
– CCD on Post-Route design
route_opt.flow.enable_ccd -value true

SNUG 2017 XILINX INTERNAL 27

 Final Timing Results - Setup

WNS Improvement (~35%) TNS Improvement (~24%)

0.3 450

0.29
400
0.25

392.5
350
0.2 300
0.21

0.2
0.2
0.19 250
0.18

0.17
0.17

0.15

245.52
245.3
0.16

0.15
200

0.15
0.13

0.12

0.1 150

174.8
0.11

165
100
0.05

99
50

74.8

49.9
39.7

33.5
28.2
0 0

24.6

21
18.8
func_1_ func_2_ func_3_ func_4_ func_5_ func_6_ func_7_ p p p p p p p
setup setup setup setup setup setup setup e tu e tu e tu e tu e tu e tu e tu
1 _s 2 _s _s _s _s _s _s
c_ c_ c _3 c _4 c_
5
c _6 _ 7
n n n n n n nc
Default Flow QoR Flow fu fu fu Defaultfu Flow fu QoR Flow
fu fu

SNUG 2017 XILINX INTERNAL 28

 Final Timing Results - Hold

WNS Trend NVE Improvement (~50%)

0.06 1800
0.05

1698
0.05 1600
0.05

0.05
0.04 1400

0.04

0.04
1200
0.03
1000
0.02

0.02
800

834
0.01
0.01

600
0.01

0.01
0 400
0

d d d d d
hol ol hol ol ol 200
_ _h _ _ h _h
_1 c_
2 _3 _1 _ 2

0
nc nc an an 0

53
51
n

31
18

3
2

2
fu fu fu sc sc
Default Flow QoR Flow
Default Flow QoR Flow

SNUG 2017 XILINX INTERNAL 29

 7-nm Testchip Deployment
Successfully Proving Out Full-Flow
• Full-Flow Focus from Synthesis to Signoff
– SPG flow qualification
– DC-MCMM correlation with ICC II
– UPF flow validation
– Signoff correlation
• Qualification of PnR flow variants:
– QoR flow for high frequency designs
• Target higher Fmax 5 Blocks Taped-Out to Validate
• Tradeoff in terms of larger runtime Flow and QoR
– Default flow for remaining designs

SNUG 2017 XILINX INTERNAL 30

 Summary

SNUG 2017 XILINX INTERNAL 31

 Summary
• Enabled P&R Framework for 7nm
– Timing and Congestion flows established
• Testchip Tapeout execution
– Timing closure with Default/QoR flows
– FEOL DRCs - Complete ICC2 support
– BEOL DRC Closure
• Future Ahead
– Post-Route Timing, Power and Noise Closure
– DRC Correlation between Implementation and Signoff Tools
• Tighter Design + EDA + Foundry collaboration

SNUG 2017 XILINX INTERNAL 32

 Thank You

SNUG 2017 XILINX INTERNAL 33