2007 12 ICC Incremental Training

IC Compiler 2007.
12
Incremental Training
IC Compiler CAE
Predictable Success
IC Compiler 2007.12 Update Training
Agenda
• Timing/SI
• MCMM
• Hierarchical Flow (Includes ILM)
• Low Power
• DFM & Routing
• User Interface
New commands/options added in 2007.12 highlighted in Blue
© 2007 Synopsys, Inc. (2)

(2) Predictable Success
IC Compiler 2007.12 – Timing/SI
• IC Compiler Feasibility flow
Design
Design Setup
Setup • Min Chip Technology
Floorplanning
Floorplanning • Optimization runtime improvement
• Improved report_congestion
place_opt
place_opt
• Integrated clock global router
• Fix DRCs beyond exceptions
clock_opt
clock_opt mark_clock_tree
route_opt • Layer based GR congestion map –

route_opt
User Interface
• Mixed mode extraction
• Auto extraction
Chip
Chip Finishing
Finishing
• Min delta delay correlation

signoff_opt
signoff_opt • SI run time improvement
• User Interface improvements for
noise

check_library
• Overview
Data consistency check between Logical v/s Physical libraries
Physical library database consistency check
Enhanced Tech File checking and man pages
• User Interface
check_library -mw_library_name {phys_library_name_list} -
logic_library_name {logical_library_name_list} –cell_list
{cell_list}
• User Benefit
• Identifies the library problems earlier and provided the details reports to
user
• Helps the turn around time and avoids late detection of library issues

IC Compiler Feasibility Flow
• Overview
The feasibility flow should be run before detail implementation
It helps to eliminate potential issues in early design stages
There are three main checks in the flow:
• Routeability
• Power network integrity
• Timing
• User Interface
N/A
• User Benefit
Gives faster turn around time (TAT)
Gives early prediction of timing closure

IC Compiler Feasibility Flow
•read_verilog_to_cel
•read_io_constraints
Read Netlist / Constraints •read_sdc
Initialize Floorplan
Virtual Flat Placement Floorplan •initiialize_floorplan
refinement
PNA/PNS
Refine •create_fp_placement
Power OK
PG mesh
Global Route •analyze_fp_rail
•synthesize_fp_rail
Routability OK
•route_fp_protp
Update Check Timing Environment
SDC Timing Optimization •report_congestion
Bad SDC NO NO Bad floorplan • check_fp_timing_environment
Timing OK
NO Identifies unconstrained paths,
zero wire delay timing violations,
Yes bottleneck cells, timing with virtual
psynopt
optimization to quickly identify bad
timing paths, modules
place_opt
•optimize_fp_timing
clock_opt
quick optimization
route_opt
Min Chip Technology
• Overview
Min chip preserves user’s investment in floorplan
• Floorplan is preserved (block shape, macro placements, blockages)
• Pins preserved (relative side and order, including on rectilinear edges)
Min chip supports proportional sizing of voltage areas
Min chip accounts for power routing using Power Network Synthesis
• Each voltage area may have different mesh patterns (strap pitch, layers,
rings)
Min chip supports complex I/O (multi-height, multi-ring, staggered)
• User Interface
Run the Tcl command estimate_fp_area or
GUI: Floorplan Æ Estimate Area
• User Benefit
Search for smallest routable de size
• Preserves floor planning investment
• Eliminates costly resizing iterations
Improves designer productivity

Min Chip Technology
Flow Recommendations
Design
DesignData
Data • Start with original netlist for P&R flow
(Original Netlist)
(Original Netlist)
• Minchip needs an optimized
database as an input or results will
Design
DesignPlanning
Planning be too optimistic
• Minchip produces the smallest
Detailed
DetailedImplementation
Implementation routable new floorplan
• After Minchip use original netlist and
MinChip
new floorplan for P&R flow
MinChip
Design
DesignData
Data
(Original
(Original Netlist++New
Netlist New
MinChip Floorplan)
MinChip Floorplan)
Detailed
DetailedImplementation
Implementation

Optimization Runtime Improvement
• Overview
Improved buffering runtime for optimization
• User Interface
No User Interface changes are required
• User Benefit
Average 30% runtime improvement @ place_opt stage
No QoR impact
Works with any optimizations
• Pre route optimization
place_opt, psynopt, clock_opt
• Post route optimization
route_opt

Integrated Clock Global Router (ICGR)
• Overview
2007.12 with the integrated clock global router
replaces virtual route for optimize_clock_tree
and balance_inter_clock_delay
• In prior releases clock tree implementation used virtual
route for wire delay and capacitance estimation which
caused correlation issues between clock and signal route
• User Interface
cts_integrated_global_router <true|false:default>

• User Benefit
Compared to virtual route based CTS flow, ICGR has shown
improved clock tree correlation between
• Post-cto and post clock route (average correlation within 10%)
• Post-cto and post clock/signal route( average correlation within
10%)
• CTO with ICGR run time: +20%
Note: Correlation can be further improved with clock spacing and

shielding and also the Non Default Rules

compile_clock_tree
set cts_integrated_global_router true Enable ICGR before CTO (default: false)
optimize_clock_tree
Set clock routing variables
set droute_wrongWayExtraCost 20
set groute_incremental 2
route_group –all_clock_nets
Reset clock routing variables
set droute_wrongWayExtraCost 0
set groute_incremental 0

Fix DRC Beyond Exceptions
• Overview
CTS fixes, reports and removes the DRCs beyond exceptions – stop,
sync and exclude pins
• User Interface
No Change
• User Benefit
DRC fixing is done by default during CTS
Improve TTR & QoR

Fix DRC Beyond Exceptions
• Flow log example
compile_clock_tree
CTS: clock tree synthesis summary
CTS: 2 buffer trees inserted
CTS: 17 buffers used (total size = 217.689)
CTS: summary of DRC fixing beyond exception pin
CTS: 1 buffer trees inserted
CTS: 3 buffers used (total size = 41.1845)
report_clock_tree –structure
shows the structure of new clock tree including beyond exceptions
remove_clock_tree
SUMMARY 14 buffer(s) & 0 inverter(s) are removed
Removing cells added for drc fixing beyond exceptions...
3 buffer(s) and 0 inverter(s) are removed

mark_clock_tree
• Overview
Modify clock related attributes on clock cells and nets
• Clock net NDR and routing layer
• Clock tree imported from Astro or 3rd party tool
• Fix or soft-fix sinks for routing resource adjustment
• User Benefit
Mark clock tree to identify imported clock tree and continue
clock optimization
Modify existing clock tree attributes for subsequent
optimization and routing

mark_clock_tree
• User Interface
•mark_clock_tree
-clock_trees
-clock_net
-clock_synthesized
-fix_sinks
-routing_rule
-use_default_routing_for_sinks
-layer_list
-ideal_net
-remove

mark_clock_tree
• Flow recommendations
Use this command to mark clock attributes on imported clock tree
structures for sub-sequent IC Compiler clock operations
To modify NDR rules applied on a already synthesized clock
network
• Known Limitations
ETM model internal clock pin are not supported

Mixed Mode Extraction
• Overview
Enhance extract_rc to perform detail route extraction and virtual route
estimation
• User Interface
Set the following variable to true
• set complete_mixed_mode_extraction true
• Default: false
• When mixed mode extraction will be ON by default, then for backward
compatibility, -routed_nets_only option will be added to
extract_rc and write_parasitics commands
• User Benefit
Minimized number of commands when extracting a partially routed design
(clock routed stage);
• extract_rc
• can now be replaces
• extract_rc –estimate; extract_rc
Please keep in mind that place_opt currently doesn’t support mixed mode
extraction

Auto Extraction
• Overview
Preserving parasitic is possible in 2007.12 when timing constraints
need to be removed (SDC) ; Fixes issues in auto-extraction for not
to extract if the design is not re-linked, tluplus files and temperatures
are not changed
• User Interface
Option –keep_parasitics is added to remove_sdc command
• User Benefit
Parasitics need not be re-extracted after remove_sdc
Ease of use and reduced runtime by not having to re-extract the
parasitics

Auto Extraction
• Usage /GUI
Use the -keep_parasitics option to retain the parasitics
information during remove_sdc
• remove_sdc –keep_parasitics
• Flow Recommendations
Use remove_sdc –keep_parasitics when removing CTS SDC
after clock_opt

Ignore Layers Support In Virtual Route
• Overview
To honor ignored layers in virtual route topology creation
• User Interface
No change in User Interface
• User Benefit
Improved correlation of virtual route and detail route topology when
ignored layers are used
• Ex. On a 7-metal layer design, if M6 and M7 are ignored, and
there is a Macro that blocks layers M1-M5, virtual route will now
detour around it (consistent with detail router topology)

Ignore Layers Support In Virtual Route
• Usage /GUI
No change in User Interface
extract_rc –estimate (executed stand-alone and also
invoked during pre-route optimization commands) will now
honor the ignored layers

Improved report_congestion
• Overview
report_congestion is updated to use the IC Compiler
global route to ensure consistency and convergence
• User Interface
report_congestion
• Changes to this feature are explained later
• User Benefit
Global router based congestion map and correlates with GUI
display of hotspots/overflows
Good correlation between pre route and post route stage

• Usage
report_congestion
-search_repair
-no_reroute
-grc_based
-coordinate
-search_repair
• Controls groute iteration. Default is 1 iteration. If this option is specified,
groute runs 4 iterations
-no_reroute
• In default, report_congestion automatically runs groute to generate
congestion map
-grc_based
• Reports GRC base. Worse 10 GRC reported
- coordinate
• Specify the region to report. Entire design reported by default


Layer-Based Global Route Congestion Map
• Overview
The old congestion map for display is two dimensional (x & y)
The global router is a 3 dimensional routing engine with metal layer being the
third dimension
• The demand and capacity of metal layers on the same direction is added
and displayed as one single demand and capacity
Hence, the old congestion map does not reflect the realistic picture of
congestion
• This is true if some metal layers have significant congestion and some
metal layers don’t
• User Benefit
The new congestion map allows user to display and view congestion
information per layer basis
• Congestion map is consistent with log file report
• Studying congestion on a specific layer is possible

• User Interface / GUI

(Examples)
M2 congestion hot spot Almost no congestion
is shown in the new is shown in the old
congestion map congestion map
Overflow on M2 is
cancelled out by
underflow on M4
and M6

• User Interface / GUI

There is no User Interface
change NEW
GUI: Route -> Global
Route Congestion Map

Min Delta Delay Correlation
• Overview
Coupling capacitance is partially grounded for min crosstalk delta delay
calculation to improve correlation with PTSI
• User Interface
set si_use_partial_grounding_for_min_analysis false
Feature not ON by default
• User Benefit
Better correlation in min-corner (Hold) timing
• Percentage of paths with arrival time difference less than 3% is
improved from 89% to 97%

SI Runtime Improvement
• Overview
Reduce SI analysis runtime in low effort crosstalk mode while improving the
correlation with PTSI
• User Interface
No NEW User Interface change
To Enable:
• set_si_options –analysis_effort low
• Default: medium
• User Benefit
Reduced runtime in update_timing, route_opt with SI low effort mode
• update_timing runtime reduced by 8%
• route_opt runtime reduced by 3.2%
Improved IC Compiler-PT-SI correlation in low effort mode

Xtalk User Interface Improvement
• Overview
Improved SI delta delay user interface in IC Compiler
• You get detail information on the individual aggressor
contribution
• Report the details of the active and screened aggressors
• User Interface
report_delay_calculation –crosstalk
• User Benefit
Ease of use for debugging PT-SI delta delay correlation on specific
timing arcs

Xtalk User Interface Improvement
IC Compiler report_delay_calculation - PTSI report_delay_calculation -crosstalk
crosstalk
Annotated max rise net delta delay: 0.010671 arc delay: 0.011469
Annotated max fall net delta delay: 0.000000 arc delay: 0.000800
Operating Conditions: WCCOM Library: tcbn90gthpwc
Annotated max rise net delta transition: 0.010078 pin transition: 0.450000
Annotated max fall net delta transition: 0.000000 pin transition: 0.242500
Annotated max rise net delta delay: 0.010671 arc delay: 0.011469 Reporting for Crosstalk:
Annotated max fall net delta delay: 0.000000 arc delay: 0.000800 Victim net name: n12228
Number of aggressors: 4
Number of effective (non-filtered) aggressors: 4
Annotated max rise net delta transition: 0.010078 pin transition: Victim driver rail voltage(VDD): 1.080000
0.450000 si_xtalk_analysis_effort_level: medium
si_xtalk_delay_analysis_mode: all_paths
Annotated max fall net delta transition: 0.000000 pin transition: si_analysis_logical_correlation_mode: true
0.242500 Crosstalk composite aggressor mode: disabled
Reporting for Crosstalk:
Attributes:
Victim net name: n12228
A - aggressor is Active
Number of aggressors: 4 C - aggressor is a composite aggressor
Number of effective (non-filtered) aggressors: 4 E - aggressor is screened due to user Exclusion
I - aggressor has Infinite arrival with respect to the victim
Victim driver rail voltage(VDD): 1.080000
L - aggressor is screened due to Logical correlation
N - aggressor does Not overlap for the worst case alignment
Attributes: S - aggressor is screened for Small bumps
A - aggressor is Active U - aggressor/victim RC calculation is skipped
X - aggressor is screened due to aggressor eXclusion
S - aggressor is screened
Victim is rising:
Victim is rising: Victim Coupling Driver Clocks
Net Cap Lib Cell
Victim Coupling Driver Clocks -------------- --------- ------------ ---------------
Net Cap Lib Cell n12228 0.002741 OAI21D1 FE_CLK
-------------- --------- ------------ ---------------
Aggressor Coupling Driver Clocks Attributes Switching Bump
n12228 0.002741 OAI21D1 FE_CLK Net Cap Lib Cell (ratio of VDD)
-------------- --------- ----------- ------------- ------------ ----------------
Aggressor Coupling Driver Clocks n3397 0.001798 INVD1 FE_CLK A 0.024420
n32801 0.000199 ND3D0 FE_CLK S -
Attributes Switching Bump n32807 0.000396 ND3D0 FE_CLK S -
Net Cap Lib Cell n32835 0.000348 NR2D0 FE_CLK S
(ratio of VDD) -
-------------- --------- ----------- ------------- --------
---- ----------------
n3397 0.001798 INVD1 FE_CLK A
0.024420
n32801 0.000199 ND3D0 FE_CLK S
-
n32807 0.000396 ND3D0 FE_CLK S
-
n32835 0.000348 NR2D0 FE_CLK S
-
Noise User Interface Improvement
• Overview
Improve SI static noise user interface in IC Compiler
• You get detail information on the individual aggressor contribution
• Report the details of active and screened aggressors
• User Interface
report_noise -verbose -all_violators -
slack_lesser_than slack_limit
report_noise_calculation -from from_pin -to to_pin
-significant_digits digits
• User Benefit
Ease of use for debugging PT-SI static noise correlation on specific
timing arcs

Noise User Interface Improvement
IC Compiler report_noise_calculation PTSI report_noise_calculation
Analysis mode : report_at_source
Region : below_high
Analysis mode : report_at_source
Victim driver pin : exetop0/e_dptop0/e_flag0/I27/Y
Region : below_high
Victim driver library cell : MX4X4
Victim driver pin : exetop0/e_dptop0/e_flag0/I27/Y
Victim net : exetop0/e_dptop0/e_flag0/N194
Victim driver library cell : MX4X4
Steady state resistance source : estimation set value
Victim net : exetop0/e_dptop0/e_flag0/N194
Driver voltage swing : 1.620
Steady state resistance source : estimation set value
Noise derate height offset : 0.000000
Attributes:
Noise derate height scale factor : 1.000000
A - aggressor is Active
Noise derate width scale factor : 1.000000
S - aggressor is screened
Noise effort threshold : 0.000000
Noise composite aggressor mode : disabled
Height Width Area Aggressor Attributes
Noise calculations:
---------------------------------------------------------------------------
Aggressors:
Attributes:
exetop0/e_rndm0/n35 0.028 0.843 0.012 A
A - aggressor is active
exetop0/e_rndm0/n10 0.025 0.702 0.009 A
C - aggressor is a composite aggressor
exetop0/e_rndm0/n19178 0.000 0.000 0.000 S
D - aggressor is analyzed with detailed engine
exetop0/e_rndm0/n18454 0.029 0.282 0.004 A
E - aggressor is screened due to user exclusion
exetop0/s_AEI2_0_ 0.000 0.000 0.000 S
G - aggressor is analyzed with gate level simulator
Total: 0.082 0.603 0.025
I - aggressor has infinite window
L - aggressor is screened due to logical correlation
Noise slack calculation:
S - aggressor is screened due to small bump height
X - aggressor is screened due to aggressor exclusion
Constraint type: user margin
Height Width Area Aggressor Attributes
Height Area
---------------------------------------------------------------------------
---------------------------------------------------------------------
Aggressors:
Required Time 0.567 (0.567 * 0.603) -
exetop0/e_rndm0/n35 0.028 0.843 0.012 A
Actual 0.082 (0.082 * 0.603)
exetop0/e_rndm0/n10 0.025 0.702 0.009 A
---------------------------------------------------------------------
exetop0/e_rndm0/n19178 0.000 0.000 0.000 S
Slack 0.485 0.293
exetop0/e_rndm0/n18454 0.029 0.282 0.004 A
exetop0/s_AEI2_0_ 0.000 0.000 0.000 S
Total: 0.082 0.603 0.025
Noise slack calculation:
Constraint type: user margin
Height Area
---------------------------------------------------------------------
Required Time 0.567 (0.567 * 0.603) -
Actual 0.082 (0.082 * 0.603)
---------------------------------------------------------------------
Slack 0.485 0.293

1. Timing/SI
2. MCMM
3. Hierarchical Flow (includes ILM)
4. Low Power
5. DFM & Route Rules
6. User Interface
New commands/options added in 2007.12 highlighted in

Blue

IC Compiler 2007.12 – MCMM
Design
Design Setup
Setup
Floorplanning
Floorplanning
place_opt
place_opt
•More Than 3 TLUPlus Support
clock_opt
clock_opt •Support For Netlist ECO
Commands
route_opt
route_opt •MCMM Reporting Enhancements
Chip
Chip Finishing
Finishing
signoff_opt
signoff_opt

More Than 3 TLUPlus Support
• Overview
• This feature addresses the previous limitation of using up to 3
TLUPlus in one MCMM session.
With 2007.12, the user can now use as many TLUPlus as needed
in a MCMM session.
• User Interface
No change in User Interface.
The user will use more than 3 TLUPlus files by creating more
scenarios.
• User Benefit
The users can see significant improvements in usage as they can
now optimize their design across any number of TLUPlus corners.

More Than 3 TLUPlus Support
• Usage
TLUPlus files must be set by the set_tlu_plus_files
command under the scope of each scenario
First create a scenario
Then set TLUPlus files for that scenario

Netlist ECO Commands To Support
MCMM
• Overview
insert_buffer/size_cell are MCMM compatible
• User Interface
The command selects the lib_cel from the library based on the
operating condition setting (associated with scenario), user can use
one of
• <.db file name>:<library name>/<lib_cell name>
• <library name>/<lib_cell name>
• <lib_cell name>
to specify the lib_cell

MCMM Reporting Enhancements
• New report_scenario command

Lists scenarios status
• all, active, current, CTS and leakage scenarios
Returns libraries, operating conditions, TLUPlus per scenario
• Enhancements to existing commands

Increased number of commands supporting a scenario list
Commands working on current scenario only
• Scenario now reported in report header

report_scenarios Command
****************************************
Report : scenarios
Design : small_test
Scenario(s): s1 s2
Version: A-2007.12-IC Compiler-ALPHA3
Date : Thu Sep 20 13:10:18 2007
****************************************
All scenarios (Total=4): s1 s2 s3 s4

All Active scenarios (Total=2): s1 s2
Current scenario : s2
CTS scenario : s3
Leakage-only scenario: not defined. Scenario #1: s2 is active.
Library(s) Used:
xx_worst (File: /des/90nm/LM/xx_worst.lib_T85.db)
Scenario #0: s1 is active.
Library(s) Used: Operating condition(s) Used:
xx_worst (File: /des/90nm/LM/xx_worst.lib_T85.db) Max Operating Condition: xx_worst:WORST
Max Process : 1.00
Operating condition(s) Used: Max Voltage : 1.10
Max Operating Condition: xx_worst:WORST Max Temperature: 85.00
Max Process : 1.00 Min Operating Condition: xx_worst:WORST
Max Voltage : 1.10 Min Process : 1.00
Max Temperature: 85.00 Min Voltage : 1.10
Min Operating Condition: xx_best:BEST Min Temperature: 85.00
Min Process : 1.00
Min Voltage : 1.30 Tlu Plus Files Used:
Min Temperature: 0.00 Max TLU+ file: /des/xx_worst_TLUP.tf
Min TLU+ file: /des/xx_best_TLUP.tf
Tlu Plus Files Used: Tech2ITF mapping file: /remote/tf2itf.map
Max TLU+ file: /des/xx_worst_TLUP.tf
Min TLU+ file: /des/xx_best_TLUP.tf
Tech2ITF mapping file: /remote/tf2itf.map

Commands supporting -scenario {scenario list}:
• report_timing
• report_timing_derate
• report_clock
• report_path_group
• report_net (scenario specific info only eg. -transition_times)
• report_power
• report_extraction_options
• report_tlu_plus_files
• report_constraint -all_violators/-verbose

report_path_group report_path_group -scenario

[all_scenarios]
****************************************
****************************************
Report : path_group Report : path_group
Design : small_test Design : small_test
Scenario(s): s2 Scenario(s): s1 s2 s3 s4
Version: A-2007.12-IC Compiler-ALPHA3 Version: A-2007.12-IC Compiler-ALPHA3
Date : Thu Sep 20 13:54:16 2007
Date : Thu Sep 20 13:54:16 2007
****************************************
****************************************
Critical
Critical Group Name Weight Range
Scenario
Group Name Weight Range ----------------------------------------------
Scenario
reg2reg 1.00 0.00 s1
---------------------------------------------- clk 1.00 0.00 s1
reg2reg 1.00 0.00 s2
clk 1.00 0.00 s2 Path Group clk: (Scenario: s1)
-to clk
Path Group clk: (Scenario: s2) Critical

-to clk Group Name Weight Range
Scenario
----------------------------------------------
reg2reg 1.00 0.00 s2
clk 1.00 0.00 s2
Path Group clk: (Scenario: s2)

-to clk

• Commands reporting only on current scenario now have
scenario information in the report header
•report_annotated_check •report_disable_timing
•report_annotated_transition •report_latency_adjustment_options
•report_annotated_delay •report_net
•report_attribute •report_power
•report_case_analysis •report_power_calculation
•report_ideal_network •report_noise
•report_internal_loads •report_signal_em
•report_clock_gating_check •report_timing_derate
•report_clock_tree •report_timing_requirements
•report_clock_tree_power •report_transitive_fanin
•report_delay_calculation •report_crpr
•report_delay_estimate_options •report_clock_timing
•report_transitive_fanout

****************************************
Report : net
Design : small_test
Scenario(s): s2
Version: A-2007.12-IC Compiler-ALPHA3
Date : Thu Sep 20 14:30:40 2007
****************************************
Parasitic source : LPE

Parasitic mode : RealRC
Extraction mode : MIN_MAX
Extraction derating : 85/85
Operating Conditions: WORST Library: xx_worst

Wire Load Model Mode: top
Attributes:
c - annotated capacitance
r - annotated resistance
Net Fanout Fanin Load Resistance Pins Attributes

--------------------------------------------------------------------------------
a 1 1 11.14 0.00 2 c, r
b 1 1 7.76 0.00 2 c, r
c 1 1 16.32 0.00 2 c, r
c1 1 1 9.21 0.00 2 c, r
c2 2 1 13.53 0.00 3 c, r
…
w17 1 1 9.25 0.00 2 c, r
w18 1 1 7.04 0.00 2 c, r
--------------------------------------------------------------------------------
Total 40 nets 43 40 433.19 0.00 83
Maximum 2 1 34.03 0.00 3
Average 1.08 1.00 10.83 0.00 2.08

1. Timing/SI
2. MCMM
4. Low Power
6. User Interface

IC Compiler 2007.12 – Hierarchical
Flow
Design
Design Setup
Setup
•Hierarchical Flow
Floorplanning
Floorplanning
•Plan Group Based Placement
place_opt
place_opt •Plan Group Shaping
•Clock Planning
clock_opt
clock_opt •Pin Assignment
•Budgeting Flow
route_opt
route_opt
•Black Box Support
Chip
Chip Finishing
Finishing
•ILM Enhancement
•Hierarchical Verilog Netlist
signoff_opt
signoff_opt

Hierarchical Design Flow
• Overview
2007.12 IC Compiler provides hierarchical design methodology to
divide and conquer large designs
• User Interface
Use IC Compiler Design Planning to perform hierarchical floorplanning,
check design feasibility, generate hierarchical design database
Use standard IC Compiler flow to finish block implementation
Generate ILM and FRAM models for blocks
Implement top level using ILM/FRAM
• User Benefit
Manage capacity and run time
Support hierarchical design methodology in different scenarios
• Black Box flow, Lower power, MCMM etc.

Hierarchical Design Flow
Hierarchical Design
Planning
Block level Top level
Read Netlist/constraints
Initial floorplan Load Design/ILM
Virtual Flat Placement

Load Design/SDC Replace CEL wt FRAM
Create plan group
shaping/refinement place_opt
PNA/PNS read_SDC
clock_opt
plangroup aware routing
route_opt place_opt
In Place Optimization
ILM/FRAM Generation
Set Pin Assignment Constraints
clock_opt
Pin Assignment
Timing Budgeting route_opt
Commit Hierarchy

Plan Group Based Placement
• Overview
Plan Group:
• Represents a module in the logical hierarchy that needs to be physically
implemented
• Physical implementation block inherits the shape and size of the
PlanGroup
Virtual Flat Placement in design with Plan Groups
• Place cells and hard macros of same physical implementation block
together
• User Interface
Run the Tcl Command create_plan_groups or
GUI: Floorplan Æ Create Plan Group
• User Benefit
Placement result can be used to decide
• Hard macro locations
• Locations, shapes and sizes of the physical blocks

Plan Group Shaping
• Overview
Plan Group Shaping feature :
• Places the Plan Groups based on cell distribution
• Can create both “rectangular” and “rectilinear” shapes for Plan
Groups
• Run virtual flat placement again to put cells into plan group area
• User Interface
Run the Tcl Command shape_fp_blocks or
GUI: Placement Æ Place and Shape Plan Groups
• User Benefit
Automatically Place and Shape plan group boundaries, black boxes
and other soft macros in the core area

Clock Planning
• Overview
Clock planning performs the following tasks:
Inserts anchor cells on the plan group input ports.
Generates the clock trees inside each plan group.
Defines the input pin of each anchor cell to be a float pin.
Generates the top-level clock tree.
Performs detail routing on the clock interface nets
• User Interface
set_fp_clock_plan_options Sets options for the clock planning
clock tree synthesis engine
report_fp_clock_plan_options Reports options for the clock
planning clock tree synthesis engine
compile_fp_clock_plan Performs clock planning
GUI: Clock Æ Set Clock Plan Options

Compile Clock Plan

Flow Recommendation On Clock Planning
In Place Optimization optimize_fp_timing
set_fp_clock_plan_options -
Clock Planning anchor_cell Anchor_Cell_Name
report_fp_clock_plan_options
Proto Route compile_fp_clock_plan
Extraction RC
route_fp_proto
Report Timing extract_rc

report_timing
check_fp_timing_environment
Timing Budget allocate_fp_budgets
Commit Hierarchy

Pin Assignment
• Overview
Assignment of pins on the soft marco boundaries based on user defined
constrains to achieve optimal timing and routablility
• User Interface
• set_fp_pin_constraints:
set pin constraints (including TDF file) on soft macros
• analyze_fp_routing:
use option “-list_feedthrough_nets” to output feedthrough (FT) nets;
use option “-finalize” to finalize FT nets and pins and to cut pins based on
Global Routing results.
• check_fp_pin_assignment:
reports whether pin assignment has observed pin constraints.
• check_fp_pin_alignment:
check pin alignment (provide pin detour report).

Pin Assignment
• place_fp_pins
place pins of Soft Macros from top level or within block level
• commit_fp_plan_groups:
Creates Soft Macros and place pins on each Soft Macro
• uncommit_fp_soft_macros:
converts Soft Macros to plan group.
• push_down_fp_objects:
push down objects (cells,preroute, … ) into Soft Macro
• push_up_fp_objects:
push up objects from Soft Macro back to plan group.

Pin Assignment
After placement and optimization:
mark_clock_tree
set_fp_pin_constraints (on Plan
Plangroup Aware Global Route
Groups)
set_parameter -name readPlanGroup -
value 1
route_global
Analyze Routing analyze_fp_routing -finalize
optimize_fp_timing -
Feedthrough IPO feedthrough_buffering_only
extract_rc
Budgeting allocate_fp_budgets
commit_fp_plan_groups -
Commit
push_down_power_and_ground_straps

Timing Budgeting Flow
• Overview
The objective of this feature is to generate SDC timing constraints
for block-level by
• Distributing positive and negative slack in the path
• Determines input and output delays by analyzing delays of
interblock timing arcs
• User Interface
Run the Tcl Command allocate_fp_budgets or
GUI: Timing Æ Allocate Budgets
• User Benefit
• Early detection of feasibility of top-level timing closure
• Good SDC achieves good implementation of blocks

Budgeting Based On Crosstalk Effect
• Overview
Does budgeting using noise-induced delay
Timer estimates coupling effect based on congestion map
Hierarchical Signal Integrity information will be written out on plangroup pins
Store top-level xtalk effect for block implementation
• User Interface
set enable_hier_si true
allocate_fp_budgets
Budgeter stores effective aggressor driving strength for input pins and coupling cap
across block boundary into block CEL view
Store into block MW CEL view

Cc1 Cc2 Cc3
D Q
Effective driving strength

check_fp_budget_result
• Post-Budgeting Analysis:
Generate a report containing real and budgeted delays
through a hierarchical block
• Flop-to-flop paths within blocks are not reported
• User Interface
Tcl Command: check_fp_budget_result
GUI: N/A
Must be performed during the same session as
allocate_fp_budgets

Timing-Driven Black Box Flow
• Overview
The objective of this flow is to provide you a virtual flat timing-driven
black box flow with
• Tcl commands on how to identify black box
• A complete virtual flat timing-driven black box flow with steps only for
black box flow in different color from the color for steps of traditional
virtual flat flow.
• User Interface
Flow can be executed with a script of sequence Tcl commands; or
Flow can be executed using each individual GUI operation
• User Benefit
You start the floorplan early without a complete netlist for some
modules (implemented as black boxes).

Timing-Driven Black Box Flow Summary
Read Netlist with Black Box
import_fp_black_boxes
Import Black Box; Estimate Size estimate_fp_black_boxes
save_mw_cel -hierarchy
Initialize Floorplan
set fp_bb_flow true
QTM Timing Model
create_qtm_model
Create Plan Group; Shaping; VF Placement …
save_qtm_model
Power Planning write_qtm_model
Set Black Box Pin Constraints; push_down_fp_objects (push

down cell row and P/G on
Place Black Box Pins
black box)
IPO set_fp_pin_constraints (on
black box)
Plangroup Aware Global Route
place_fp_pins (on black
box)
Analyze Routing
Feedthrough IPO
Budgeting
Commit z Step for Black Box Only

Feedthrough Net Support
• Overview
Starting with 2007.12, feedthroughs are supported throughout the IC
Compiler hierarchical flow, including ILM usage
Prior to 2007.12, ILMs could not have feedthroughs or multiple-port nets.
• You had to use the set_fix_multiple_port_nets command
before block level synthesis & model creation (FRAM and ILM)
• No longer required in 2007.12
• User Interface
No User Interface change
• User Benefit
Provides consistent support throughout the hierarchical flow, where
feedthroughs may be the best solution (i.e. for routing through blocks)
Applies to both signal and clock nets
• Top-level CTS supports the use of clock feedthroughs on ILM blocks

Nested ILM Support
• Overview
Nested ILMs are fully supported Block2
throughout the hierarchical flow from ILM1
Nested
2007.12 ILM
The feature targets very large designs
where multiple levels of abstraction are
used
• User Interface
create_ilm
• User Benefit
Inner ILMs are transparently absorbed into upper level ILM, so that only
the logic involved in the upper level ILM’s timing paths are retained from
lower level ILMs
This helps to minimize the size of the upper level ILM and keep the
overall memory footprint small.
Compact ILM Support
• Overview
• Reduces ILM size by including only the timing critical portion of the
interface logic
For each block-level port, retains only the most critical paths (i.e. those
related to max_rise, max_fall, min_rise, min_fall corners)
• User Interface
Block-level: create_ilm –compact
Top-level: create_ilm_models –compact {list of reference
blocks}
• User Benefit
Smaller memory footprint than regular ILMs is possible
Results in faster top-level runtime

CTS Supports ILMs
• Overview
IC Compiler CTS now supports clocks created inside ILM and
those going through ILM
It also supports clock exceptions defined on ILM ports and
inside ILM
• User Interface
All new features are on by default
• User Benefit
Faster runtime and uses less memory
Ease of Use in the top level flow

CTS Support For ILM
Guide Generated clock
B
buffer Top-level FFs driven
CLK
by ILM generated clock
Guide
A Buffer
Top-level FFs driven

by ILM muxed clock
ILM Muxed clock C
Top-level FFs
driven by CLK
• CTS adds guide buffers to ILM clock inputs & outputs

• Nets between guide buffers are marked with a ‘dont_buffer_net’
• CTS honors clock definitions and clock exceptions inside ILM and/or on I/O
ports of ILM
• CTS synthesizes the tree for top-level FFs after ports B and C and driven by CLK

Writing Out a Full Verilog Netlist
• You can write out a full Verilog netlist (e.g. for handoff to
PrimeTime) for hierarchical designs containing ILMs
• It only takes one command to do this:
write_verilog -macro_definition
Full_Design.vg
CEL views (full block level designs) are written out for all
blocks modeled by ILMs

1. Timing/SI
2. MCMM
4. Low Power
6. User Interface

IC Compiler 2007.12 – Low Power
Design
Design Setup
Setup • Pre CTS Optimization
• Simultaneous PNS/PNA
Floorplanning
Floorplanning • MTCMOS Design Planning &
Exploration
place_opt
place_opt • UPF
User Interface
clock_opt Enhancement
clock_opt
UPF Flat Flow
Recommendations In
route_opt
route_opt 2007.12
• MV Checker
Chip
Chip Finishing
Finishing
• Adaptive Leakage Optimization
(ALO)
signoff_opt
signoff_opt

Optimize Pre CTS Design For Power
• Overview
The objective of this feature is to optimize the placed design for power by
• Physical optimization of Integrated Clock Gating (ICGs) cells, and
• Low power placement
• User Interface
Set options to enable clock gate optimization and low power placement. By
default both these options are false
set_power_options –clock_gating true

-low_power_placement true
Run optimize_pre_cts_power
optimize_pre_cts_power or
clock_opt –power

Optimize Pre CTS Design for Power
• User Benefit
Improvement in power (average 10%), with minimal impact to
timing and CTS QoR
• Significant improvement is seen on designs with large number
of clock gates which have small fan out
• Power improvement comes with a cost of runtime

Optimize Pre CTS Design For Power
Using this feature with IC Compiler Using this feature with IC Compiler
default flow low power flow
IC Compiler pre IC Compiler pre

Set clock placement CEL placement CEL
options before view view
power aware Set clock options Set clock options
placement is set_clock_tree_options set_clock_tree_options
done; CTS is Set clock tree references Set clock tree references
set_clock_tree_references set_clock_tree_references By default, both
run under the
Set clock tree exceptions Set clock tree exceptions clock gate
hood during
set_clock_tree_exceptions set_clock_tree_exceptions optimization and
power aware
low power
placement
set_power_options set_power_options placement are
–clock_gating true –clock_gating true disabled; only
–low_power_placement true –low_power_placement true leakage
–leakage false –leakage true optimization is on
by default when –
place_opt place_opt -power power is used
clock_opt -power clock_opt -power
route_opt route_opt -power

Simultaneous PNS/PNA in MVDD
Design
• Overview
The objective of this feature is to synthesize multiple power networks on
multiple voltage areas with user specified P/G constraints at same time.
• User Interface
Set four groups of power network synthesis constraints for each voltage
set_fp_rail_voltage_area_constraints -voltage_area
-nets –layer –global –ring_nets
Run
synthesize_fp_rail
-synthesize_voltage_area -power_budget
• User Benefit
To generate multiple power networks on different voltage area concurrent to
reduce turn around time.
To create common ground over multiple voltage area, common grounds
transition smoothly among voltage areas.
PNS- Power Network Synthesis, PNA- Power Network Analysis

MTCMOS Design Planning
• Overview
The objective of this feature is to explore MTCMOS planning
• User Interface
explore_header_footer
To explore MTCMOS cell placement and IR drop, based on the

inserted MTCMOS
• User Benefit
Insert and place MTCMOS array to explore if whole chip IR drop
meets IR drop target with inserted MTCMOS array

MTCMOS Design Planning
MW design lib & floorplan creation
voltage area (power domain)
creation and planning
virtual flat placement
create base power mesh
power network creation and analysis explore_header_footer
MTCMOS cell explorer

add_header_footer_cell_array
power switch insertion connect_virtual_pg_net
pre route power switch cell
optimize_header_footer
power network analysis (preroute main and virtual pg
net in physical)
LS / ISO insertion
(recommend done in logic synthesis)
analyze_fp_rail
placement refine and routeability check)
place_opt / clock_opt / route_opt

Additional Step

Unified Power Format (UPF)
• Overview
UPF 1.0 key commands supported in IC Compiler
Binary flow through MW recommended
Automatic pg derivation based on UPF power intent
Special cells insertion (Isolation Cells; Retention Register) must be done in Design
Compiler as in non-upf mode
• Libraries need to have power and ground (PG) pin definitions
Customer Consumable Application Note on Library requirements for
PG Pin syntax Modeling : https://solvnet.synopsys.com/retrieve/022443.html
Level Shifter and Isolation Cell Modeling :
https://solvnet.synopsys.com/retrieve/020279.html
Switch Cell Modeling : https://solvnet.synopsys.com/retrieve/020281.html
Retention Cell Modeling: https://solvnet.synopsys.com/retrieve/020282.html
Always ON cell Modeling : https://solvnet.synopsys.com/retrieve/022442.html
• Please refer to IC Compiler 2007.12 User Guide for ICC UPF methodology

User Interface Enhancement For
UPF Support
•Overview create_power_domain
remove_power_domain
New UPF objects have
report_power_domain
been added to Milkyway
database and User create_supply_port
Interface remove_supply_port
•User Interface report_supply_port

set_domain_supply_net
14 new Tcl User Interface
create_supply_net
commands are added to
IC Compiler to manipulate connect_supply_net
those new UPF objects report_supply_net
•Usage/GUI remove_supply_net
•New Tcl User Interface create_power_switch

commands are: remove_power_switch
report_power_switch

User Interface Enhancement For UPF
Support
IC Compiler must be in UPF mode, otherwise these new 14
User Interface commands won’t be available.
A design must be loaded before any of these new
commands could be executed successfully
Commands need GALAXY-MV feature license.
• (i.e. create_*, remove_*,
set_domain_supply_net, and
connect_supply_net)
• Except all of the report_* commands
Minimal runtime and memory impact for the new commands.

UPF: Recommendation In 2007.12 MV
Flat Flow (upf_mode)
open_mw_cel
•VA creation
•Switch cell mapping + insertion
check_mv_design
Design Planning phase

•Secondary power pin routing
•check_physical_design
•derive_pg_connection
place_opt
Note:
Libraries must have power and ground (PG)
clock_opt Pin Connections
Please refer to 2007.12 User Guide

route_opt
for Flow Details
Chip finishing
save_upf Highlighted are only applicable to
upf_mode

MV Checker
• Overview
Existing check_mv_design addresses logical checking only
Lack of physical analysis and checking capability for MV
designs
A debug utility to check the validity of user constraints
• Usage /GUI
check_physical_design –for_mv

MV Checker
•User Benefit
The report from checking the physical
constraints helps debug and guides
your error corrections
• Report and count of special cells
(level shifters, isolation cells etc.)
in the design
• Report of special cells that are
fixed placement or in RP blocks
• If the voltage area site rows
contains the required site-types
• Utilization of always-on power
wells to determine the size of
power wells
• If voltage area contains fixed cells
located outside
• Absence of guard-band
• Absence of power domain in
association with voltage area

Adaptive Leakage Optimization (ALO)
• Overview
Improves leakage optimization QoR
ALO makes place_opt, clock_opt and route_opt
leakage aware
• Enables optimization to use as many low leakage cells as
possible
• User Interface
Off by default. To enable ALO,
set adaptive_leakage_opto true
• User Benefit
Average 15% lower leakage power than 2007.03 after
route_opt
Note: Runtime hit of up to 10% is expected for overall flow

Adaptive Leakage Optimization (ALO)
• Usage /GUI
To use the ALO, the user interface remains the same
set adaptive_leakage_opto true
…
set target_library “hvt.db lvt.db”
…
set_power_options –leakage true
place_opt –power
…
clock_opt –power
…
route_opt –power
…

1. Timing/SI
2. MCMM
3. Hierarchical Flow (Includes ILM)
4. Low Power
6. GUI

IC Compiler 2007.12 – Route Rules
Design
Design Setup
Setup
Floorplanning
Floorplanning
•Via Farm Rule
place_opt
place_opt •Poly Contact Enclosure
clock_opt
clock_opt
•Area Based Antenna Rule
•Coaxial Shielding
route_opt
route_opt •Via Enclosure
•Parallel Length Dot Short
Chip
Chip Finishing
Finishing
signoff_opt
signoff_opt

Via Farm Rule
• Overview
This is an enhancement for PG Route Via Farm Rule to honor the
rule specified in technology file on via farms spacing and maximum
number of rows only in the longer direction of wires intersection
• User Benefit
Design satisfies specified via farm rule on PG wires

Via Farm Rule
• Existing via farm rule

maxNumRows = 2
viaFarmSpacing = spacing
viaFarmSpacing
• New via farm rule

maxNumRows = 2
viaFarmSpacing = spacing
viaFarmLongDirection = 1
viaFarmSpacing

Via Farm Rule
• Usage
For existing via farm rule, specify the following in the
ContactCode section of the technology file:
• maxNumRows = number
• viaFarmSpacing = spacing
For the new via farm rule, specify the following in the Contact
Code section of the technology file:
• maxNumRows = number
• viaFarmSpacing = spacing
• viaFarmLongDirection = 1

Poly Contact Enclosure
• Overview
In 45nm design, poly contact requires different metal enclosure with respect
to metal width and projection/parallel length to the adjacent metals
• User Interface
New droute options are added to trigger the metal extension rule
set_droute_options –name M1FloatingSpaceForViaOffLimit \
–value 0.08
set_droute_options –name M1FloatingParaLenForViaOffLimit \
–value 0.27
• User Benefit
Drouter shifts the via to meet metal enclosure rule if the tech file variables
and droute options were defined

Poly Contact Enclosure
• Usage /GUI
Metal enclosure of poly contact =0.015 if width of W1 or W2 >= 0.11,
space < 0.08 and projection/parallel length > 0.27
This rule is ignored if double contacts with cut spacing < 0.11
W1 DesignRule {
W2
S layer1 = “METAL1"
layer2 = “CO"
endOfLineEncTblSize = 2
X1 endOfLineEncSideThreshold = (0.11, 0.21)
X2 fatWireViaKeepoutMinSize = ( 2, 2)
P fatWireViaKeepoutEnclosure = ( 0.015, 0 )
}
S is defined in droute option M1FloatingSpaceForViaOffLimit = 0.08

P is defined in droute option M1FloatingParaLenForViaOffLimit = 0.27
X1/X2: fatWireViaKeepoutEnclosure
Area Based Antenna Rule
• Overview
In general, antenna is checked by considering antenna ratio
(antenna_area/gate_size). With this new enhancement, router
is able to consider antenna by area and insert a diode at a specific
distance to gate.
• User Interface
New Tcl command defines antenna area rule
• define_antenna_area_rule
-mode
<ignore_lower_layers|include_lower_layers|inclu
de_all_lower_layers>
-max_area max_metal_area
[-diode_distance diode_distance]

• Usage /GUI Metal3
VIA2
Metal2
VIA1
Metal1
Gate diode_distance = 200
Define/report antenna area rules in IC Compiler_shell:

define_antenna_area_rule -mode ignore_lower_layers \
-max_area 50 -diode_distance 200
report_antenna_rules -output dump.rule lib_name
If area of metal3 violates max_area=50, then a diode must be placed within

the diode_distance to protect the gate from excessive charges

• User Benefit
Router detects the area-base-antenna violation and uses
metal-splitting (route_search_repair) or insert a diode
(insert_diode) to overcome the violation

Coaxial Shielding
• Overview
In general, shielding only takes place on the same layer
IC Compiler shields a net with same, upper and lower (coaxially)
metal layers.
The upper or lower shields are placed at one another track
• User Interface
New options are added to both GUI and Tcl command
create_auto_shield
• [-coaxial_below]
• [-coaxial_above]
• User Benefit
Coaxial shielded nets can have better noise-resistance

Coaxial Shielding
• Usage / GUI
M3/M5 • Upper and lower shields are
placed at one another track
M2/M4
Clock net
M4 Shielding Net
M5
VIA34 M3 Clock Net M4
M3
Cross-view
Top-view
Coaxial Shielding
Route specific group of nets first and then do coaxial shielding
Long runtime if coaxial shields are created in a complete routed
design

Parallel Length Dot Short
• Overview
Provides the detection and fixing floating antenna violation with
respect to floating metal’s area and parallel distance and spacing to
the adjacent metal wire
• User Interface
report_antenna_ratio to report floating antenna violation
• A new droute option is added to setup the detection/fixing mode:

set_droute_options –name floatingWireMode –value 1
;; range [0,2], default=0, stored in cell;
;; 0: fixing based on antenna conx (if any)
;; 1: fixing based on floating antenna conx only
;; 2: fixing based on floating antenna conx only
(ignore violations on user routes)

Parallel Length Dot Short – User
Interface
set_droute_options -name m1FloatingWireArea -value 70.000
set_droute_options -name m1FloatingWireSpacing -value 10
set_droute_options -name ignoreFloatingWireSpacing -value 0

set_droute_options -name M1FloatingWirePLength1 -value 0.0
set_droute_options -name M1FloatingWirePLMinSpc1 -value 3.0

Parallel Length Dot Short
• User Benefit
Reports floating antenna violation
Fixes floating antenna violation by Search & Repair
Set all constraints by drouter variable then fix “dot short” by Search
and Repair
Floating antenna does not check on pre routes

DRC Rules Support In IC Compiler
2007.12
• For More details on the DRC Support in IC Compiler
• 45 nm DRC Support in IC Compiler
• https://solvnet.synopsys.com/retrieve/021298.html
• 65 nm DRC Support in IC Compiler
• https://solvnet.synopsys.com/retrieve/018370.html

1. Timing/SI
2. MCMM
3. Hierarchical Flow (Includes ILM)
4. Low Power
6. User Interface

IC Compiler 2007.12 – User Interface
Design
Design Setup
Setup
Floorplanning
Floorplanning
place_opt
place_opt
clock_opt
clock_opt • New Highlight tool
• Show GUI Dialog
route_opt
route_opt •check_library
Chip
Chip Finishing
Finishing
signoff_opt
signoff_opt

New Highlight Tool
• Highlights
Allows highlighting objects w/o making/changing selection
Allows highlighting objects with their original object colors
Allows highlighting nets of the chosen wire segments
Allows query on highlighted objects
• Usage
Click on the “highlighter” tool icon in the “Mouse Tools” toolbar
Check the options in the “Highlight Tool Options” command dialog
Check on/off the menu item “Highlight->Highlight Using Object
Color”
Check on/off the menu item “View->InfoTip

New Highlight Tool
Highlight with Highlight with

highlight color object color

New Highlight Tool

Show GUI Dialog
• Show GUI Dialog Or Menu Locations

Bring up the corresponding GUI command dialog box of a
given Tcl command (without knowing & choosing the menu
item)
Show the menu locations of a given group of Tcl commands
• Usage
icc_shell> GUI_show_form route*
icc_shell> GUI_show_form place_opt

Show GUI Dialog

New Command Check_library
•check_library command has been implemented in
DC-T and IC Compiler in 2007.12 release
• Recommendation is to use this command before/after you
setup your design and make sure the libraries do not have
problems
• You can perform selective checks by setting the options
using set_check_library_options
• If no options are set using
set_check_library_options, check_library will
perform default checking
• You can report the options set by
set_check_library_options using the command
report_check_library_options

Types Of Checks Currently Available
Number Checks performed ( Logical v/s Physical ) Option
1 If no options are specified in set_check_library_options, by No Option specified

default, it will check for missing cells and pins and
mismatched pins including pg_pin’s in .lib vs. Power and
Ground pins in Milkyway
2 Checks area attribute of cells in logical library vs. actual area -cell_area
by cell PR boundary in physical library
3 Checks cell PR boundary and pins in physical library among a -cell_footprint

class of cells with the same cell_footprint attribute
4 Checks and reports bus delimiters in logical and physical -bus_delimiter

libraries

Types of Checks Currently Available
Number Checks performed ( Physical Library checks ) Option
1 Cell view vs. FRAM view in reference library with missing -view_comparison
views and mismatched views (e.g. earlier FRAM views)
reported
2 Missing antenna property for cells and antenna rules in the -antenna
layers,
Missing signal EM rule -signal_em
3 Cells with identical names in different reference libraries with -same_name_cell

names of cells reported
4 Report boundaries for (macro) cells, rectilinear or -rectilinear_cell

rectangular, and coordinates
5 Check and report physical properties (e.g. pin types, cell -phys_property {place
symmetry, preferred routing direction, tile pattern, route cell}
pr_boundary, and wire_track)

Types of Checks Currently Available
Number Checks performed ( Physical Library Checks ) Option
6 Report physical only cells (filler cells with and without metal, -physical_only_cell
diode cells with antenna props, and corner cells)
7 TF consistency check enhancement between main and -tech_consistency

reference libraries
8 technology data quality for a single library (from -tech

cmCheckLibrary)
9 DRC checks for library cells (FRAM view) (from -drc

cmCheckLibrary)
10 Routeability: physical pin access (pin on tracks) -routeability

check_library
•check_library -mw_library_name
{phys_library_name_list} -logic_library_name
{logical_library_name_list} –cell_list
{cell_list}
• Where
-mw_library_name {phys_library_names}
• Specifies Milkyway Reference library names to be checked. If not specified,
the reference libraries used in the current design will be checked
-logic_library_name {logical_library_names}
• Specifies one or more logical library names (filenames) to be checked. If
not specified link libraries used in the current design will be checked
-cell_list {cell_list}
• Specifies a list of cell names that should be checked. If not specified all the
cells in the libraries will be checked.

set_check_library_options
• You should set_check_library_options before running

check_library command if you want to check specific
options
• If you don’t set any options using
set_check_library_options the default behavior is to
check for missing cells and pins and mismatched pins
• In addition to the options mentioned in the tables there are 4
other options:
• set_check_library_options
[-physical]
[-logic_vs_physical]
[-reset]
[-all]

Thank You

Appendix
• Timing Budgeting Flow

• Block Box Flow
• Auto Orientation of Relative Placement Blocks
• Relative Placement – Keep out GUI support
• Relative Placement – size_only flows for
clock_opt & place_opt
• Scan Wire Length Reduction
• Binary Scan DEF flow (Beta)
• AHFS User Interface Update

Timing-Driven Black Box Flow:
Identifying Black Box
“import_fp_black_boxes” generates separate cel view for black box modules
• Black box cel view is used for shaping, pin assigment, floorplan pushdown etc
get_cells with black box filters
• First level filter
"is_logical_black_box==true”
Filter out black box before “import_fp_black_boxes”
“is_pyhsical_black_box==true”
Filter out black box after “import_fp_black_boxes”
• Second level filter
“black_box_type==Empty“
“black_box_type==Missing”
“black_box_type==Tie-Off”
“black_box_type==Feedthru”
“black_box_type==DF”
Example:
• [get_cells -hier -filter "is_logical_black_box==true &&
black_box_type==Empty"]

Relative Placement Keep Out GUI
Support
• Overview
Request from customers to have the relative placement (RP) keepout
displayed in GUI layout window
• Usage/GUI
Added under “RP Keepout” in the layout “View Setting” toolbar
Displayed in layout window
Displayed in relative placement hierarchy view window
• User Benefit
Enable users to check the quality of keep out creation and placement
Enable users to manipulate the RP keepouts during RP placement and
optimization via GUI

Relative Placement Keep Out GUI Support Use these arrows
to browse the
three RP
keepouts
• Layout window: Three keepouts placed inside a RP group

Relative Placement Keep Out GUI Support
• Relative placement hierarchy view window: Two keepouts placed in
the RP group Oprnd_B_reg
Keepout placed at
column0 row3 Keepout placed next to
RP cell at column0 row1

Auto-Orientation of RP Blocks
• Overview
To enable the coarse placer to have more control to orient the relative
placement groups according to data flow
Before 2007.12, RP columns are always placed from left to right (i.e. RP
group orientation = N)
• This may result in longer wire length if data flow is from right to left
In 2007.12, RP columns can be placed starting from the last column to the
first (i.e. RP group orientation = FN)
• Result in shorter wire length if data flow is from right to left
By default, orientation is automatically selected to minimize wire length

Auto-Orientation of Relative Placement Blocks
RP group orientations versus data flow
set_rp_group_options[all_rp_g set_rp_group_options [all_rp_groups]

roups] –orient N –orient FN

Auto-Orientation of Relative Placement Blocks
• User Benefit
QoR changes with data flow
• Left to right: no change
• Right to left: 5% better
Runtime impact is within 1%

Size-Only Flows For clock_opt, route_opt
• Overview
Current implementation in the RP flow to preserve the RP structures
• Fixes the RP cells in clock_opt and route_opt
• Restricts optimizer from further optimizing the design
This feature enables sizing after place_opt in addition to the
fixed_placement option
• Changes to set_rp_group_options and
create_rp_group commands
• Added size_only for -cts_option
• Added in_place_size_only for -route_opt_option
• User Benefit
QoR improvement expected within 5% with a 1% runtime/memory
hit

• Sample script for size_only in clock_opt
source setup.tcl
# create RP groups and constraints for placement &
synthesis
source rp.tcl
# avoid RP cells being removed during place_opt by
set_size_only
set_size_only [rp_group_references -leaf]
place_opt
# check if there is any RP violation
check_rp_groups -all
# allow size_only in clock_opt
set_rp_group_options [all_rp_groups] -cts_option size_only
clock_opt
check_rp_group –all
# check RP placement result in GUI
GUI_start
• Sample script for in_place_size_only in route_opt

# set up design
...
# create RP groups
source rp.tcl
# avoid RP cells being removed during place_opt
set_size_only [rp_group_references -leaf]
place_opt
set_rp_group_options [all_rp_groups] \
# allow size_only in clock_opt and in_place_size_only for route_opt -
cts_option size_only \
-route_opt_option in_place_size_only
clock_opt
check_rp_group -all
route_opt
check_rp_group -all

• Known Limitation
size_only for -cts_option of set_rp_group_options and
create_rp_group commands applies only to clock_opt core
command but not to atomic commands
• optimize_clock_tree
• compile_clock_tree

Scan Wire Length Reduction
• Overview
Some design types cause the current scan chain repartitioning
algorithm to have scan wire length increase.
No reordering done if repartitioning + reordering has wire length
increase.
In 2007.12, optimize_dft (in place_opt flow) will now attempt
reordering alone if repartitioning + reordering does not produce scan
wire length reduction.
• User Interface
No user interface or flow change. Feature enabled by default
• User Benefit
Automatically obtains scan wire length reduction on designs which
previously did not have any reduction.
Customers had to manually remove PARTITION labels to
accomplish this previously. This is no longer required

IC Compiler-RM Roadmap Update
Flat Design Planning

Floorplan Exploration
Hierarchical Design Planning
Multi-voltage + MTCMOS
Multivoltage + MTCMOS
Placement and
Placement based optimization
TTR + QOR RM
UPF Based
CTS and post CTS
MCMM
optimization
Routing and post route
optimization including SI
Chipfinishing
Cell/metal filler, antenna, CAA
Signoff driven closure with
Star-RCXT/PrimeTime SI
2007.12 2007.12 –SP1 2007.12 –SP2

Thank You


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IC Compiler 2007.

New commands/options added in 2007.12 highlighted in Blue

© 2007 Synopsys, Inc. (2)

route_opt • Layer based GR congestion map –

• Min delta delay correlation

© 2007 Synopsys, Inc. (3)

© 2007 Synopsys, Inc. (4)

© 2007 Synopsys, Inc. (5)

© 2007 Synopsys, Inc. (7)

© 2007 Synopsys, Inc. (8)

© 2007 Synopsys, Inc. (9)

© 2007 Synopsys, Inc. (10)

 Note: Correlation can be further improved with clock spacing and

© 2007 Synopsys, Inc. (11)

set cts_integrated_global_router true Enable ICGR before CTO (default: false)

© 2007 Synopsys, Inc. (12)

© 2007 Synopsys, Inc. (13)

© 2007 Synopsys, Inc. (14)

© 2007 Synopsys, Inc. (15)

© 2007 Synopsys, Inc. (16)

© 2007 Synopsys, Inc. (17)

© 2007 Synopsys, Inc. (18)

© 2007 Synopsys, Inc. (19)

© 2007 Synopsys, Inc. (20)

© 2007 Synopsys, Inc. (21)

© 2007 Synopsys, Inc. (22)

© 2007 Synopsys, Inc. (23)

© 2007 Synopsys, Inc. (24)

© 2007 Synopsys, Inc. (25)

© 2007 Synopsys, Inc. (26)

• User Interface / GUI

© 2007 Synopsys, Inc. (27)

• User Interface / GUI

© 2007 Synopsys, Inc. (28)

© 2007 Synopsys, Inc. (29)

© 2007 Synopsys, Inc. (30)

© 2007 Synopsys, Inc. (31)

© 2007 Synopsys, Inc. (33)

Noise slack calculation:

Constraint type: user margin

© 2007 Synopsys, Inc. (34)

New commands/options added in 2007.12 highlighted in

© 2007 Synopsys, Inc. (35)

© 2007 Synopsys, Inc. (36)

© 2007 Synopsys, Inc. (37)

© 2007 Synopsys, Inc. (38)

© 2007 Synopsys, Inc. (39)

• New report_scenario command

• Enhancements to existing commands

© 2007 Synopsys, Inc. (40)

All scenarios (Total=4): s1 s2 s3 s4

© 2007 Synopsys, Inc. (41)

© 2007 Synopsys, Inc. (42)

report_path_group report_path_group -scenario

Path Group clk: (Scenario: s2) Critical

Path Group clk: (Scenario: s2)

© 2007 Synopsys, Inc. (43)

© 2007 Synopsys, Inc. (44)

Parasitic source : LPE

Operating Conditions: WORST Library: xx_worst

Note: Correlation can be further improved with clock spacing and

GUI: Clock Æ Set Clock Plan Options

To explore MTCMOS cell placement and IR drop, based on the