National University

of Computer & Emerging Sciences

Static Timing Analysis

STA for nanometer design: A practical Approach by

J.Bhaskar and R.Chadha
Need for Timing Analysis
 Metal interconnect traces
 Typically used to make the connections between
various portions of the circuitry to realize the
d i
design
 Deep Submicron : Delays, Noise and Crosstalk
limit the operating speed of a design
 Verification should consider these effects
 Deep
D submicron
b i normally
ll starts
t t bbelow
l 250 nm
feature size and nanometer designs from 100 nm
Timing Analysis
 Timing analysis simply refers to the analysis of
the design for timing issues. Types:
 Timing Simulation
 Static
St ti ti
timing
i analysis
l i (STA)
 Static Timing Analysis :
 Analysis of the design for timing issues
 STA does not consider the input pattern applied at
inputs
p
 Timing Simulation
 Stimulus applied on input signals
Static Timing Analysis – Purpose
 Validate if design can operate at rated speed/frequency
without Timing violations
 Given
 The
Th ddesign
i
 Input clock definitions
 Definitions of external environment
 Exhaustively performs timing checks through all the design
 In contrast , simulation depends on quality of testbench and
coverage
 Verification based upon logic simulation cannot handle the
effects
ff t off crosstalk,
t lk noise
i andd on-chip
hi variations.
i ti
 Analogy with PCB design and city modelling
 Examples of timing checks
 Setup check
 Data must arrive at a flip-flop a certain
time before clock edge
 Hold
H ld check
h k
 Data is held for at least a minimum
time so that there is no unexpected
pass-through of data through a flip-flop
 A flip
flip-flop
flop captures the intended data
correctly
 Timing Checks Cont’d
 In Static Timing Analysis
 Required timing checks performed for all possible paths and
scenarios
 Design under analysis (DUA) specified using Verilog HDL or
VHDL
 The external environment, includingg the clock definitions,
are specified typically using SDC or an equivalent format
 Synopsys Design Constraints: It is a defacto standard but a
proprietary format of Synopsys,
Synopsys Inc.
Inc
 The timing reports are in ASCII form, typically with
multiple
p columns, with each column showingg one attribute
of the path delay
STA significance
 Timingg simulation of designs
g containingg 10-100
million gates is a time consuming process
 Testbench should cover all ppossibilities and pparts
of the design
 Static timing analysis on the other hand provides a
faster method
Cross Talk and Noise
 Noise:
 Limiting
L factor
f for
f
 Functionality
 Performance
 Occurs due to
 Crosstalk with other signals
 Noise
N i on primary
i iinputs
t or power supply
l
 Can affect operating frequency of the design
 Design Robustness Check: it should withstand the
noise without affecting the rated performance of the
design
 Cannot
C bbe performed
f d bby Logic
L i simulation
i l i
When is STA performed
during IC Design Flow?
 ASIC design
g flow ((Front End))
 Design entry.
 Enter the design HDL or schematic entry
 Simulation
 Synthesis
y
 Transforming HDL design into a gate-level netlist, given all
the specified constraints and optimization settings
 Logic synthesis:
synthesis
 Process of translating and mapping RTL code written into
technology specific gate level representation
 Post Synthesis Simulation
 ASIC design
g flow ((Backend))
 System partitioning: Divide a large system into ASIC-sized
ppieces
eces
 Prelayout simulation: Check to see if the design functions
correctly
 Floorplanning: Arrange the blocks of the netlist on the chip
 Placement: Decide the locations of cells in a block
 Routing:
R ti M Make
k ththe connections
ti bbetween
t cells
ll andd bl
blocks
k
 Extraction: Determine the resistance and capacitance of the
interconnect
 Postlayout simulation: To check that design works with the
added loads of the interconnect
 Physical Verification
IC Design Processes
FPGA Prototyping Testing
•RTL Code Preparation
•Verilog Code Compilation with ASIC
libraries. Integration of libraries & 3rd
Front End Design Party IPs
•Functional Simulations
•Synthesis
•Translation of Code to Gate/Cell
B kE
Back End
dDDesign
i
level Description
•DFT (Design for Testability)
•Netlist Verification
Chip Tapeout & Packaging •Formal Verification
•Post-Synthesis Simulations

ASIC Power Up Testing on

Board
IC Design Processes
•Floorplanning
FPGA Prototyping Testing g
•Arrangement of Large
g Blocks e.g.
g
PLL, memory, logic Area
Optimization
Front End Design •Place & Route
•Placement of cells in each block
•Clock Tree synthesis to ensure
propagation of ideal clock through out
B kE
Back End
dDDesign
i chip
h
•Routing of interconnect between
cells in blocks
Chip Tapeout & Packaging
•Minimization of interconnect path
lengths
•RC Extraction
ASIC Power Up Testing on Determination of RC Extraction and
•Determination
Board post layout Simulation
•Layout vs Schematic Comparison, DRC
IC Design Processes
FPGA Prototyping Testing

Front End Design

•Chip Tapeout
•Manufacturingg of wafer and die in
B kE
Back End
dDDesign
i
fabrication plant
•Packaging
•Manufacturing of substrate for
Chip Tapeout & Packaging connection of Die with PCB

ASIC Power Up Testing on

Board
IC Design Processes
FPGA Prototyping Testing

Front End Design

B kE
Back End
dDDesign
i

Chip Tapeout & Packaging •Testing on PCB for

f manufacturing
f fault
f l
analysis using ATE (Automatic Testing
Equipment) in test mode
ASIC Power Up Testing on •Testing on PCB in functional mode
Board
 Front End Backend

Design
Specifications
p
w (Synopsyys)

RTL
T
Floor Planning
Description
p
VCS
RTL
Test Vectors Functional
No
Placement
esign – Standard Flow

V ifi ti
Verification Design
Yes Implementation
Clock Tree Using IC Compiler
Constraints RTL to Gate Synthesis (CTS)
Level
Std. Cells Lib
Logic Routing
Optimization

Synthesis
Power Estimation
Timing/Area (IR Power
Using Optimization
p
RC Extraction
Drop,
Drop
p, Averaged,
Averaged
g , and Peak Power))
Digital IC De

D i
Design
Compiler PrimeTime PX,
VCS, Verdi Layout
Tetramax Scan Path Insertion & PrimeRail
Test Pattern Generation No Function &
Timing Test
Formality VCS, Verdi Verification Vectors
Netlist , LVS
Validation N
No
Yes
Test Vectors (DFT+BSD
+BIST) Chip Finishing
Yes
When is STA performed
 STA is normally done after RTL is ready
 STA can be run before timing optimization
 The goal is to identify worst or critical timing paths
 STA is rerun after logic optimization to identify failing
and critical paths
 At start of physical design
 Clock Tree is ideal without delays
 STA is repeated after different steps
When is STA performed –cont’d
cont’d
 Modes of STA at different steps
 At Logical design phase,
 Ideal
d l interconnect assumedd
 No physical information related to the placement
 More interest in viewing the logic contributing to the worst paths
 Use of wire load model
 Estimate the length of the interconnect using a wireload model
 Wireload
Wi l d model d l provides
id estimated
ti t d RC based
b d on ththe fanouts
f t off a cell.
ll
 During global route,
 Implementation
p tools use an estimate of the routingg distance to obtain
RC parasitics for the route
 During this phase, effect of coupling cannot be modeled
 It is done after detailed routing and results from RC extractor tool