APW8819

DDR TOTAL POWER SOLUTION

SYNCHRONOUS BUCK CONTROLLER WITH 1.5A LDO

Features General Description

Buck Controller (VDDQ) The APW8819 integrates a synchronous buck PWM con-
• High Input Voltages Range from 3V to 28V Input troller to generate VDDQ, a sourcing and sinking LDO
Power linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3 memory system. It
• Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable
offers the lowest total solution cost in system where space
Output Voltage from 0.5V to 2V
is at a premium.
- ±1% Accuracy Over-Temperature
• Build in VREF Voltage 1.8V ±1% Accuracy over The APW8819 provides excellent transient response and
Temperature accurate DC voltage output in PFM Mode. In Pulse Fre-
• Integrated MOSFET Drivers quency Mode (PFM), the APW8819 provides very high ef-
ficiency over light to heavy loads with loading-modulated
• Integrated Bootstrap Forward P-CH MOSFET
switching frequencies.
• Excellent Line and Load Transient Responses
• PFM Mode for Increased Light Load Efficiency The APW8819 is equipped with accurate current-limit,
• Selectable 300kHz/400kHz/500kHz Switching output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
Frequebcies
prevents wrong operation during power on.
• Integrated MOSFET Drivers and Bootstrap Diode
• S3 and S5 Pins Control The Device in S0, S3, or The LDO is designed to provide a regulated voltage with
S4/S5 State bi-directional output current for DDR-SDRAM termination.
• Power Good Monitoring The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
• 50% Under-Voltage Protection (UVP)
and thermal shutdown protection.
• 125% Over-Voltage Protection (OVP)
• Adjustable Current-Limit Protection An internal resistor divider is used to provide a half volt-
- Using Sense Low-Side MOSFET RDS(ON) age of VDDQSNS for VTTREF and VTT Voltage. The VTT
• QFN-20 3mmx3mm Package (QFN-20) and output voltage is only requiring 20µF of ceramic output
capacitance for stability and fast transient response. The
QFN-16 3mmx3mm Thin Package (TQFN-16)
S3 and S5 pins provide the sleep state for VTT (S3 state)
• Lead Free Available (RoHS Compliant)
and suspend state (S4/S5 state) for device, when S5 and
+1.5A LDO Section (VTT)
S3 are both pulled low the device provides the soft-off for
• Souring or Sinking Current up to 1.5A
VTT and VTTREF.The APW8819 is available in
• Fast Transient Response for Output Voltage 3mmx3mm 20-pin QFN and 3mmx3mm 16-pin TQFN
• Output Ceramic Capacitors Support at Least packages.
10µF MLCC
• VTT and VTTREF Track at Half the VDDQSNS by
Internal Divider
Applications
• ±20mV Accuracy for VTT and VTTREF
• Independent Over-Current-Limit (OCL) • DDR2, and DDR3 Memory Power Supplies
• Thermal Shutdown Protection • SSTL-2 SSTL-18 and HSTL Termination

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.6 - May, 2013
APW8819

Simplified Application Circuit

5V
VIN VTT
+3V~28V VDDQ/2

Q1 ROC
VDDQ LOUT
DDR VREF
PWM
Q2 LDO
REFIN
RTOP
MODE RGND
RMODE
S3 S5

Ordering and Marking Information

APW8819 Package Code

QA : QFN-20 QB : TQFN-16
Assembly Material Temperature Range
I : -40 to 85 oC
Handling Code Handling Code
Temperature Range TR : Tape & Reel TY : Tray
Assembly Material
Package Code G : Halogen and Lead Free Device
APW
APW8819 QA : 8819 XXXXX - Date Code
XXXXX

APW
APW8819 QB : 8819 XXXXX - Date Code
XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

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Rev. A.6 - May, 2013
APW8819

Pin Configuration

M O D E 19

M O D E 16
P O K 20

O C 18

O C 15
S 3 17
S 5 16

S5 13
S 3 14
VTTSNS 1 15 BOOT POK 1 12 BOOT
VLDOIN 2 14 UGATE
VLDOIN 2 11 UGATE
VTT 3 13 PHASE GND
VTT 3 10 PHASE
VTTGND 4 12 VCC
VTTREF 5 11 LGATE VTTREF 4 9 VCC

5 VR EF

6 REFIN

7 VD D QSN S

8 LGATE
6 VREF
7 GND
8 R E FIN
9 VDDQSNS
10 P G N D

QFN 3x3-20 TQFN 3x3-16

(Top View) (Top View)

= Thermal Pad (connected to GND plane for better heat dissipation)

Absolute Maximum Ratings (Note 1, 2)

Symbol Parameter Rating Unit
VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V
VBOOT BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V
BOOT Supply Voltage (BOOT to GND)
VBOOT-GND <20ns Pulse Width -5 ~ 42 V
>20ns Pulse Width -0.3 ~ 35
UGATE Voltage (UGATE to PHASE)
<20ns Pulse Width -5 ~ VBOOT+0.3 V
>20ns Pulse Width -0.3 ~ VBOOT+0.3
LGATE Voltage (LGATE to GND)
<20ns Pulse Width -5 ~ VCC+0.3 V
>20ns Pulse Width -0.3 ~ VCC+0.3
PHASE Voltage (PHASE to GND)
<20ns Pulse Width -5 ~ 35 V
>20ns Pulse Width -0.3 ~ 28
PGND and VTTGND to GND Voltage -0.3 ~ 0.3 V
All Other Pins (OC, MODE, S3, S5, VDDQSNS, VTTSNS, VLDOIN,
-0.3 ~ 7 V
VREF, POK, VTT, VTTREF and REFIN to GND Voltage)
o
TJ Maximum Junction Temperature 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Soldering Temperature, 10 Seconds 260 C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.

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Rev. A.6 - May, 2013
APW8819

Thermal Characteristics (Note 3)

Symbol Parameter Typical Value Unit
Thermal Resistance - Junction to Ambient
θJA QFN3x3-20 95 °C/W
TQFN3x3-16 95

Note 3: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed
pad of package is soldered directly on the PCB.

Recommended Operating Conditions (Note 4)

S ymbol Parameter Range Unit
VCC VCC Supply Voltage 4.5 ~ 5.5 V
VIN Converter Input Voltage 3 ~ 28 V
VVD DQ Converter Output Voltage 0.5 ~2V/ DDR2 (1.8V)/ DDR 3 (1.5V) V
V VTT LDO Output Voltage 0.25~ 1 V
I OUT Converter Output Current 0 ~ 20 A
I VTT LDO Output Current -1.5 ~ +1.5 A
CVCC VCC Capacitance 1~ µF
C VTT VTT Output Capacitance 10~ µF
C VTTREF VTTREF Output Capacitance 0.22 ~ 2.2 µF
o
TA Ambient Temperature -40 ~ 85 C
TJ o
Junction Temperature -40 ~ 125 C

Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.

APW8819
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SUPPLY CURRENT
IVCC VCC Supply Current TA = 25oC, VS3 = VS5 = 5V, no load - 1.2 1.5 mA
IVCCSTB VCC Standby Current TA = 25oC, VS3 = 0V, VS5 = 5V, no load - 740 850 µA
µA
o
IVCCSDN VCC Shutdown Current TA =25 C, VS3 = VS5 = 0V, no load - 0.1 1
o
ILDOIN LDOIN Supply Current TA = 25 C, VS3 = VS5 = 5V, no load 0.3 0.6 1 mA
ILDOINSTB LDOIN Standby Current TA = 25oC, VS3 = 0V, VS5 = 5V, no load - 0.1 10
µA
ILDOINSDN LDOIN Shutdown Current TA = 25oC, VS3 = VS5 = 0V, no load - 0.1 1
POWER-ON-RESET
VCC POR Threshold VCC Rising 4.15 4.3 4.45 V
VCC POR Hysteresis - 100 - mV
VTT OUTPUT
IVREF=30µA, TA=25oC - 1.8 - V
VVREF VREF Output Voltage
0uA＜IVREF＜300uA, TA= -40oC~85oC 1.782 - 1.8144 V

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Rev. A.6 - May, 2013
APW8819

Electrical Characteristics (Cont.)

Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.

APW8819
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VTT OUTPUT
VLDOIN = VVDDQSNS = 1.8V - 0.9 -
VVTT VTT Output Voltage V
VLDOIN = VVDDQSNS = 1.5V - 0.75 -
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT,
-20 - 20
IVTT = 0A
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT,
-30 - 30
IVTT = 1.5A
VVTT VTT Output Tolerance mV
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT,
-20 - 20
IVTT = 0A
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT,
-30 - 30
IVTT = 1.5A
Sourcing Current (VLDOIN = 1.8V) 2 2.2 3
A
Sinking Current (VLDOIN = 1.8V) -2 -2.2 -3
ILIM Current-Limit
Sourcing Current (VLDOIN = 1.5V) 2 2.2 3
A
Sinking Current (VLDOIN = 1.5V) -2 -2.2 -3
IVTTLK VTT Leakage Current VVTT = 1.25V, VS3 = 0V, VS5 = 5V, TA = 25oC -1.0 - 1.0 µA
µA
o
IVTTSNSLK VTTSNS Leakage Current VVTT = 1.25V, TA = 25 C -1.00 0.01 1.00
VVTT = 0.5V, VS3 = VS5 = 0V, TA = 25oC,
IVTTDIS VTT Discharge Current - 7.8 - mA
VVREF = 0V
VTTREF OUTPUT
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - 0.9 -
VVTTREF VTTREF Output Voltage V
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - 0.75 -
-10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF
-18 - +18
VLDOIN = VVTTREF =1.8V
VTTREF Tolerance mV
-10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF
-15 - +15
VLDOIN = VVDDQSNS = 1.5V
IVTTREF VTTREF Source Current VVTTREF = 0V -10 -25 -40 mA
IVTTREF VTTREF Sink Current VVTTREF = VVDDQSNS 10 25 40 mA
IVTTREFDIS VTTREF Discharge Current TA = 25oC , S3=S5=0V, VVTTREF = 0.5V - 2.6 - mA
VDDQ OUTPUT
VVDDQ VDDQ Output Voltage VREFIN = 1.8V - 1.8 - V
VDDQSNS Regulation Voltage o
TA = 25 C, VREFIN = 1.8V, No Load -15 - 15 mV
Tolerance to REFIN
IVDDQSNS VDDQSNS Input Current VVDDQSNS=1.8V - 12 - µA
IREFIN REFIN Input Current VREFIN=1.8V -0.1 - 0.1 µA
VS3 = VS5 = 0V, VVDDQSNS = 0.5V, MODE Pin Pulled
VDDQ Discharge Current - 12 - mA
Down to GND Through 47kΩ (Non-Tracking)
VS3 = VS5 = 0V, VVDDQSNS = 0.5V, MODE Pin
LDOIN Discharge Current - 1000 - mA
Pulled Down to GND Through 100kΩ (Tracking)

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Rev. A.6 - May, 2013
APW8819

Electrical Characteristics (Cont.)

Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.

APW8819
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PWM CONTROLLERS
VIN=12V, VVDDQSNS=1.8V, RMODE=100 kΩ 270 300 330 kHz
FSW Operating Frequency
VIN=12V, VVDDQSNS=1.8V, RMODE=200 kΩ 360 400 440 kHz
TSS Internal Soft Start Time S5 is High to VOUT Regulation 0.9 1.2 1.5 ms
TOFF(MIN) Minimum off Time 350 450 550 ns
TON(MIN) Minimum on Time 80 110 140 ns
Zero-Crossing Threshold -9.5 0.5 10.5 mV
VDDQ PROTECTIONS
TA = 25oC 9 10 11 µA
OC Pin Source Current Temperature Coefficient,
- 4500 - ppm/ oC
On The Basis of 25 οC
(VOC – VPGND) – (VPGND – VPHASE),
OCP Comparator Offset -10 0 +10 mV
VOC – VPGND = 60mV
VDDQ Current Limit Setting Range VOC-VPGND 0.2 - 3 V
VDDQ OVP Trip Threshold VVDDQ Rising 120 125 130 %
VDDQ OVP Debounce Delay VVDDQ Rising, DV=10mV - 2 - µs
VDDQ UVP Trip Threshold VVDDQ Falling 40 50 60 %
VDDQ UVP Trip Hysteresis - 3 - %
VDDQ UVP Debounce - 16 - µs
VDDQ UVP Enable Delay 2 2.4 2.8 ms
POK
POK in from Lower (POK Goes High) 87 90 93 %
VPOK POK Threshold
POK Out from Normal (POK Goes Low) 120 125 130 %
IPOK POK Leakage Current VPOK=5V - 0.1 1.0 µA
POK Sink Current VPOK=0.5V 2.5 7.5 - mA
POK Enable Delay Time S5 High to POK High 2 2.4 2.8 ms
POK Delay Time Delay for POK In - 63 - µs
GATE DRIVERS
UGATE Pull-Up Resistance BOOT-UGATE=0.5V - 1.5 3 Ω
UGATE Sink Resistance UGATE-PHASE=0.5V - 0.7 1.8 Ω
LGATE Pull-Up Resistance VCC-LGATE=0.5V - 1 2.2 Ω
LGATE Sink Resistance LGATE-PGND=0.5V - 0.5 1.2 Ω
UGATE to LGATE Dead time UGATE falling to LGATE rising, no load - 20 - ns
LGATE to UGATE Dead time LGATE falling to UGATE rising, no load - 20 - ns

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Rev. A.6 - May, 2013
APW8819

Electrical Characteristics (Cont.)

Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.

APW8819
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
BOOTSTRAP SWITCH
VF RON VVCC - VBOOT, IF = 10mA, TA = 25oC - 0.5 0.8 V
VBOOT = 30V, VPHASE = 25V, VVCC = 5V,
IF Reverse Leakage - - 0.5 µA
TA = 25oC
LOGIC THRESHOLD
VIH S3, S5 High Threshold Voltage S3, S5 Rising 1.6 - - V
VIL S3, S5 Low Threshold Voltage S3, S5 Falling - - 0.9 V
IILEAK Logic Input Leakage Current VS3 = VS5 = 5V, TA =25oC -1 - 1 µA
IMODE MODE Source Current 14 15 16 µA
MODE = 0 - - 0.829
MODE = 1 0.879 - 1.202
VTHMODE MODE Threshold Voltage MODE = 2 1.262 - 1.76 V
MODE = 3 1.84 - 1.95
MODE = 4 VCC-1 - -
THERMAL SHUTDOWN
o
TSD Thermal Shutdown Temperature TJ Rising - 160 - C
o
Thermal Shutdown Hysteresis - 25 - C

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Rev. A.6 - May, 2013
APW8819

Typical Operating Characteristics

VREFIN =1.5V, VDDQ=1.5V VREFIN=1.8V, VDDQ=1.8V

1.52 1.83

VDDQ Output Voltage (V)

VDDQ Output Voltage (V)

1.82
1.51
1.81

1.50 1.8

1.79
1.49
1.78

1.48 1.77
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Junction Temperature, TJ (oC) Junction Temperature, TJ (°C)

Supply Current in S 0 State vs. Shutdown Current vs. Junction

Junction Temperature Temperature
2.0
1.0
Shutdown Current, IVCC (uA)

1.6
Supply Current, IVCC (mA)

0.8

1.2
0.6

0.8
0.4

0.4
0.2
S3=S5=5V
0
0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Junction Temperature, TJ (°C) Junction Temperature, TJ (°C)

Supply Current in S3 State vs.

Frequency vs. Junction Temperature
Junction Temperature
1.0 330

320
0.8
Switching Frequency,FSW
Supply Current, IVCC (mA)

310
0.6
(KHz)

300
0.4
290

0.2
280
S3=0V, S5=5V Frequency Setting : 300kHz
0 270
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Junction Temperature, TJ (°C) Junction Temperature, TJ (°C)

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Rev. A.6 - May, 2013
APW8819

Typical Operating Characteristics

MODE Source Current vs. Junction OC Pin Sink Current vs. Junction
Temperature Temperature
20 18
16
MODE Source Current (uA)

18 14

OC Sink Current (uA)

12
16
10
8
14
6

12 4
2
10 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Junction Temperature, TJ (°C) Junction Temperature, TJ (°C)

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Rev. A.6 - May, 2013
APW8819

Operating Waveforms

S5 Enable , No Load Non-Zero VDDQ S5 Enable

CH1: V S5 (5V/div) CH1: VS5 (5V/div)

CH2: V VDDQ (1V/div) CH2: VVDDQ (1V/div)
CH3: V VTT (500mV/div) CH3: VUGATE (20V/div)
CH4: V POK (5V/div) CH4: VPOK (5V/div)
Time: 500µs/div Time: 500µs/div

S5 Shutdown - Tracking Discharge S5 Shutdown - Non-Tracking Discharge

CH1: VS5 (5V/div) CH1: VS5 (5V/div)

CH2: VVDDQ (1V/div) CH2: VVDDQ (1V/div)
CH3: VVTT (500mV/div) CH3: VVTT (500mV/div)
CH4: VVTTREF (500mV/div) CH4: VVTTREF (500mV/div)
Time: 200µs/div Time: 5ms/div

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Rev. A.6 - May, 2013
APW8819

Operating Waveforms

S3 Enable-Shutdown Load Transient , I VDDQ = 0A->12A->0A

CH1: VS3 (5V/div) CH1: V VDDQ (100mV/div)

CH2: VVDDQ (1V/div) CH2: V UGATE (20V/div)
CH3: VVTTREF (500mV/div) CH3: V LGATE (5V/div)
CH4: VVTT (500mV/div) CH4: IL (10A/div)
Time: 10ms/div Time: 20µs/div

Load Transient , IVDDQ = 5A->17A->5A Current Limit then Occur UVP

CH1: V VDDQ (100mV/div) CH1: V VDDQ (1V/div)

CH2: V UGATE (20V/div) CH2: V VTT (500mV/div)
CH3: V LGATE (5V/div) CH3: V PHASE (20V/div)
CH4: IL (10A/div) CH4: IL (10A/div)
Time: 20µs/div Time: 100µs/div

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Rev. A.6 - May, 2013
APW8819

Operating Waveforms

Short Circuit Test : VDDQ Short to GND

CH1: VVDDQ (1V/div)

CH2: VVTT (500mV/div)
CH3: VPHASE (20V/div)
CH4: IL (10A/div)
Time: 20µs/div

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Rev. A.6 - May, 2013
APW8819

Pin Description
NO.
NAME FUNCTION
QFN-20 TQFN-16
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output
1 - VTTSNS
capacitor.
2 2 VLDOIN Supply voltage input for the VTT LDO.
3 3 VTT Power output for the VTT LDO.
4 - VTTGND Power ground output for the VTT LDO.
5 4 VTTREF VTTREF buffered reference output.
1.8V Reference Output. A recommended capacitor with a value of 0.1uF should be attached
6 5 VREF
to the VREF terminal.
Thermal Signal ground for the PWM controller and VTT LDO. Connect to minus terminal of the VTT
7 GND
Pad LDO output capacitor.
Reference input for VDDQ. Programmed by the resistor-divider connected between VREF
8 6 REFIN
and GND.
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge
9 7 VDDQSNS current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for
VDDQ output if VDDQSET pin is connected to VCC or GND.
Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the
10 - PGND low-side MOSFET. Also it is current sense comparator positive input terminal and the
ground of power good circuit.
Output of the low-side MOSFET driver for PWM. Connect this pin to Gate of the low-side
11 8 LGATE
MOSFET. Swings from PGND to VCC.
12 9 VCC Filtered 5V power supply input for internal control circuitry.
Junction point of the high-side MOSFET Source, output filter inductor and the low-side
13 10 PHASE MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as
the lower supply rail for the UGATE high-side gate driver.
Output of the high-side MOSFET driver for PWM. Connect this pin to Gate of the high-side
14 11 UGATE
MOSFET.
Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an
15 12 BOOT external capacitor and diode to create a boosted voltage suitable to drive a logic-level
N-channel MOSFET.
16 13 S5 S5 signal input.
17 14 S3 S3 signal input.
Over-current trip voltage setting input for RDS(ON) current sense scheme. Connect resistor to
18 15 OC
GND to set over-current threshold at VOC/8.
19 16 MODE Discharge mode and switching frequency setting pin.
Power-okay output pin. POK is an open drain output used to Indicate the status of the output
20 1 POK
voltage. When VDDQ output voltage is within the target range, it is in high state.

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Rev. A.6 - May, 2013
APW8819

Block Diagram

0.5 x VDDQ
VDDQSNS
VTTREF

VLDOIN

Thermal
Shutdown

S3
S3,S5 Control Logic Current Limit
VTT
S5

0.5 x VDDQ +5/10%

VTTSNS

VTTGND
0.5 x VDDQ -5/10%

15uA

Discharge
Mode MODE
Selection

Soft Start POR VCC

VREF Reference 1.8V

OC

10uA
REFIN
7R
Current Limit

125% x REFIN 1R
OV
Error
Comparator
BOOT

UV UGATE

50% x REFIN
PHASE
PWM
PHASE
ZC TON Generator Signal
Controller
VCC
REFIN x 125%
POK
LGATE

Delay PGND

GND
REFIN x 90%

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Rev. A.6 - May, 2013
APW8819

Typical Application Circuit

RPOK ROC
RMODE 100 K
100K RVCC
47K
5V
S5 2.2
S3
VIN
VLDOIN
7V~25V

S3
MODE

S5
OC
POK

CVLDOIN CIN
10uF CBOOT
10uF x 2
(MLCC) 0.1uF
(MLCC)
VTTSNS BOOT

VLDOIN UGATE Q1
APM4354 LOUT
1µH
VTT VTT
APW 8819 PHASE VDDQ
CVTT
QFN-20 1.5V/20A
10uF
(MLCC) VTTGND VCC COUT

Q2 330uF(6mΩ)x 2
VTTREF LGATE
APM4354
VDDQSNS

CVCC
REFIN

PGND
VREF

GND

1uF

VTTREF
VDDQ/2
RTOP
10K, 1%
CVTTREF C VREF
0.1 uF 0.1uF
RGND
CREFIN
49K, 1%
0.01uF

DDR3, 400kHz Application Circuit

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Rev. A.6 - May, 2013
APW8819

Function Description
In PWM operation, the high-side switch on-time is deter-
The APW8819 integrates a synchronous buck PWM con- mined by a switching frequency control circuit in the on-
troller to generate VDDQ, a sourcing and sinking LDO time generator block. The switching frequency control
linear regulator to generate VTT. It provides a complete circuit senses the switching frequency of the high-side
power supply for DDR2 and DDR3 memory system in switch and keeps regulating it at a constant frequency in
20-pin QFN and 16-pin TQFN packages. User defined PWM mode. The design improves the frequency varia-
output voltage is also possible and can be adjustable tion and be more outstanding than a conventional con-
from 0.5V to 2V. Input voltage range of the PWM converter stant on-time controller which has large switching fre-
is 3V to 28V. The converter runs an adaptive on-time PWM quency variation over input voltage, output current and
operation at high-load condition and automatically re- temperature. Both in PFM and PWM, the on-time generator,
duces frequency to keep excellent efficiency down to sev- which senses input voltage on PHASE pin, provides very
eral mA. fast on-time response to input line transients.
The VTT LDO can source and sink up to 1.5A peak cur- Another one-shot sets a minimum off-time (typical:
rent with only 10µF ceramic output capacitor. VTTREF 450ns). The on-time one-shot is triggered if the error com-
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks parator is high, the low-side switch current is below the
VTTREF within 20 mV at no load condition while 40 mV at current-limit threshold, and the minimum off-time one-
full load. The LDO input can be separated from VDDQ shot has timed out.
and optionally connected to a lower voltage by using
Power-On-Reset
VLDOIN pin. This helps reducing power dissipation in
sourcing phase. The APW8819 is fully compatible to A Power-On-Reset (POR) function is designed to prevent
JEDEC DDR2/DDR3 specifications at S3/S5 sleep state wrong logic controls when the VCC voltage is low. The
(see Table 1). When both VTT and VDDQ are disabled, POR function continually monitors the bias supply volt-
the part has two options of output discharge function. age on the VCC pin if at least one of the enable pins is set
The tracking discharge mode discharges VDDQ and VTT high. When the rising VCC voltage reaches the rising
outputs through the internal LDO transistors and then POR voltage threshold (4.3V typical), the POR signal goes
VTT output tracks half of VDDQ voltage during discharge. high and the chip initiates soft-start operations. There is
The non-tracking discharge mode discharges outputs almost no hysteresis to POR voltage threshold (about
using internal discharge MOSFETs that are connected to 100mV typical). When VCC voltage drop lower than 4.2V
VDDQSNS and VTT. The current capability of these dis- (typical), the POR disables the chip.
charge MOSFETs are limited and discharge occurs more
Soft-Start
slowly than the tracking discharge. Selecting non-dis-
charge mode can disable these discharge functions. The APW8819 integrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
regulation set point at a predictable slew rate. The slew
Constant-On-Time PWM Controller with Input Feed-For-
rate of output voltage is internally controlled to limit the
ward inrush current through the output capacitors during soft-
The constant on-time control architecture is a pseudo- start process. The figure 1 shows VDDQ soft-start
fixed frequency with input voltage feed-forward. This ar- sequence. When the S5 pin is pulled above the rising S5
chitecture relies on the output filter capacitor’s effective threshold voltage, the switch regulator wait for 400µs and
series resistance (ESR) to act as a current-sense resistor, Mode status is read in this period. And then, the device
so the output ripple voltage provides the PWM ramp signal. initiates a soft-start process to ramp up the output voltage.
In PFM operation, the high-side switch on-time controlled The total soft-start interval is 1.2ms (typical) from S5 goes
by the on-time generator is determined solely by a one- high to VDDQ ramps up to regulation and independent of
shot whose pulse width is inversely proportional to input the UGATE switching frequency.
voltage and directly proportional to output voltage.

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Rev. A.6 - May, 2013
APW8819

Function Description (Cont.)

Soft-Start (Cont.) When PWM converter’s output voltage is greater than 90%
of its target value, the internal open-drain device will be
pulled low. After 63µs debounce time, the POK goes high.
When the output voltage VDDQ outruns 125% of the tar-
2.4ms
get voltage, POK signal will be pulled low immediately.
VCC

1.2ms
VVDDQ Under Voltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When load current is big-
S5
ger than current limit threshold value, the output voltage
will fall out of the required regulation range. The under-
voltage continually monitors the setting output voltage
after 2.4ms of PWM operations to ensure startup. If a
load step is strong enough to pull the output voltage lower
VPOK than the under voltage threshold (50% of normal output
Figure 1. Soft-Start Sequence voltage), the internal UVP delay counter begins counting.
After 16µs debounce time, the device turns off both high-
During soft-start stage before the POK pin is ready, the side and low-side MOSEFET with latched and starts a
under voltage protection is prohibited. The over voltage soft-stop process to shut down the output gradually. Tog-
and current limit protection functions are enabled. If the gling VCC power-on-reset signal can only reset it and
output capacitor has residue voltage before startup, both bring the chip back to operation.
low-side and high-side MOSFETs are in off-state until the
internal digital soft start voltage equal the VVDDQ voltage.
This will ensure the output voltage starts from its existing Over-Voltage Protection (OVP)
voltage level. The feedback voltage should increase over 125% of the
The VTT LDO part monitors the output current, both sourc- reference voltage due to the high-side MOSFET failure or
ing and sinking current, and limits the maximum output for other reasons, and the over voltage protection com-
current to prevent damages during current overload or parator designed with a 1.5µs noise filter will force the
short circuit (shorted from VTT to GND or VLDOIN) low-side MOSFET gate driver to be high. This action ac-
conditions. tively pulls down the output voltage.
The VTT LDO provides a soft-start function, using the When the OVP occurs, the POK pin will pull down and
constant current to charge the output capacitor that gives latch-off the converter. This OVP scheme only clamps the
a rapid and linear output voltage rise. If the load current is voltage overshoot, and does not invert the output voltage
above the current limit start-up, the VTT cannot start when otherwise activated with a continuously high output
successfully. from low-side MOSFET driver. It’s a common problem for
APW8819 has an independent counter for each output, OVP schemes with a latch. Once an over-voltage fault
but the POK signal indicates only the status of VDDQ and condition is set, toggling VCC power-on-reset signal can
does not indicate VTT power good externally. only reset it.

Power-Good Output (POK)

POK is an open-drain output and the POK comparator

continuously monitors the output voltage. POK is actively
held low in shutdown, and standby.

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Rev. A.6 - May, 2013
APW8819

Function Description (Cont.)

PWM Converter Current-Limit
IPEAK

INDUCTOR CURRENT
The current-limit circuit employs a “valley” current-sens-
ing algorithm (See Figure 2). The APW8819 uses the
ILIMIT
low-side MOSFET’s RDS(ON) of the synchronous rectifier
as a current-sensing element. If the magnitude of the
IVALLEY
current-sense signal at PHASE pin is above the current
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current
limit threshold by an amount equals to the inductor ripple
0 Time
current. Therefore, the exact current-limit characteristic
Figure 2. Current-Limit Algorithm
and maximum load capability are the functions of the
sense resistance, inductor value, and input voltage. VTT Sink/Source Regulator
The PWM controller uses the low-side MOSFET’s on-
The output voltage at VTT pin tracks the reference voltage
resistance RDS(ON) to monitor the current for protection
applied at VTTREF pin. Two internal N-channel MOSFETs
against shortened outputs. The MOSFET’s RDS(ON) is var-
controlled by separate high bandwidth error amplifiers
ied by temperature and gate to source voltage, the user
regulate the output voltage by sourcing current from
should determine the maximum RDS(ON) in manufacture’s
VLDOIN pin or sinking current to GND pin. To prevent two
datasheet.
pass transistors from shoot-through, a small voltage off-
The OC pin can source 10µA through an external resistor
set is created between the positive inputs of the two error
for adjusting current-limit threshold. The voltage at OC
amplifiers. The VTT with fast response feedback loop
pin is equal to 10µA x ROC. The relationship between the
keeps tracking to the VTTREF within ±40mV at all condi-
sampled voltage VOC and the current-limit threshold ILIMIT
tions including fast load transient.
is given by:
S3, S5 Control

In the DDR2/DDR3 memory applications, it is important

1
× 10uA × ROC = ILIMIT X RDS(ON) to keep VDDQ always higher than VTT/VTTREF including
8 both start-up and shutdown.
The S3 and S5 signals control the VDDQ, VTT, VTTREF
states and these pins should be connected to SLP_S3
Where ROC is the resistor of current-limit setting threshold. and SLP_S5 signals respectively. The table1 shows the
RDS(ON) is the low side MOSFETs conducive resistance. truth table of the S3 and S5 pins. When both S3 and S5
ILIMIT is the setting current-limit threshold. ILIMIT can be are above the logic threshold voltage, the VDDQ, VTT and
expressed as IOUT minus half of peak-to-peak inductor VTTREF are turned on at S0 state. When S3 is low and
current. S5 is high, the VDDQ and VTTREF are kept on while the
The PCB layout guidelines should ensure that noise and VTT voltage is disabled and left high impedance in S3
DC errors do not corrupt the current-sense signals at state. When both S3 and S5 are low, the VDDQ, VTT and
PHASE. Place the hottest power MOSEFTs as close to VTTREF are turned off and discharged to the ground ac-
the IC as possible for best thermal coupling. When com- cording to the discharge mode selected by MODE pin
bined with the under-voltage protection circuit, this cur- during S4/S5 state.
rent-limit method is effective in almost every circumstance.

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Rev. A.6 - May, 2013
APW8819

Function Description (Cont.)

S3, S5 Control (Cont.) Thermal Shutdown

Table1: The Truth Table of S3 and S5 Pins. A thermal shutdown circuit limits the junction tempera-
STATE S3 S5 VDDQ VTTREF VTT ture of APW8819. When the junction temperature exceeds
S0 H H 1 1 1 +160oC, PWM converter, VTTLDO and VTTREF are shut
0 off, allowing the device to cool down. The regulator regu-
S3 L H 1 1
(high-Z) lates the output again through initiation of a new soft-
S4/5 L L
0 0 0 start cycle after the junction temperature cools by 25oC,
(discharge) (discharge) (discharge)
resulting in a pulsed output during continuous thermal
overload conditions. The thermal shutdown designed with
VDDQ and VTT Discharge Control a 25oC hysteresis lowers the average junction tempera-
APW8819 discharges VDDQ, VTTREF and VTT outputs ture during continuous thermal overload conditions, ex-
during S3 and S5 are both low. There are two different tending life time of the device.
discharge modes. A 15µA current is sourced from MODE For normal operation, device power dissipation should
pin across RMODE resistor connected between MODE pin be externally limited so that junction temperatures will
to GND. Table 2 shows R MODE values, corresponding not exceed +125oC.
switching frequency and discharge mode configuration.

Table 2. MODE Selection.

MODE RMODE(kΩ) FSW(kHz) DISCHARGE MODE
0 47 400
Non-Tracking
1 68 300
2 100 300
Tracking
3 200 400
4 Open 500 Tracking

When in tracking-discharge mode, APW8819 discharges

outputs through the internal VTT regulator transistors and
VTT output tracks half of VDDQ voltage during this
discharge. Note that VDDQ discharge current flows via
VLDOIN to VTTGND thus VLDOIN must be connected to
VDDQ output in this mode. The internal LDO can handle
up to 1.5A and discharge quickly. After VDDQ is discharged
down to 0.2V, the internal LDO is turned off and the op-
eration mode is changed to the non-tracking discharge
mode.
When in non-tracking-discharge mode, APW8819 dis-
charges outputs using internal MOSFETs that are con-
nected to VDDQSNS and VTT. The current capability of
these MOSFETs is limited to discharge slowly.
Note that VDDQ discharge current flows from VDDQSNS
to PGND in this mode. In case of no discharge mode,
APW8819 does not discharge output charge at all.

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Rev. A.6 - May, 2013
APW8819

Application Information
Output Voltage Selection In some types of inductors, especially core that is made
The Output VDDQSNS Voltage is defined by REFIN of ferrite, the ripple current will increase abruptly when it
voltage. The APW8819 provides a 1.8V voltage reference saturates. This will be result in a larger output ripple
from VREF. In normal application circuit, the VREF output voltage.
voltage drive the REFIN input voltage through a voltage
divider circuit. The VDDQ output range is between 0.75 V Output Capacitor Selection
and 1.8V, programmed by the resister-divider connected Ou tp ut vol ta ge r ip pl e and t he t rans ie nt vol ta g e
between VREF and GND. For stability operation, connect- de viat ion are fac tor s th at h ave to be take n in to
ing a few nano farads of capacitance from REFIN to GND consideration when selecting an output capacitor.
is necessary. Higher capacitor value and lower ESR reduce the
output ripple and the load transient drop. Therefore,
selecting high performance low ESR capacitors is in-
Output Inductor Selection
tended for switching regulator applications. In addition to
The duty cycle of a buck converter is the function of the high frequency noise related MOSFET turn-on and turn-
input voltage and output voltage. Once an output voltage
off, the output voltage ripple includes the capacitance volt-
is fixed, it can be written as: age drop and ESR voltage drop caused by the AC peak-
VOUT to-peak current. These two voltages can be represented
D=
VIN by:

The inductor value determines the inductor ripple current IRIPPLE

∆VCOUT =
and affects the load transient reponse. Higher inductor 8COUTFSW
value reduces the inductor’s ripple current and induces ∆VESR = IRIPPLE × RESR

lower output ripple voltage. The ripple current and ripple

voltage can be approxminated by:
These two components constitute a large portion of the
VIN - VOUT VOUT total output voltage ripple. In some applications, multiple
IRIPPLE = ×
FSW × L VIN capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
Where FSW is the switching frequency of the regulator. another load with high pulsating current, more capaci-
Although increase the inductor value and frequency tors are needed in order to reduce the equivalent ESR
reduce the ripple current and voltage, there is a tradeoff and suppress the voltage ripple to a tolerable level. A
between the inductor’s ripple current and the regulator small decoupling capacitor in parallel for bypassing
load transient response time. the noise is also recommended, and the voltage rating
A smaller inductor will give the regulator a faster load of the output capacitors must also be considered.
transient response at the expense of higher ripple To support a load transient that is faster than the
current. Increasing the switching frequency (FSW ) also switching frequency, more capacitors have to be used
reduces the ripple current and voltage, but it will to reduce the voltage excursion during load step change.
increase the switching loss of the MOSFETs and the Another aspect of the capacitor selection is that the
power dissipation of the converter. The maximum total AC current going through the capacitors has to be
ripple current occurs at the maximum input voltage. A less than the rated RMS current specified on the ca-
good starting point is to choose the ripple current to be pacitors to prevent the capacitor from over-heating.
approximately 30% of the maximum output current.
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
rent without going into saturation.

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Rev. A.6 - May, 2013
APW8819

Application Information (Cont.)

Input Capacitor Selection
The input capacitor is chosen based on the voltage rating losses in the MOSFETs have two components: conduc-
and the RMS current rating. For reliable operation, select tion loss and transition loss. For the high-side and low-
the capacitor voltage rating to be at least 1.3 times higher side MOSFETs, the losses are approximately given by
than the maximum input voltage. The maximum RMS the following equations :
2
current rating requirement is approximately IOUT/2, where Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
IOUT is the load current. During power up, the input capaci- 2
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
tors have to handle large amount of surge current. In low-
duty notebook appliactions, ceramic capacitors are Where
remmended. The capacitors must be connected between I is the load current
OUT
the drain of high-side MOSFET and the source of low- TC is the temperature dependency of RDS(ON)
side MOSFET with very low-impeadance PCB layout. FSW is the switching frequency
tSW is the switching interval
MOSFET Selection D is the duty cycle
The application for a notebook battery with a maximum Note that both MOSFETs have conduction losses while
voltage of 24V, at least a minimum 30V MOSFETs the high-side MOSFET includes an additional transi-
should be used. The design has to trade off the gate tion loss. The switching internal, t SW , is the function
charge with the RDS(ON) of the MOSFET: of the reverse transfer capacitance CRSS. The (1+TC) term
is to factor in the temperature dependency of the RDS(ON)
• For the low-side MOSFET, before it is turned on, the
and can be extracted from the “RDS(ON) vs Temperature”
body diode has been conducted. The low-side MOSFET
curve of the power MOSFET..
driver will not charge the miller capacitor of this
MOSFET. Layout Consideration
• In the turning off process of the low-side MOSFET,
In any high switching frequency converter, a correct layout
the load current will shift to the body diode first. The
is important to ensure proper operation of the regulator.
high dv/dt of the phase node voltage will charge the
With power devices switching at higher frequency, the
miller capacitor through the low-side MOSFET driver
resulting current transient will cause voltage spike across
sinking current path. This results in much less
the interconnecting impedance and parasitic circuit
switching loss of the low-side MOSFETs. The duty
elements. As an example, consider the turn-off transition
cycle is often very small in high battery voltage
of the PWM MOSFET. Before turn-off condition, the
applications, and the low-side MOSFET will con-
MOSFET is carrying the full load current. During turn-off,
duct most of the switching cycle; therefore, the RDS(ON)
current stops flowing in the MOSFET and is freewheeling
of the low-side MOSFET, the less the power loss. The
by the lower MOSFET and parasitic diode. Any parasitic
gate charge for this MOSFET is usually a secondary
inductance of the circuit generates a large voltage spike
consideration. The high-side MOSFET does not have
during the switching interval. In general, using short and
this zero voltage switching condition, and because
wide printed circuit traces should minimize interconnect-
it conducts for less time compared to the low-side
ing impedances and the magnitude of voltage spike. And
MOSFET, the switching loss tends to be dominant.
signal and power grounds are to be kept separating and
Priority should be given to the MOSFETs with less
finally combined to use the ground plane construction or
gate charge, so that both the gate driver loss and
single point grounding. The best tie-point between the
switching loss will be minimized.
signal ground and the power ground is at the negative
The selection of the N-channel power MOSFETs are de-
side of the output capacitor on each channel, where there
termined by the RDS(ON), reversing transfer capacitance
is less noise. Noisy traces beneath the IC are not
(CRSS) and maximum output current requirement. The
recommended. Below is a checklist for your layout:

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Rev. A.6 - May, 2013
APW8819

Application Information (Cont.)

Layout Consideration (Cont.)
• Keep the switching nodes (UGATE, LGATE, BOOT, and • The PGND trace should be a separate trace, and inde
PHASE) away from sensitive small signal nodes pendently go to the source of the low-side MOSFETs
(VREF, REFIN, VTTREF, OC, and MODE) since these for current limit accuracy.
nodes are fast mov ing signals. Therefore, keep traces
to these nodes as short as possible and there should TQFN3X3-16
be no other weak signal traces in parallel with theses 3mm
traces on any layer.

• The signals going through theses traces have both

high dv/dt and high di/dt, with high peak charging and
discharging current. The traces from the gate drivers to 0.5mm *

the MOSFETs (UGATE and LGATE) should be short 0.24mm

and wide.

1.66 mm
• Place the source of the high-side MOSFET and the drain 3mm

of the low-side MOSFET as close as possible. Mini- 0.5mm

mizing the impedance with wide layout plane between

1.66mm
0.508mm 0.162mm
the two pads reduces the voltage bounce of the node.
• Decoupling capacitor, the resistor dividers, boot
capacitors, and current limit stetting resistor should be
close their pins. (For example, place the decoupling * Just Recommend

ceramic capacitor near the drain of the high-side

MOSFET as close as possible. The bulk capacitors are
also placednear the drain). And need to noted, con- QFN3x3-20
necting capacitor with OC pin is forbidden. 3mm
• The input capacitor should be near the drain of the up
per MOSFET; the high quality ceramic decoupling ca-
pacitor can be put close to the VCC and GND pins; the
VTTREF decoupling capacitor should be close to the 0.5mm *

VTTREF pin and GND; A capacitor with a value of 0.1µF 0.2mm

or larger should be close to the VREF terminal; the

REFIN decoupling capacitor should be close to the
1.66
mm

REFIN pin and GND; the VDDQ and VTT output capaci- 3mm
tors should be located right across their output pin as 0.4mm

clase as possible to the part to minimize parasitics. 0.17

1.66 mm mm
The input capacitor GND should be close to the output
0.5mm
capacitor GND and the lower MOSFET GND.
• The drain of the MOSFETs (PHASE node) should be a
large plane for heat sinking. And PHASE pin traces are
also the return path for UGATE. Connect this pin to the * Just Recommend

converter’s upper MOSFET source. Figure3. Recommended Minimum Footprint

Copyright  ANPEC Electronics Corp. 22 www.anpec.com.tw

Rev. A.6 - May, 2013
APW8819

Package Information
QFN3x3-20
A
D

b
E
Pin 1

A1
A3
D2 NX
aaa c

Pin 1 Corner
E2
L K

S QFN3x3-20
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.80 1.00 0.031 0.039
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.15 0.25 0.006 0.010
D 2.90 3.10 0.114 0.122

D2 1.50 1.80 0.059 0.071

E 2.90 3.10 0.114 0.122
E2 1.50 1.80 0.059 0.071
e 0.40 BSC 0.016 BSC
L 0.30 0.50 0.012 0.020
K 0.20 0.008
aaa 0.08 0.003
Note : 1. Followed from JEDEC MO-220 WEEE

Copyright  ANPEC Electronics Corp. 23 www.anpec.com.tw

Rev. A.6 - May, 2013
APW8819

Package Information
TQFN3x3-16
D A

b
Pin 1

D2
A1
A3

Pin 1
Corner
E2
L K

S TQFN3x3-16
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.031

A1 0.00 0.05 0.000 0.002

A3 0.20 REF 0.008 REF

b 0.18 0.30 0.007 0.012

D 2.90 3.10 0.114 0.122

D2 1.50 1.80 0.059 0.071

E 2.90 3.10 0.114 0.122

E2 1.50 1.80 0.059 0.071

e 0.50 BSC 0.020 BSC

L 0.30 0.50 0.012 0.020

K 0.20 0.008
Note : Follow JEDEC MO-220 WEED-4.

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Rev. A.6 - May, 2013
APW8819

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
QFN3X3-20 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 3.30±0.20 3.30±0.20 1.30±0.20
-0.00 -0.40
A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
TQFN3x3-16
P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 3.30±0.20 3.30±0.20 1.30±0.20
-0.00 -0.40

(mm)

Devices Per Unit

Package Type Unit Quantity
QFN3x3-20 Tape & Reel 3000
TQFN3x3-16 Tape & Reel 3000

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Rev. A.6 - May, 2013
APW8819

Taping Direction Information

QFN3x3-20 &TQFN3x3-16

USER DIRECTION OF FEED

Classification Profile

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Rev. A.6 - May, 2013
APW8819

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

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Rev. A.6 - May, 2013
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Rev. A.6 - May, 2013