25C320

32K 5.0V SPI Bus Serial EEPROM

FEATURES PACKAGE TYPES
• SPI modes 0,0 and 1,1 DIP/SOIC
• 3.0 MHz Clock Rate
• Single 5V Supply CS 1 8 VCC
• Low Power CMOS Technology

25C320
SO 2 7 HOLD
- Max Write Current: 5 mA
- Read Current: 1.0 mA at 5.5V, 3MHz WP 3 6 SCK
- Standby Current: 1 µA typical
• 4096 x 8 Organization VSS 4 5 SI
• 32 Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles TSSOP
• Block Write Protection CS 1 14 VCC
- Protect none, 1/4, 1/2, or all of Array SO 2 13 HOLD

25C320
NC 3 12 NC
• Built-in Write Protection NC 4 11 NC
- Power On/Off Data Protection Circuitry NC 5 10 NC
WP 6 9 SCK
- Write Enable Latch VSS 7 8 SI
- Write Protect Pin
• High Reliability
- Endurance: 1M cycles (guaranteed) BLOCK DIAGRAM
- Data Retention: >200 years Status
- ESD protection: >4000V HV Generator
Register
• 8-pin PDIP/SOIC, 14-pin TSSOP
• Temperature ranges supported
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
EEPROM
- Automotive (E): -40°C to +125°C
I/O Control Memory X
Control Array
DESCRIPTION Logic
Logic Dec
The Microchip Technology Inc. 25C320 is a 32K-bit
serial Electrically Erasable PROM (EEPROM). The Page Latches
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals WP
required are a clock input (SCK) plus separate data in SI
(SI) and data out (SO) lines. Access to the device is SO Y Decoder
controlled through a chip select (CS) input, allowing any CS
number of devices to share the same bus. SCK
Sense Amp.
There are two other inputs that provide the end user HOLD
R/W Control
with additional flexibility. Communication to the device
Vcc
can be paused via the hold pin (HOLD). While the Vss
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also write
operations to the Status Register can be disabled via
the write protect pin (WP).

SPI is a trademark of Motorola.

 1996 Microchip Technology Inc. Preliminary DS21159B-page 1

This document was created with FrameMaker 4 0 4

25C320
1.0 ELECTRICAL FIGURE 1-1: AC TEST CIRCUIT
CHARACTERISTICS Vcc

1.1 Maximum Ratings*

2.25 K
VCC ........................................................................ 7.0V
All inputs and outputs w.r.t. VSS ....... -0.6V to VCC+1.0V SO
Storage temperature ............................ -65°C to 150°C
Ambient temperature under bias.......... -65°C to 125°C 1.8 K 100 pF
Soldering temperature of leads
(10 seconds) .................................................... +300°C
ESD protection on all pins..................................... 4 kV
*Notice: Stresses above those listed under ‘Maximum ratings’
may cause permanent damage to the device. This is a stress rat- 1.2 AC Test Conditions
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings AC Waveform:
of this specification is not implied. Exposure to maximum rating VLO = 0.2V
conditions for extended period of time may affect device reliability VHI = Vcc - 0.2V (Note 1)
TABLE 1-1: PIN FUNCTION TABLE VHI = 4.0V (Note 2)

Name Function Timing Measurement Reference Level

CS Chip Select Input Input 0.5 VCC
Output 0.5 VCC
SO Serial Data Output
Note 1: For VCC ≤ 4.0V
SI Serial Data Input
2: For VCC > 4.0V
SCK Serial Clock Input
WP Write Protect Pin
VSS Ground
VCC Supply Voltage
HOLD Hold Input
NC No Connect

TABLE 1-2: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = 4.5V to 5.5V
Commercial (C): Tamb = 0°C to +70˚C
Industrial (I): Tamb =-40˚C to +85˚C
Automotive (E): Tamb = -40°C to +125°C

Parameter Symbol Min Max Units Test Conditions

High level input voltage VIH 2.0 VCC+1 V

Low level input voltage VIL -0.3 0.8 V

Low level output voltage VOL — 0.4 V IOL=2.1 mA
High level output voltage VOH VCC-0.5 — V IOH=-400 µA
Input leakage current ILI -10 10 µA CS=VIH, VIN=GND to VCC
Output leakage current ILO -10 10 µA CS=VIH, VOUT=GND to VCC

Internal Capacitance CINT — 7 pF Tamb=25°C, FCLK=1.0 MHz,

(all inputs and outputs) VCC=5.5V (Note)
Operating Current ICC write —— 5 mA VCC=5.5V; SO=Open
ICC read — 1 mA VCC=5.5V; SO=Open, FCLK=3.0 MHz
Standby Current ICCS — 5 µA CS=VCC=5.5V; VIN=Gnd or VCC
Note: This parameter is periodically sampled and not 100% tested.

DS21159B-page 2 Preliminary  1996 Microchip Technology Inc.

 25C320
FIGURE 1-2: SERIAL INPUT TIMING
tCSD

CS
tCSS tR tCLD
tF tCSH

SCK
tSU tHD

SI msb in lsb in

high impedance
SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

tCSH
tHI tLO
SCK
tV tDIS
tHO

SO msb out lsb out

don’t care
SI

FIGURE 1-4: HOLD TIMING

CS
tHS tHH tHS tHH

SCK
tHZ tHV
high impedance
SO n+2 n+1 n n n-1

tSU
don’t care
SI n+2 n+1 n n n-1

HOLD

 1996 Microchip Technology Inc. Preliminary DS21159B-page 3

25C320
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = 4.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = +40°C to +85C
Automotive (E): Tamb = -40°C to +125°C
Symbol Parameter Min Max Units Test Conditions
fSCK Clock Frequency — 3 MHz
tCSS CS Setup Time 100 — ns
tCSH CS Hold Time 100 — ns
tCSD CS Disable Time 250 — ns
tSU Data Setup Time 30 — ns
tHD Data Hold Time 50 — ns
tR CLK Rise Time — 2 µs (Note 1)
tF CLK Fall Time — 2 µs (Note 1)
tHI Clock High Time 150 — ns
tLO Clock Low Time 150 — ns
tCLD Clock Delay Time 50 — ns
tV Output Valid from — 150 ns
Clock Low
tHO Output Hold Time 0 — ns
tDIS Output Disable Time — 200 ns (Note 1)
tHS HOLD Setup Time 100 — ns
tHH HOLD Hold Time 100 — ns
tHZ HOLD Low to Output High-Z 100 — ns (Note 1)
tHV HOLD High to Output Valid 100 — ns (Note 1)
tWC Internal Write Cycle Time — 5 ms (Note 2)
— Endurance 1M — E/W Cycles 25°C, Vcc = 5.0V, Block Mode
(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write
cycle is complete.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

DS21159B-page 4 Preliminary  1996 Microchip Technology Inc.

 25C320
2.0 PRINCIPLES OF OPERATION The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
The 25C320 is a 4096-byte EEPROM designed to allows writes to the array and status register, when set
interface directly with the serial peripheral interface (SPI) to a ‘0’ the latch prohibits writes to the array and status
port of many of today’s popular microcontroller families, register. The state of this bit can always be updated via
including Microchip’s midrange PIC16CXX microcontrol- the WREN or WRDI commands regardless of the state
lers. It may also interface with microcontrollers that do of write protection on the status register. This bit is read
not have a built-in SPI port by using discrete I/O lines only.
programmed properly with software.
The Block Protection (BP0 and BP1) bits indicate
The 25C320 contains an 8-bit instruction register. The which blocks are currently write protected. These bits
part is accessed via the SI pin, with data being clocked are set by the user issuing the WRSR instruction.
in on the rising edge of SCK. The CS pin must be low These bits are non-volatile.
and the HOLD pin must be high for the entire operation.
If the WPEN bit in the status register is set, the WP pin The Write Protect Enable (WPEN) bit is a nonvolatile
must be held high to allow writing to the nonvolatile bits bit that is available as an enable bit for the WP pin. The
in the status register. Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the
Table 2-1 contains a list of the possible instruction bytes programmable hardware write protect feature.
and format for device operation. All instructions, Hardware write protection is enabled when the WP pin
addresses and data are transferred MSB first, LSB last. is low and the WPEN bit is high. Hardware write
Data is sampled on the first rising edge of SCK after CS protection is disabled when either the WP pin is high or
goes low. If the clock line is shared with other peripheral the WPEN bit is low. When the chip is hardware write
devices on the SPI bus, the user can assert the HOLD protected, only writes to nonvolatile bits in the status
input and place the 25C320 in ‘HOLD’ mode. After register are disabled. See Table 2-2 for matrix of
releasing the HOLD pin, operation will resume from the functionality on the WPEN bit and Figure 2-1 for a
point when the HOLD was asserted. flowchart of Table 2-2.
2.1 Write Enable (WREN) and Write See Figure 3-5 for RDSR timing sequence.
Disable (WRDI) TABLE 2-1: INSTRUCTION SET
The 25C320 contains a write enable latch. This latch
Instruction Instruction
must be set before any write operation will be Description
Name Format
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. The following is WREN 0000 0110 Set the write enable latch
a list of conditions under which the write enable latch (enable write operations)
will be reset: WRDI 0000 0100 Reset the write enable
• Power-up latch (disable write opera-
• WRDI instruction successfully executed tions)
• WRSR instruction successfully executed RDSR 0000 0101 Read status register
• WRITE instruction successfully executed WRSR 0000 0001 Write status register (write
protect enable and block
2.2 Read Status Register (RDSR) write protection bits)
The RDSR instruction provides access to the status READ 0000 0011 Read data from memory
register. The status register may be read at any time, array beginning at
even during a write cycle. The status register is format- selected address
ted as follows: WRITE 0000 0010 Write data to Memory
Array beginning at
7 6 5 4 3 2 1 0 Selected Address
WPEN X X X BP1 BP0 WEL WIP
The Write-In-Process (WIP) bit indicates whether the
25C320 is busy with a write operation. When set to a ‘1’
a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.

 1996 Microchip Technology Inc. Preliminary DS21159B-page 5

25C320
TABLE 2-2: WRITE PROTECT FUNCTIONALITY MATRIX
WPEN WP WEL Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART

CS Returns High

Write No No
to Status Write To other
Reg? to array? Commands

Yes Yes

No No
WEL = 1? WEL = 1?

Yes Yes

No Write to the
WP is low? Unprotected Block

Yes

No Do not write to
WPEN = 1? Array

Yes
Write to
Status Register

Do not write to
Status Register

From other
Commands

Continue

DS21159B-page 6 Preliminary  1996 Microchip Technology Inc.

 25C320
2.3 Write Status Register (WRSR) Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
The WRSR instruction allows the user to select one of followed by the 16-bit address, with the four MSBs of
four protection options for the array by writing to the the address being don’t care bits, and then the data to
appropriate bits in the status register. The array is be written. Up to 32 bytes of data can be sent to the
divided up into four segments. The user has the ability 25C320 before a write cycle is necessary. The only
to write protect none, one, two, or all four of the seg- restriction is that all of the bytes must reside in the
ments of the array. The partitioning is controlled as illus- same page. A page address begins with XXXX XXXX
trated in Table 2-3. XXX0 0000 and ends with XXXX XXXX XXX1 1111. If
See Figure 3-6 for WRSR timing sequence. the internal address counter reaches XXXX XXXX
XXX1 1111 and the clock continues, the counter will roll
TABLE 2-3: ARRAY PROTECTION back to the first address of the page and overwrite any
data in the page that may have been written.
Array Addresses
BP1 BP0 For the data to be actually written to the array, the CS
Write Protected
0 0 none must be brought high after the least significant bit (D0)
0 1 upper 1/4 of the nth data byte has been clocked in. If CS is brought
0C00h - 0FFFh high at any other time, the write operation will not be
1 0 upper 1/2 completed. Refer to Figure 3-3 and Figure 3-4 for more
0800h - 0FFFh detailed illustrations on the byte write sequence and the
1 1 all page write sequence respectively.
0000h - 0FFFh
While the write is in progress, the status register may
3.0 DEVICE OPERATION be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits. A read attempt of a memory array
3.1 Clock and Data Timing location will not be possible during a write cycle. When
a write cycle is completed, the write enable latch is
Data input on the SI pin is latched on the rising edge of reset.
SCK. Data is output on the SO pin after the falling edge
of SCK. 3.4 Data Protection

3.2 Read Sequence The following protection has been implemented to

prevent inadvertent writes to the array:
The part is selected by pulling CS low. The 8-bit read
• The write enable latch is reset on power-up.
instruction is transmitted to the 25C320 followed by the
• A write enable instruction must be issued to set
16-bit address, with the four MSBs of the address being
the write enable latch.
don’t care bits. After the correct read instruction and
• After a successful byte write, page write, or status
address are sent, the data stored in the memory at the
register write, the write enable latch is reset.
selected address is shifted out on the SO pin. The data
• CS must be set high after the proper number of
stored in the memory at the next address can be read
clock cycles to start an internal write cycle.
sequentially by continuing to provide clock pulses. The
• Access to the array during an internal write cycle
internal address pointer is automatically incremented to
is ignored and programming is continued.
the next higher address after each byte of data is
shifted out. When the highest address is reached 3.5 Power On State
(0FFFh) the address counter rolls over to address
0000h allowing the read cycle to be continued indefi- The 25C320 powers on in the following state:
nitely. The read operation is terminated by setting CS • The device is in low power standby mode (CS=1).
high (Figure 3-1). • The write enable latch is reset.
• SO is in high impedance state.
3.3 Write Sequence
• A low level on CS is required to enter active state.
Prior to any attempt to write data to the 25C320, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-2). This is done by setting CS low
and then clocking the proper instruction into the
25C320. After all eight bits of the instruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.

 1996 Microchip Technology Inc. Preliminary DS21159B-page 7

25C320
FIGURE 3-1: READ SEQUENCE
CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK

instruction 16 bit address

SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0

data out
high impedance
SO 7 6 5 4 3 2 1 0

FIGURE 3-2: WRITE ENABLE SEQUENCE

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 1 0

high impedance
SO

FIGURE 3-3: WRITE SEQUENCE

CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16 bit address data byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

high impedance
SO

DS21159B-page 8 Preliminary  1996 Microchip Technology Inc.

 25C320
FIGURE 3-4: PAGE WRITE SEQUENCE
CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
data byte 2 data byte 3 data byte n (32 max)
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

FIGURE 3-5: READ STATUS REGISTER SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
instruction
SI 0 0 0 0 0 1 0 1

data from status register

high impedance
SO 7 6 5 4 3 2 1 0

FIGURE 3-6: WRITE STATUS REGISTER SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
instruction data to status register
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0

high impedance
SO

 1996 Microchip Technology Inc. Preliminary DS21159B-page 9

25C320
4.0 PIN DESCRIPTIONS 4.5 Write Protect (WP)

4.1 Chip Select (CS) This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
A low level on this pin selects the device. A high level in the status register. When WP is low and WPEN is
deselects the device and forces it into standby mode. high, writing to the non-volatile bits in the status register
However, a programming cycle which is already in is disabled. All other operations function normally.
progress will be completed, regardless of the CS input When WP is high, all functions, including writes to the
signal. If CS is brought high during a program cycle, the non-volatile bits in the status register operate normally.
device will go into standby mode as soon as the pro- If the WPEN bit is set WP going low during a status reg-
gramming cycle is complete. As soon as the device is ister write sequence will disable writing to the status
deselected, SO goes to the high impedance state, register. If an internal write cycle has already begun,
allowing multiple parts to share the same SPI bus. A WP going low will have no effect on the write.
low to high transition on CS after a valid write sequence The WP pin function is blocked when the WPEN bit in
is what initiates an internal write cycle. After power-up, the status register is low. This allows the user to install
a low level on CS is required prior to any sequence the 25C320 in a system with the WP pin grounded and
being initiated. still be able to write to the status register. The WP pin
functions will be enabled when the WPEN bit is
4.2 Serial Input (SI)
set high.
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data to be written 4.6 Hold (HOLD)
to the memory. Input is latched on the rising edge of the The HOLD pin is used to suspend transmission to the
serial clock. 25C320 while in the middle of a serial sequence without
It is possible for the SI pin and the SO pin to be tied having to re-transmit the entire sequence over at a later
together. With SI and SO tied together, two way time. It should be held high any time this function is not
communication of data can occur using only one being used. Once the device is selected and a serial
microcontroller I/O line. sequence is underway, the HOLD pin may be pulled low
to pause further serial communication without resetting
4.3 Serial Output (SO) the serial sequence. The HOLD pin must be brought
low while SCK is low, otherwise the HOLD function will
The SO pin is used to transfer data out of the 25C320.
not be evoked until the next SCK high to low transition.
During a read cycle, data is shifted out on this pin after
The 25C320 must remain selected during this
the falling edge of the serial clock.
sequence. The SI, SCK, and SO pins are in a high
It is possible for the SI pin and the SO pin to be tied impedance state during the time the part is paused and
together. With SI and SO tied together, two-way transitions on these pins will be ignored. To resume
communication of data can occur using only one serial communication, HOLD must be brought high
microcontroller I/O line. while the SCK pin is low, otherwise serial communica-
tion will not resume.
4.4 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25C320. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.

DS21159B-page 10 Preliminary  1996 Microchip Technology Inc.

 25C320
25C320 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.

25C320 - /P
Package: P = PDIP (300 mil Body), 8-lead
SN = SOIC (150 mil Body), 8-lead
ST = TSSOP (4.4 mm Body), 14-lead

Temperature Blank = 0°C to +70°C

Range: I = -40°C to +85°C
E = -40°C to +125°C

Device: 25C320 32K SPI Bus Serial EEPROM

25C320T 32K SPI Bus Serial EEPROM (Tape and Reel)

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see next page)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

 1996 Microchip Technology Inc. Preliminary DS21159B-page 11

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All rights reserved.  1996, Microchip Technology Incorporated, USA. 11/96

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DS21159B-page 12 Preliminary  1996 Microchip Technology Inc.