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16-BIT ADDRESS COMPARATOR
SDAS012C – JUNE 1982 – REVISED JANUARY 1995

• 16-Bit Address Comparator With Enable DW OR NT PACKAGE

• Package Options Include Plastic

(TOP VIEW)

Small-Outline (DW) Packages and Standard A1 VCC

1 24
Plastic (NT) 300-mil DIPs A2 G
2 23
A3 3 22 Y
description
A4 4 21 P3
This 16-bit address comparator simplifies A5 5 20 P2
addressing of memory boards and/or other A6 6 19 P1
peripheral devices. The four P inputs are normally A7 7 18 P0
hardwired with a preprogrammed address. An A8 8 17 A16
internal decoder determines what input A9 9 16 A15
information applied to the A inputs must be low or A10 10 15 A14
high to cause a low state at the Y output. For A11 11 14 A13
example, a positive-logic bit combination of 0111 GND 12 13 A12
(decimal 7) at the P input determines that inputs
A1 through A7 must be low and that inputs A8
through A16 must be high to cause the output to
go low. Equality of the address applied at the
A inputs to the preprogrammed address is
indicated by the output being low.
This device features an enable (G) input. When G is low, the device is enabled. When G is high, the device is
disabled and the output is high, regardless of the A and P inputs.
The SN74ALS677A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE
INPUTS
OUTPUT
G P3 P2 P1 P0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
L L L L L H H H H H H H H H H H H H H H H L
L L L L H L H H H H H H H H H H H H H H H L
L L L H L L L H H H H H H H H H H H H H H L
L L L H H L L L H H H H H H H H H H H H H L
L L H L L L L L L H H H H H H H H H H H H L
L L H L H L L L L L H H H H H H H H H H H L
L L H H L L L L L L L H H H H H H H H H H L
L L H H H L L L L L L L H H H H H H H H H L
L H L L L L L L L L L L L H H H H H H H H L
L H L L H L L L L L L L L L H H H H H H H L
L H L H L L L L L L L L L L L H H H H H H L
L H L H H L L L L L L L L L L L H H H H H L
L H H L L L L L L L L L L L L L L H H H H L
L H H L H L L L L L L L L L L L L L H H H L
L H H H L L L L L L L L L L L L L L L H H L
L H H H H L L L L L L L L L L L L L L L H L
L All other combinations H
H Any combination H

PRODUCTION DATA information is current as of publication date. Copyright  1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALS677A
16-BIT ADDRESS COMPARATOR
SDAS012C – JUNE 1982 – REVISED JANUARY 1995

logic symbol†

23 [ADDRESS COMP]
G EN
18 P≥1 =1 &
P0 0 1
19 P≥2
P1 =1
20 P 2
P2 P≥3 =1
21
P3 3 3
1 P≥4 =1
A1 Z1 4
2
A2 Z2 P≥5 =1
3 5
A3 Z3
4 P≥6 =1
A4 Z4 6
5 P≥7 =1
A5 Z5 7
6 22
A6 Z6 P≥8 =1 Y
7 8
A7 Z7
8 P≥9 =1
A8 Z8 9
9 P ≥ 10 =1
A9 Z9
10 10
A10 Z10 P ≥ 11 =1
11 11
A11 Z11
13 P ≥ 12 =1
A12 Z12 12
14 P ≥ 13 =1
A13 Z13
15 13
A14 Z14 P ≥ 14 =1
16 14
A15 Z15
17 P ≥ 15 =1
A16 Z16 15
16

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
 SN74ALS677A
16-BIT ADDRESS COMPARATOR
SDAS012C – JUNE 1982 – REVISED JANUARY 1995

logic diagram (positive logic)

1
A1

2
A2

3
A3

4
A4

5
A5

6
A6

7
A7

8
A8 22
Y

9
A9

10
A10

11
A11

13
A12

14
A13

15
A14

16
A15
17
A16
18
P0
19
P1
20
P2
21
P3
23
G
SN74ALS677A
16-BIT ADDRESS COMPARATOR
SDAS012C – JUNE 1982 – REVISED JANUARY 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current – 2.6 mA
IOL Low-level output current 24 mA
TA Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT
VIK VCC = 4.5 V, II = – 18 mA – 1.2 V
VCC = 4.5 V to 5.5 V, IOH = – 0.4 mA VCC – 2
VOH V
VCC = 4.5 V, IOH = – 2.6 mA 2.4 3.2
IOL = 12 mA 0.25 0.4
VOL VCC = 4
4.5
5V V
IOL = 24 mA 0.35 0.5
II VCC = 5.5 V, VI = 7 V 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 µA
IIL VCC = 5.5 V, VI = 0.4 V – 0.1 mA
IO§ VCC = 5.5 V, VO = 2.25 V – 30 –112 mA
ICC VCC = 5.5 V 21 33 mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

switching characteristics (see Figure 2)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
FROM TO RL = 500 Ω,
PARAMETER UNIT
(INPUT) (OUTPUT) TA = MIN to MAX¶
MIN MAX
tPLH 4 25
Any P Y ns
tPHL 8 38
tPLH 5 22
Any A Y ns
tPHL 5 30
tPLH 3 13
G Y ns
tPHL 5 35
¶ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
 SN74ALS677A
16-BIT ADDRESS COMPARATOR
SDAS012C – JUNE 1982 – REVISED JANUARY 1995

APPLICATION INFORMATION

The SN74ALS677A can be wired to recognize any one of 216 addresses. The number of lows in the address
determines the input pattern for the P inputs. Those system address lines that are low in the address to be recognized
are connected to the lowest-numbered A inputs of the address comparator. The system address lines that are high
are connected to the highest-numbered A inputs.
For example, assume the comparator is to enable a device when the 16-bit system address is:

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

H H L L H H L L H H L L H H H H
Because the address contains six lows and ten highs, the following connections are made:
• P3 to 0 V, P2 to VCC, P1 to VCC, and P0 to 0 V
• System address lines A13, A12, A9, A8, A5, and A4 to comparator inputs A1 through A6 in any
convenient order
• The remaining ten system address lines to comparator inputs A7 through A16 in any convenient order
The output provides an active-low enabling signal.
Figure 1 shows a modulo-N synchronous counter. The ′ALS163B provides a low-level clear signal when N = FEFF16.

15 12 8 4 0
FEFF16 = HHHH HHHL HHHH HHHH

Four
′ALS163B SN74ALS677A

CTR 16 [ADDRESS
CLR G COMP]
1R EN
CLK P0
CLK C1/+ VCC 0
P1
P2 P
Maximum
P3 Count
8 3
0...7
A1
8 [P = 1]
7 15 A2 – A16
9 . . . 15

Figure 1. Modulo-N Synchronous Counter

SN74ALS677A
16-BIT ADDRESS COMPARATOR
SDAS012C – JUNE 1982 – REVISED JANUARY 1995

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
VCC RL = R1 = R2

S1
RL
R1
From Output Test From Output Test From Output Test
Under Test Point Under Test Point Under Test Point
CL RL CL
CL R2
(see Note A) (see Note A)
(see Note A)

LOAD CIRCUIT FOR

BI-STATE LOAD CIRCUIT LOAD CIRCUIT
TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

Timing 3.5 V High-Level 3.5 V

Input 1.3 V Pulse 1.3 V 1.3 V
0.3 V 0.3 V
th tw
tsu
3.5 V 3.5 V
Data Low-Level
Input 1.3 V 1.3 V 1.3 V 1.3 V
Pulse
0.3 V 0.3 V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3.5 V
Output
Control 1.3 V 1.3 V
(low-level
enabling) 0.3 V 3.5 V
tPZL Input 1.3 V 1.3 V
tPLZ
[3.5 V 0.3 V
tPHL
Waveform 1 tPLH
S1 Closed 1.3 V
In-Phase VOH
(see Note B) 1.3 V 1.3 V
VOL Output
tPHZ 0.3 V VOL
tPZH tPLH
VOH tPHL
Waveform 2 VOH
Out-of-Phase
S1 Open 1.3 V 0.3 V 1.3 V 1.3 V
Output
(see Note B)
[0 V (see Note C) VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

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