MC74HC14A

Hex Schmitt-Trigger
Inverter
High−Performance Silicon−Gate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS http://onsemi.com
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The HC14A is useful to “square up” slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds SOIC−14 NB TSSOP−14
applications in noisy environments. D SUFFIX DT SUFFIX
CASE 751A CASE 948G
Features
• Output Drive Capability: 10 LSTTL Loads PIN ASSIGNMENT
• Outputs Directly Interface to CMOS, NMOS and TTL VCC A6 Y6 A5 Y5 A4 Y4
• Operating Voltage Range: 2.0 to 6.0 V 14 13 12 11 10 9 8
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 60 FETs or 15 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring 1 2 3 4 5 6 7
Unique Site and Control Change Requirements; AEC−Q100 A1 Y1 A2 Y2 A3 Y3 GND
Qualified and PPAP Capable
14−Lead (Top View)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant MARKING DIAGRAMS

LOGIC DIAGRAM 14
14
HC
1 2 HC14AG 14A
A1 Y1 AWLYWW ALYWG
G
1 1
3 4
A2 Y2 TSSOP−14
SOIC−14 NB
A = Assembly Location
5 6 L, WL = Wafer Lot
A3 Y3
Y, YY = Year
Y=A W, WW = Work Week
9 8 G or G = Pb−Free Package
A4 Y4 Pin 14 = VCC
(Note: Microdot may be in either location)
Pin 7 = GND
11 10 FUNCTION TABLE
A5 Y5
Inputs Outputs
13 12 A Y
A6 Y6
L H
H L

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 14 MC74HC14A/D
 MC74HC14A

MAXIMUM RATINGS
Symbol Parameter Value Unit This device contains protection
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V circuitry to guard against damage
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must
be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
voltage higher than maximum rated
Iin DC Input Current, per Pin ±20 mA voltages to this high−impedance
circuit. For proper operation, Vin and
Iout DC Output Current, per Pin ±25 mA
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ±50 mA range GND v (Vin or Vout) v VCC.
Unused inputs must always be
PD Power Dissipation in Still Air, SOIC Package† 500 mW tied to an appropriate logic voltage
TSSOP Package† 450 level (e.g., either GND or VCC).
Tstg Storage Temperature Range –65 to +150 _C Unused outputs must be left open.

TL Lead Temperature, 1 mm from Case for 10 Seconds _C

Plastic DIP, SOIC or TSSOP Package 260

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature Range, All Package Types –55 +125 _C
tr, tf Input Rise/Fall Time VCC = 2.0 V 0 No Limit* ns
(Figure 1) VCC = 4.5 V 0 No Limit*
VCC = 6.0 V 0 No Limit*
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*When Vin = 50% VCC, ICC > 1mA

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 MC74HC14A

DC CHARACTERISTICS (Voltages Referenced to GND)

VCC Guaranteed Limit
Symbol Parameter Condition V −55 to 25°C ≤85°C ≤125°C Unit
VT+ max Maximum Positive−Going Input Vout = 0.1V 2.0 1.50 1.50 1.50 V
Threshold Voltage |Iout| ≤ 20mA 3.0 2.15 2.15 2.15
(Figure 3) 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VT+ min Minimum Positive−Going Input Vout = 0.1V 2.0 1.0 0.95 0.95 V
Threshold Voltage |Iout| ≤ 20mA 3.0 1.5 1.45 1.45
(Figure 3) 4.5 2.3 2.25 2.25
6.0 3.0 2.95 2.95
VT− max Maximum Negative−Going Input Vout = VCC − 0.1V 2.0 0.9 0.95 0.95 V
Threshold Voltage |Iout| ≤ 20mA 3.0 1.4 1.45 1.45
(Figure 3) 4.5 2.0 2.05 2.05
6.0 2.6 2.65 2.65
VT− min Minimum Negative−Going Input Vout = VCC − 0.1V 2.0 0.3 0.3 0.3 V
Threshold Voltage |Iout| ≤ 20mA 3.0 0.5 0.5 0.5
(Figure 3) 4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
VHmax Maximum Hysteresis Voltage Vout = 0.1V or VCC − 0.1V 2.0 1.20 1.20 1.20 V
(Note 1) (Figure 3) |Iout| ≤ 20mA 3.0 1.65 1.65 1.65
4.5 2.25 2.25 2.25
6.0 3.00 3.00 3.00
VHmin Minimum Hysteresis Voltage Vout = 0.1V or VCC − 0.1V 2.0 0.20 0.20 0.20 V
(Note 1) (Figure 3) |Iout| ≤ 20mA 3.0 0.25 0.25 0.25
4.5 0.40 0.40 0.40
6.0 0.50 0.50 0.50
VOH Minimum High−Level Output Vin ≤ VT− min 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20mA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin ≤ VT− min |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low−Level Output Vin ≥ VT+ max 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20mA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin ≥ VT+ max |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 mA
Current (per Package) Iout = 0mA
1. VHmin > (VT+ min) − (VT− max); VHmax = (VT+ max) − (VT− min).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

VCC Guaranteed Limit
Symbol Parameter V −55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Inverter)* 22 pF
* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .

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 MC74HC14A

tf tr
VCC
90%
INPUT A 50%
10% GND
tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)

3
(VT+) VHtyp

2
(VT-)

2 3 4 5 6
VCC, POWER SUPPLY VOLTAGE (VOLTS)

VHtyp = (VT+ typ) - (VT- typ)

Figure 3. Typical Input Threshold, VT+, VT− versus Power Supply Voltage

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 MC74HC14A

A Y

(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt-Trigger Offers Maximum Noise Immunity

VCC VCC
VH VH
VT+ VT+
Vin Vin
VT- VT-

GND GND

VOH VOH

Vout Vout

VOL VOL

Figure 4. Typical Schmitt−Trigger Applications

ORDERING INFORMATION
Device Package Shipping†
MC74HC14ADG SOIC−14 NB 55 Units / Rail
(Pb−Free)

MC74HC14ADR2G SOIC−14 NB 2500 / Tape & Reel

(Pb−Free)

MC74HC14ADTG TSSOP−14 96 Units / Rail

(Pb−Free)

MC74HC14ADTR2G TSSOP−14 2500 / Tape & Reel

(Pb−Free)

NLV74HC14ADG* SOIC−14 NB 55 Units / Rail

(Pb−Free)

NLV74HC14ADR2G* SOIC−14 NB 2500 / Tape & Reel

(Pb−Free)

NLV74HC14ADTG* TSSOP−14 96 Units / Rail

(Pb−Free)

NLV74HC14ADTR2G* TSSOP−14 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable

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 MC74HC14A

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.

ÉÉÉ
ÇÇÇ
−V− K1 MILLIMETERS INCHES
DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
SECTION N−N F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
−W− J 0.09 0.20 0.004 0.008
C J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
−T− SEATING D G H DETAIL E M 0_ 8_ 0_ 8_
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC74HC14A

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
ISSUE K
D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
b DIM MIN MAX MIN MAX
0.25 M B M 13X
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h D 8.55 8.75 0.337 0.344
A X 45 _ E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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