Low Power Dual 8-Input Multiplexer: General Description Features

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100363 Low Power Dual 8-Input Multiplexer

July 1992

100363
Low Power Dual 8-Input Multiplexer
General Description Features
The 100363 is a dual 8-input multiplexer. The Data Select Y 50% power reduction of the 100163
(Sn) inputs determine which bit (An and Bn) will be present- Y 2000V ESD protection
ed at the outputs (Za and Zb respectively). The same bit Y Pin/function compatible with 100163
(0 – 7) will be selected for both the Za and Zb output. All Y Voltage compensated operating range e b4.2V to
inputs have 50 kX pulldown resistors. b 5.7V
Y Available to MIL-STD-883
Y Available to industrial grade temperature range

Logic Symbol
Pin Names Description
S0 –S2 Data Select Inputs
A0 –A7 A Data Inputs
B0 –B7 B Data Inputs
Za, Zb Data Outputs

TL/F/10612 – 1

Connection Diagrams
24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak

TL/F/10612 – 3

TL/F/10612 – 4

TL/F/10612–2

C1995 National Semiconductor Corporation TL/F/10612 RRD-B30M105/Printed in U. S. A.


Logic Diagram

TL/F/10612 – 5

Truth Table
Inputs
Outputs
Select Data
A7 A6 A5 A4 A3 A2 A1 A0 Za
S2 S1 S0
B7 B6 B5 B4 B3 B2 B1 B0 Zb
L L L L L
L L L H H
L L H L L
L L H H H
L H L L L
L H L H H
L H H L L
L H H H H
H L L L L
H L L H H
H L H L L
H L H H H
H H L L L
H H L H H
H H H L L
H H H H H
H e HIGH Voltage Level
L e LOW Voltage Level
Blank e X e Don’t Care

2
Absolute Maximum Ratings Recommended Operating
Above which the useful life may be impared (Note 1)
Conditions
If Military/Aerospace specified devices are required,
Case Temperature (TC)
please contact the National Semiconductor Sales
Commercial 0§ C to a 85§ C
Office/Distributors for availability and specifications.
Industrial b 40§ C to a 85§ C
Storage Temperature (TSTG) b 65§ C to a 150§ C Military b 55§ C to a 125§ C
Maximum Junction Temperature (TJ) Supply Voltage (VEE) b 5.7V to b 4.2V
Ceramic a 175§ C
Plastic a 150§ C
VEE Pin Potential to Ground Pin b 7.0V to a 0.5V
Input Voltage (DC) VEE to a 0.5V
Output Current (DC Output HIGH) b 50 mA
ESD (Note 2) t 2000V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics
VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0§ C to a 85§ C (Note 3)

Symbol Parameter Min Typ Max Units Conditions


VOH Output HIGH Voltage b 1025 b 955 b 870 mV VIN e VIH (Max) Loading with
or VIL (Min) 50X to b2.0V
VOL Output LOW Voltage b 1830 b 1705 b 1620 mV
VOHC Output HIGH Voltage b 1035 mV VIN e VIH (Min) Loading with
or VIL (Max) 50X to b2.0V
VOLC Output LOW Voltage b 1610 mV
VIH Input HIGH Voltage b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs
VIL Input LOW Voltage b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs
IIL Input LOW Current 0.50 mA VIN e VIL (Min)
IIH Input HIGH Current VIN e VIH (Max)
Sn 265
mA
An, Bn 340
IEE Power Supply Current b 80 b 40 mA Inputs Open
Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.

DIP AC Electrical Characteristics


VEE e b4.2V to b5.7V, VCC e VCCA e GND

TC e 0§ C TC e a 25§ C TC e a 85§ C
Symbol Parameter Units Conditions
Min Max Min Max Min Max
tPLH Propagation Delay
0.70 1.65 0.80 1.70 0.80 1.80 ns
tPHL A0 – A7, B0 – B7 to Output
tPLH Propagation Delay
1.30 2.60 1.40 2.70 1.40 2.70 ns Figures 1 and 2
tPHL S0 – S2 to Output
tTLH Transition Time
0.45 1.30 0.45 1.30 0.45 1.30 ns
tTHL 20% to 80%, 80% to 20%

3
Commercial Version (Continued)

PCC and Cerpak AC Electrical Characteristics


VEE e b4.2V to b5.7V, VCC e VCCA e GND

TC e 0§ C TC e a 25§ C TC e a 85§ C
Symbol Parameter Units Conditions
Min Max Min Max Min Max
tPLH Propagation Delay
0.70 1.65 0.80 1.70 0.80 1.80 ns
tPHL A0 – A7, B0 – B7 to Output
tPLH Propagation Delay
1.30 2.60 1.40 2.70 1.40 2.70 ns Figures 1 and 2
tPHL S0 – S2 to Output
tTLH Transition Time
0.45 1.30 0.45 1.30 0.45 1.30 ns
tTHL 20% to 80%, 80% to 20%

4
Industrial Version

DC Electrical Characteristics
VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40§ C to a 85§ C (Note 1)

TC e b40§ C TC e 0§ C to a 85§ C
Symbol Parameter Units Conditions
Min Max Min Max
VOH Output HIGH Voltage b 1085 b 870 b 1025 b 870 mV VIN e VIH (max) Loading with
VOL Output LOW Voltage b 1830 b 1575 b 1830 b 1620 mV or VIL (min) 50X to b2.0V

VOHC Output HIGH Voltage b 1095 b 1035 mV VIN e VIH (min) Loading with
VOLC Output LOW Voltage b 1565 b 1610 mV or VIL (max) 50X to b2.0V

VIH Input HIGH Voltage b 1170 b 870 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs
VIL Input LOW Voltage b 1830 b 1480 b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs
IIL Input LOW Current 0.50 0.50 mA VIN e VIL (min)
IIH Input HIGH Current VIN e VIH (Max)
Sn 265 265
mA
An, Bn 380 340
IEE Power Supply Current b 80 b 35 b 80 b 40 mA Inputs Open
Note 1: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.

AC Electrical Characteristics
VEE e b4.2V to b5.7V, VCC e VCCA e GND
TC e b40§ C TC e a 25§ C TC e a 85§ C
Symbol Parameter Units Conditions
Min Max Min Max Min Max
tPLH Propagation Delay
0.60 1.65 0.80 1.70 0.80 1.80 ns
tPHL A0 – A7, B0 – B7 to Output
tPLH Propagation Delay
1.20 2.60 1.40 2.70 1.40 2.70 ns Figures 1 and 2
tPHL S0 – S2 to Output
tTLH Transition Time
0.30 1.90 0.45 1.30 0.45 1.30 ns
tTHL 20% to 80%, 80% to 20%

5
Military Version

DC Electrical Characteristics
VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55§ C to a 125§ C

Symbol Parameter Min Max Units TC Conditions Note


VOH Output HIGH Voltage 0§ C to
b 1025 b 870 mV
a 125§ C
b 1085 b 870 mV b 55§ C VIN e VIH (Max) Loading with
1, 2, 3
VOL Output LOW Voltage 0§ C to or VIL (Min) 50X to b2.0V
b 1830 b 1620 mV
a 125§ C
b 1830 b 1555 mV b 55§ C

VOHC Output HIGH Voltage 0§ C to


b 1035 mV
a 125§ C
b 1085 mV b 55§ C VIN e VIH (Min) Loading with
1, 2, 3
VOLC Output LOW Voltage 0§ C to or VIL (Max) 50X to b2.0V
b 1610 mV
a 125§ C
b 1555 mV b 55§ C

VIH Input HIGH Voltage b 55§ C to Guaranteed HIGH Signal for All Inputs
b 1165 b 870 mV 1, 2, 3, 4
a 125§ C

VIL Input LOW Voltage b 55§ C to Guaranteed LOW Signal for All Inputs
b 1830 b 1475 mV 1, 2, 3, 4
a 125§ C

IIL Input LOW Current b 55§ C to VEE e b4.2V


0.50 mA 1, 2, 3
a 125§ C VIN e VIL (Min)
IIH Input HIGH Current
Sn 265 0§ C to
mA
An, Bn 340 a 125§ C VEE e b5.7V 1, 2, 3
VIN e VIH (Max)
Sn 385
mA b 55§ C
An, Bn 490
IEE Power Supply Current b 55§ C to Inputs Open
b 87 b 30 mA 1, 2, 3
a 125§ C

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55§ C), then testing
immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be
considered a worst case condition at cold temperatures.
Note 2: Screen tested 100% on each device at b 55§ C, a 25§ C, and a 125§ C, Subgroups 1, 2, 3, 7, and 8.
Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b 55§ C, a 25§ C, and a 125§ C, Subgroups A1, 2, 3, 7, and 8.
Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.

6
Military Version (Continued)

AC Electrical Characteristics
VEE e b4.2V to b5.7V, VCC e VCCA e GND

TC e b55§ C TC e a 25§ C TC e a 125§ C


Symbol Parameter Units Conditions Notes
Min Max Min Max Min Max
tPLH Propagation Delay
0.50 2.40 0.60 2.30 0.70 3.00 ns
tPHL A0 – A7, B0 – B7 to Output
1, 2, 3
tPLH Propagation Delay
0.80 3.00 0.90 2.80 0.80 3.40 ns Figures 1 and 2
tPHL S0 – S2 to Output
tTLH Transition Time
0.30 1.90 0.40 1.80 0.30 2.10 ns 4
tTHL 20% to 80%, 80% to 20%
Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55§ C), then testing
immediately after power-up. This provides ‘‘cold start’’ specs which can be considered a worst case condition at cold temperatures.
Note 2: Screen tested 100% on each device at a 25§ C temperature only, Subgroup A9.
Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a 25§ C, Subgroup A9, and at a 125§ C and b 55§ C, temperatures, Subgroups A10 and
A11.
Note 4: Not tested at a 25§ C, a 125§ C, and b 55§ C temperature (design characterization data).

Test Circuitry

Notes: TL/F/10612 – 6
VCC, VCCA e a 2V, VEE e b 2.5V FIGURE 1. AC Test Circuit
L1 and L2 e equal length 50X impedance lines
RT e 50X terminator internal to scope
Decoupling 0.1 mF from GND to VCC and VEE
All unused outputs are loaded with 50X to GND
CL e Fixture and stray capacitance s 3 pF
Pin numbers shown are for flatpak; for DIP see logic symbol

7
Switching Waveforms

TL/F/10612 – 7
FIGURE 2. Propagation Delay and Transition Times

Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:

100363 D C QB

Device Type (Basic) Special Variation


QB e Military grade device with
Package Code environmental and burn-in
D e Ceramic DIP processing
F e Quad Cerpak
Q e Plastic Leaded Chip Carrier (PCC) Temperature Range
P e Plastic DIP C e Commercial (0§ C to a 85§ C)
I e Industrial (b40§ C to a 85§ C)
(PCC only)
M e Military (b55§ C to a 125§ C)
Physical Dimensions inches (millimeters)

24-Pin Ceramic Dual-In-Line Package (D)


NS Package Number J24E

8
Physical Dimensions inches (millimeters) (Continued)

24-Lead Plastic Dual-In-Line Package (P)


NS Package Number N24E

24-Pin Quad Cerpak (F)


NS Package Number W24B

9
100363 Low Power Dual 8-Input Multiplexer
Physical Dimensions inches (millimeters) (Continued) Lit. Ý114927

28-Pin Plastic Leaded Chip Carrier (Q)


NS Package Number V28A

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SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
This datasheet has been download from:

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