74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description the outputs until the next rising edge of the Clock Pulse input. The F74 is a dual D-type flip-flop with Direct Clear and Set Asynchronous Inputs: inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge LOW input to SD sets Q to HIGH level of the clock pulse. Clock triggering occurs at a voltage level LOW input to CD sets Q to LOW level of the clock pulse and is not directly related to the transition Clear and Set are independent of clock time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is Simultaneous LOW on CD and SD locked out and information present will not be transferred to makes both Q and Q HIGH
Ordering Code: Order Number Package Number Package Description 74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
74F74 Unit Loading/Fan Out U.L. Input IIH/IIL Pin Names Description HIGH/LOW Output IOH/IOL
D1 , D2 Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA Q1, Q1, Q2, Q2 Outputs 50/33.3 −1 mA/20 mA
Truth Table Inputs Outputs
SD CD CP D Q Q
L H X X H L H L X X L H L L X X H H H H h H L H H l L H H H L X Q0 Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial Q0 = Previous Q (Q) before LOW-to-HIGH Clock Transition Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com 2 74F74 Absolute Maximum Ratings(Note 1) Recommended Operating Storage Temperature −65°C to +150°C Conditions Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature 0°C to +70°C Junction Temperature under Bias −55°C to +150°C Supply Voltage +4.5V to +5.5V VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation 3-STATE Output −0.5V to +5.5V under these conditions is not implied. Current Applied to Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V
DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH 10% VCC 2.5 IOH = −1 mA V Min Voltage 5% VCC 2.7 IOH = −1 mA VOL Output LOW 10% VCC 0.5 V Min IOL = 20 mA Voltage IIH Input HIGH 5.0 µA Max VIN = 2.7V Current IBVI Input HIGH Current 7.0 µA Max VIN = 7.0V Breakdown Test ICEX Output HIGH 50 µA Max VOUT = VCC Leakage Current VID Input Leakage IID = 1.9 µA 4.75 V 0.0 Test All Other Pins Grounded IOD Output Leakage VIOD = 150 mV 3.75 µA 0.0 Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 VIN = 0.5V (D, CP) mA Max −1.8 VIN = 0.5V (CD, SD) IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V ICC Power Supply Current 10.5 16.0 mA Max
3 www.fairchildsemi.com 74F74 AC Electrical Characteristics TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V Symbol Parameter Units CL = 50 pF CL = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 100 125 100 MHz tPLH Propagation Delay 3.8 5.3 6.8 3.8 7.8 ns tPHL CPn to Qn or Qn 4.4 6.2 8.0 4.4 9.2 tPLH Propagation Delay 3.2 4.6 6.1 3.2 7.1 ns tPHL CDn or SDn to Qn or Qn 3.5 7.0 9.0 3.5 10.5
AC Operating Requirements TA = +25°C TA = 0°C to +70°C Symbol Parameter VCC = +5.0V VCC = +5.0V Units Min Max Min Max tS(H) Setup Time, HIGH or LOW 2.0 2.0 tS(L) Dn to CPn 3.0 3.0 ns tH(H) Hold Time, HIGH or LOW 1.0 1.0 tH(L) Dn to CPn 1.0 1.0 tW(H) CPn Pulse Width 4.0 4.0 ns tW(L) HIGH or LOW 5.0 5.0
tW(L) CDn or SDn Pulse Width
4.0 4.0 ns LOW tREC Recovery Time 2.0 2.0 ns CDn or SDn to CP
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user.
