Received: 20 July 2020

DOI: 10.1049/cds2.12049
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Revised: 29 September 2020

O R I G I N A L R E S E A R C H PA P E R
Accepted: 2 November 2020

- IET Circuits, Devices & Systems

Temperature dependence of analogue/RF performance, linearity

and harmonic distortion for dual‐material gate‐oxide‐stack
double‐gate TFET

Satyendra Kumar

Department of Electronics and Communication Abstract

Engineering, Jaypee Institute of Information
Technology, Noida, Uttar Pradesh, India
This article presents an investigation report of the effects of temperature variation in the
range of 300 to 480 K on electrical performance parameters of conventional dual‐
Correspondence material double‐gate tunnel field effect transistor (DMDG‐TFET) and dual‐material gate‐
Satyendra Kumar, Jaypee Institute of Information oxide‐stack double‐gate tunnel field effect transistor (DMGOSDG‐TFET). This report
Technology, Sector‐128, Jaypee wish town village, shows an analysis and comparison of the impacts of operating temperature variation on
Sultanpur, Noida, 201 304, Uttar Pradesh, India.
Email: [email protected]
both the devices in terms of DC, analogue/RF, linearity and harmonic distortion pa-
rameters with the help of simulation results obtained using a numerical device simulator.
It could be stated that DMGOSDG‐TFET is more insensitive with respect to temper-
ature variation in terms of DC, analogue/RF and linearity performances as compared to
conventional DMDG‐TFET. Moreover, in terms of harmonic distortion characteristics
DMGOSDG‐TFET is found to be more stable with temperature variation as compared
to DMDG‐TFET.

1 | INTRODUCTION [27–30]. Although the above‐mentioned approaches were

found to limit the ambipolar conduction, they lead to reduction
In the recent research, to address the scaling limit issues of the in the ION and increase in the drain series resistance. Therefore,
metal‐oxide‐semiconductor field effect transistors (MOSFETs) in order to improve the ION and suppress the ambipolarity
several types of low geometry devices have been investigated behaviour, dual material double gate tunnel field effect tran-
[1–5]. Among them the tunnel field effect transistor (TFET) is sistor (DMDG‐TFET) has been proposed in [31]. Further, to
regarded as one of the most promising alternatives of con- improve the DC and analogue/RF performances in addition to
ventional MOSFET as it can get the better of the subthreshold switching ratio of DMDG‐TFET, a new device Dual‐material
swing (SS) limitation as well as the leakage current issue of the Gate‐oxide‐stack Double‐gate TFET (DMGOSDG‐TFET)
conventional device due to its working principle based on has been introduced and examined in [32]. In DMGOSDG‐
quantum tunnelling of charge carriers rather than thermionic TFET, use of high‐k gate dielectric (HfO2) helps to increase
emission [6–18]. However, TFET has been reported to be the coupling between gate and its underneath silicon, further
suffering, mainly with ambipolar conduction and limited ON‐ the use of dual gate work‐function engineering improves the
state current (ION) due to the poor band‐to‐band tunnelling ION as well as the ambipolarity behaviour of the device.
(BTBT) efficiency [11–21]. To address the issue of limited Non‐linear behaviour of the active devices results in har-
ON‐state current, many concepts like strained‐Si, hetero- monic distortion (HD), which is a critical issue for analogue/
structure TFET and pocket doping have been suggested in the mixed signal circuit design. Therefore, the devices used in the
literature [22–26]. Also to resolve the issue of ambipolar integrated circuits (ICs) designed for analogue/mixed signal
conduction several approaches such as: use of heterogeneous applications, should have lower HD. The increasing integration
gate dielectric, various doping profile in the drain region, large of metal‐oxide semiconductor devices in the ICs dedicated to
band gap material on the drain side and dual‐material double‐ analogue/RF applications for high temperature environments
source T‐shaped TFET, have been proposed by the researchers has demanded further prediction of component's electrical

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© 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.

IET Circuits Devices Syst. 2021;1–13. wileyonlinelibrary.com/journal/cds2 1

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behaviour at higher temperature range [33]. Also, the overall

cost of electronic control systems employed in the elevated
temperature environment like in avionics, automobiles,
geothermal oil wells and so forth, can be reduced significantly
if the devices can operate directly in hot areas. Also, these
devices do not require additional equipments for insulation and
cooling mechanisms, which maintain the temperature within
the range tolerated by silicon/germanium based devices,
currently near to 390 K [34,35]. An investigation of DC,
analogue/RF, linearity performance and HD parameters of the
semiconductor devices at elevated temperature range is the
subject of great interest for the electronic systems designed to
be employed in higher temperature environment [33,36,37].
In this study, we have undertaken the comprehensive
analysis of conventional dual‐material double‐gate TFET and
DMGOSDG‐TFET in terms of DC characteristics, analogue/
RF performance, linearity performance and HD parameters at
elevated temperature ranges from 300 to 480 K with the help
of simulations results obtained using technology computer‐
aided design (TCAD) tool. Therefore, it can be stated that the
main aim of this article is to investigate and compare the
temperature sensitivities of DMDG‐TFET and DMGOSDG‐
TFET with respect to analogue/RF, linearity and HD param-
eters, for higher temperature environments.
This article is divided in four sections. Section 2 describes
the device structure and simulation setup. Section 3 presents
the temperature sensitivity analysis of both the devices for
elevated temperature range using simulation results, in four
subsections. Section 3.1 gives the analysis of both the devices
in terms of different operating states concentration profiles,
and Section 3.2 includes the temperature sensitivity analysis in
terms of DC characteristics. Section 3.3 investigates the impact
of temperature variation in terms of analogue/RF perfor-
mances and Section 3.4 in terms of the linearity and distortion F I G U R E 1 Cross‐sectional views of (a) conventional DMDG‐TFET
parameters. Finally, the work is concluded in Section 4. [31] and (b) DMGOSDG‐TFET [32]

engineering at gate electrode helps to overcome the drawback

2 | DEVICE STRUCTURE AND of ambipolarity in a TFET structure. In the simulation setup
SIMULATION SETUP for this work, we have not been taken care of quantum
confinement effect as the thickness of silicon body is 10.0 nm.
The cross‐sectional views of conventional DMDG‐TFET and The gate leakage tunnelling through the gate oxide has also not
DMGOSDG‐TFET are shown in Figure 1a,b, respectively. been considered in this study.
The corresponding design parameters for both the devices are In simulation setup non‐local BTBT model is activated
listed in Table 1 [31,32]. to account the tunnelling of electrons in forward as well as
The metal gate structure of both the devices is tri‐ reverse direction of degenerately doped p‐n junctions.
segmented into tunnel gate (M1), control gate (M2) and Shockley Read Hall (SRH) and Auger recombination models
auxiliary gate (M3) with the respective work‐functions as ϕ1, are used to observe the minority recombination effect [3,38].
ϕ2 and ϕ3. The material selected for tunnel and auxiliary gate Concentration‐dependent mobility model (CONMOB) and
electrodes is aluminium (Al) as its work‐function meets 4.0 eV, field‐dependent mobility model (FLDMOB) are employed
whereas for control gate electrode is molybdenum (Mo) as its to observe the impacts of different doping concentrations
work‐function meets 4.6 eV [21]. Conventional device as and electric fields on the carrier mobilities. Band gap nar-
shown in Figure 1a, consist of single SiO2 layer with thickness rowing (BGN) model is invoked to account the narrowing
of 2.0 nm, whereas as depicted in Figure 1b, DMGOSDG‐ band gap due to high doping concentration. Fermi Dirac
TFET having gate‐oxide in stack fashion of HfO2 and SiO2 statistics account for certain properties of degenerated ma-
layers. The stacked oxide layer in DMGOSDG‐TFET which terials, such as reduced carrier concentrations in heavily
helps to improve the on‐state current due to better capacitive doped source and drain regions, therefore Fermi Dirac
coupling between the gate and the channel. Work‐function statistics is used [39].
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TA B L E 1 Design parameters used in the simulation of the devices As shown in Figure 2c,d in ON‐state of both the devices,
Parameters Symbols Values
due to the gate bias VGS = 1.5 V, the electron concentration
increases and the hole concentration decreases in the channel
Gate length Lg 50 nm region. Also, there is negligible variation in majority carrier
SiO2 thickness (conventional TFET) tSiO2 _conv 2.0 nm concentration with change of temperature, while a significant
variation in the minority carrier concentration is observed.
SiO2 thickness tSiO2 0.8 nm
Furthermore, it can be seen from Figure 2c,d, that abruptness
HfO2 thickness tHf O2 1.2 nm in the majority carrier concentration at source/channel inter-
face is higher in the case of DMGOSDG‐TFET as compared
Silicon thickness tSi 10 nm
to DMDG‐TFET. Accordingly, ON‐state and OFF‐state cur-
Tunnel gate work function ϕ1 4.0 eV rents are affected.
Control gate work function ϕ2 4.6 eV

Auxiliary gate work function ϕ3 4.0 eV

3.2 | Effect of temperature on DC
HfO2 dielectric constant k 25 characteristics
Tunnelling gate length L1 10 nm
In general, to understand the BTBT phenomenon of a semi-
Control gate length L2 25 nm conductor device, the energy band diagram is used. The energy
Auxiliary gate length L3 15 nm band gap of the semiconductor material decreases with in-
Channel doping NCH 1 � 1017 cm−3
crease in temperature, which affects the device characteristics
accordingly. Energy band gap temperature dependency can be
Source doping (p‐type) NS 1 � 1020 cm−3 described by the following equation [40]:
Drain doping (n‐type) ND 5 � 1018 cm−3

αT 2
Eg ðT Þ ¼ Eg ð0Þ − ð1Þ
3 | RESULTS AND DISCUSSION T þβ

Temperature, which is a physical parameter, affects the per- where Eg(T) is the band gap at absolute temperature T,
formance of the device. Therefore, this section deals with the Eg(0) represents the band gap at T = 0 K, α and β are the
temperature sensitivity investigation of DMDG‐TFET and fitting parameters. Figure 3a,b shows the effect of temperature
DMGOSDG‐TFET in terms of carrier concentration profile, variation on the energy band diagrams of conventional
DC characteristics, analogue/RF performances, linearity and DMDG‐TFET and DMGOSDG‐TFET respectively, along the
harmonic distortion parameters. This section also presents the X‐position for ON‐state (VGS = 1.50 V and VDS = 1.0 V).
comparison between both the devices in terms of above Irrespective of temperature variation, it can be observed from
mentioned parameters at elevated temperature ranges from 300 these results that, the band overlapping at source/channel
to 480 K. interface is more for DMGOSDG‐TFET as compared to the
conventional device. Which results in higher tunnelling of
electrons from the valance band at source side to the channel
3.1 | Carrier concentration profiles of both side conduction band for DMGOSDG‐TFET as compared to
the devices DMDG‐TFET. As demonstrated in these figures, the influence
of temperature variation is very small on the energy bands of
For the equilibrium state, carrier concentration profiles of both the devices.
DMDG‐TFET and DMGOSDG‐TFet along the channel are Under the ON‐state condition, the effect of temperature
shown in Figure 2a,b, respectively, while for ON‐state are variation on the electric field of DMDG‐TFET and
shown in Figure 2c,d. Along the x‐position, gate region is \DMGOSDG‐TFET is shown in Figure 4a,b, respectively.
extended from 25 to 75 nm for both the devices. Owing to the From these figures it can be stated that there is no significant
lower gate work‐function (ϕ3 = ϕ1 = 4.0 eV) for both the variation in the electric field with temperature changes for
devices that is under the gate electrodes M3 and M1 electron DMDG‐TFET as well as DMGOSDG‐TFET. Moreover, the
concentrations increase and the hole concentration decreases. peak of the electric field is higher for DMGOSDG‐TFET
It can be observed from Figure 2a,b, that the presence of high compared to DMDG‐TFET. It means electrical characteristics
gate‐dielectric in the case of DMGOSDG‐TFET, make above of the DMGOSDG‐TFET is less sensitive towards the tem-
discussed increment/decrement in electron/hole concentra- perature variation as compared with conventional DMDG‐
tion higher side as compared to DMDG‐TFET. As demon- TFET.
strated in Figure 2a,b, with rise in temperature, the electron Figure 4c,d presents the drain current (ID) versus gate to
concentration is increasing smoothly, while hole (minority) source voltage (VGS) characteristics for DMDG‐TFET and
concentration is increasing drastically [40]. DMGOSDG‐TFET at drain to source voltage (VDS) = 1.0 V
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(a) (b)

(c) (d)

F I G U R E 2 Variation in carrier concentration profile along the channel in Equilibrium‐state (VGS = 0.0 V and VDS = 0.0 V) for (a) DMDG‐TFET
(b) DMGOSDG‐TFET, with temperature. Variation in carrier concentration profile along the channel in ON‐state (VGS = 1.5 V and VDS = 1.0 V) for
(c) DMDG‐TFET (d) DMGOSDG‐TFET, with temperature

(a) (b)

FIGURE 3 ON‐state energy band diagram along x‐position at different temperatures for (a) DMDG‐TFET (b) DMGOSDG‐TFET
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(a) (b)

(c) (d)

F I G U R E 4 (a) Variation in electric field along x‐position at different temperatures for (a) DMDG‐TFET (b) DMGOSDG‐TFET, IDS‐VGS characteristics at
different temperatures for (c) DMDG‐TFET (d) DMGOSDG‐TFET, at VDS = 1.0 V

with temperature ranges from 300 to 480 K. Figures show that is defined as the first derivative of IDS − VGS characteristics of
ION is changing slightly with the variations in temperature as it a device, hence it is given by the following equation:
depends strongly on BTBT phenomenon rather than temper-
ature. On the other hand, IOFF rises significantly with the in- ∂I DS
crease in temperature because it depends on thermally gm ¼ ð2Þ
∂V GS
generated minority charge carriers in the depletion region [41],
which rises exponentially with temperature. Larger (ION) is also
seen for DMGOSDG‐TFET as compared to DMDG‐TFET In order to compute the gain of a device, its trans-
due to the presence of high‐k gate dielectric. Therefore, conductance is an important parameter. Therefore, gm of a
DMGOSDG‐TFET is more insensitive as compared to device plays a crucial role in the design and analysis of the
DMDG‐TFET with respect to temperature variation. circuits for analogue/RF applications. Figure 5a,b shows the
transconductance variation of DMDG‐TFET and
DMGOSDG‐TFET with VGS for VDS = 1.0 V at different
3.3 | Effect of temperature on analogue/RF temperature varying from 300 to 480 K. Also gm for
performance DMGOSDG‐TFET is on the higher side and shows less
temperature sensitivity as compared to DMDG‐TFET.
This section presents the impacts of temperature variation on Analog/RF and linearity performances of a device are
the analogue/RF performances of conventional DMDG‐ also determined with the help of its gate to source capacitance
TFET as well as DMGOSDG‐TFET. Transconductance (gm) (CGS) and gate to drain capacitance (CGD) [42]. These
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(a) (b)

FIGURE 5 Effects of temperature variation on transconductance (gm) with gate bias of (a) DMDG‐TFET (b) DMGOSDG‐TFET

capacitances have extracted from small signal analysis at Figure 7c,d shows the impact of temperature variation on
1 MHz frequency [21]. With positive gate voltage, (CGD) in- GBP for DMDG‐TFET and DMGOSDG‐TFET, respectively.
creases significantly due to the reduction in drain‐to‐channel GBP shows almost similar behaviour as fT for both the devices
barrier width, whereas CGS shows small reduction because of at different temperatures.
source‐to‐channel barrier width. Figure 6a,b shows the varia- Temperature sensitivity analysis in terms of maximum
tion in (CGD) with gate bias at different temperatures of oscillation frequency ( fmax) is also done for DMDG‐TFET
conventional DMDG‐TFET and DMGOSDG‐TFET and DMGOSDG‐TFET. fmax can be defined as per the
respectively, whereas Figure 6c,d in (CGS) of respective de- following equation [44]:
vices. It can be noticed from these results that variation in
(CGD) and (CGS) for both the devices, is smaller at lower gate sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
bias as compared to higher gate bias. Moreover, these capac- fT
f max ¼ ð5Þ
itances are at the larger side for DMGOSDG‐TFET as 8πC GD RGD
compared with the conventional device, therefore (CGD) and
(CGS) characteristics of DMGOSDG‐TFET are more stable Figure 7e,f present the variations in fmax with gate bias at
with respect to temperature variation, as compared to different temperatures for DMDG‐TFET and DMGOSDG‐
DMDG‐TFET. TFET, respectively. It is apparent that DMGOSDG‐TFET has
Cut‐off frequency ( fT) is another important parameter higher maximum oscillating frequency as compared to con-
for RF analysis point of view of a device. fT is defined as ventional DMDG‐TFET.
the frequency at which the current gain of the device From these results, it can be observed that DMGOSDG‐
becomes unity, it can be computed by the following TFET is less sensitive with respect to temperature variation as
equation [43]: compared to DMDG‐TFET.
�
f T ¼ gm ð2 � πðC GS þ C GD ÞÞ ð3Þ
3.4 | Effect of temperature on linearity and
According to this equation, it can be stated that gm, CGS
distortion parameters
and CGD are the governing parameters of fT. Figure 7a,b
Modern communication system needs to produce a signal with
present the effects of temperature variation on the cut‐off
minimum higher order harmonics. This critical criterion can be
frequency of DMDG‐TFET and DMGOSDG‐TFET respec-
achieved by designing the system with devices of better line-
tively. It can be observed from these results that fT of
arity. To get the better linearity of a device, its trans-
DMGOSDG‐TFET is higher side as compared to conven-
conductance should remain constant irrespective of gate
tional device and exhibits lesser temperature sensitivity for
voltage. However, the gm characteristics of MOSFET as well as
DMGOSDG‐TFET as compared to DMDG‐TFET.
TFET exhibit a variation with gate voltage [39]. Also, the
The gain bandwidth product (GBP) is another parameter
transconductance of these devices varies with temperature.
used for RF analysis of a device. GBP can be formulated as per
Therefore, this work investigates the effects of temperature
the following equation [42]:
variation on the linearity and signal distortion of both the
� devices in terms of gm2, gm3, VIP3, IIP3 and IMD3, where
GBP ¼ gm ð2 � π � 10 � C GD Þ ð4Þ these metrics are given as follows [45]:
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(a) (b)

(c) (d)

F I G U R E 6 Variation in gate‐to‐drain capacitance (CGD) as a function of gate bias at different temperatures, for (a) DMDG‐TFET (b) DMGOSDG‐TFET.
Variation in gate‐to‐source capacitance (CGS) as a function of gate bias at different temperatures, for (c) DMDG‐TFET (d) DMGOSDG‐TFET, at VDS = 1.0 V

Voltage intercept point VIP3 signifies the extrapolated

∂n I DS
gmn ¼ ð6Þ input voltage at which first and third harmonic voltages are
n!∂V nGS equal. Input intercept point IIP3 expresses the extrapolated
sffiffiffiffiffiffiffiffiffiffiffi�
ffiffiffiffiffiffiffiffiffiffi�
ffiffiffi input power at which third‐order intermodulation term of the
gm1 output becomes equal to the main harmonic. Furthermore,
V IP3 ¼ 24 � ð7Þ
gm3 third‐order intermodulation distortion IMD3 is the extrapo-
lated intermodulation power at which the power of the first‐
� � and the third‐order intermodulation components becomes
2 gm1 equal. For a device to be better in terms of linearity, parameters
IIP3 ¼ � ð8Þ
3 gm3 � RS VIP3 and IIP3 should be higher whereas IMD3 should be
lower.
� �2 gm2 and gm3 of DMDG‐TFET and DMGOSDG‐TFET
9
IMD3 ¼ � ðV IP3Þ2 � ðgm3 Þ � RS ð9Þ with gate bias at different temperatures are shown in
2
Figure 8a–d, respectively. From Figure 8a,b, it can be seen that
gm2 of both the devices remains almost insensitive with respect
Moreover, RS is taken as 50 Ω since this value usually used to temperature at lower VGS, while it exhibits temperature
for most of the RF applications. sensitivity around the peak which occurs at higher VGS. From
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(a) (b)

(c) (d)

(e) (f)

F I G U R E 7 Variation in cut‐off frequency (fT) with gate bias at different temperatures for (a) DMDG‐TFET (b) DMGOSDG‐TFET, Variation in gain
bandwidth product (GBP) with gate bias at different temperatures for (c) DMDG‐TFET (d) DMGOSDG‐TFET, Variation in maximum oscillation frequency
( fmax) with gate bias at different temperatures for (e) DMDG‐TFET, at VDS = 1.0 V

Figure 8c,d, it can be observed that gm3 of both the devices Figure 9a,b shows the VIP3 with gate voltage for DMDG‐
shows almost similar trend as of gm2 with respect to temper- TFET and DMGOSDG‐TFET, respectively, at elevated tem-
ature variation. perature ranges from 300 to 480 (k) From these results it may
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(a) (b)

(c) (d)

F I G U R E 8 Variation in the second‐order transconductance coefficient (gm2) with gate bias at different temperatures for (a) DMDG‐TFET
(b) DMGOSDG‐TFET. Variation in the third‐order transconductance coefficient (gm3) with gate bias at different temperatures for (c) DMDG‐TFET
(d) DMGOSDG‐TFET, at VDS = 1.0 V

be noticed that the peak of VIP3 occurs at higher gate bias are computed using the approximate analytical equations given
voltage, also the effects of temperature variation on VIP3 can as follows [46,47]:
be observed around the peak, for both the devices. The vari-
ations of IIP3 for DMDG‐TFET and DMGOSDG‐TFET at dg
different temperatures are shown in Figure 9c,d. Here, the 1 dV m
HD2 ¼ V a GS ð10Þ
impact of temperature variation can be observed around the 2 2gm
kink occurring at a lower gate bias and around the peak d 2 gm
appearing at a higher gate bias voltage, for both the devices. As 1 dV 2
HD3 ¼ V a2 GS ð11Þ
depicted in Figure 9e,f, in terms of IMD3, both the devices 4 6gm
show the variation with respect to temperature at lower VGS, pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
whereas no significant variation was observed at a higher VGS. T HD ¼ HD22 þ HD32 þ … ð12Þ
From Figure 9, it can be seen that the values of IIP3 are larger
than that of IMD3 for all temperatures, which ensures the where Va represents the amplitude of input sinusoidal
better linearity performance and lower distortion of the device signal and it is set down to be very small (≈50 mV).
under investigation [33]. Figure 10a–f demonstrates the variations of HD2, HD3
Furthermore, to analyse the distortion characteristics, and THD as a function of VGS at different temperatures for
second‐order harmonic distortion (HD2), third‐order har- DMDG‐TFET and DMGOSDG‐TFET, respectively. From
monic distortion (HD3) and total harmonic distortion (THD) Figure 10a,b, it can be observed that in terms of HD2, at the
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(a) (b)

(c) (d)

(e) (f)

F I G U R E 9 Variation in VIP3 with gate bias at different temperatures for (a) DMDG‐TFET (b) DMGOSDG‐TFET. Variation in IIP3 with gate bias at
different temperatures for (c) DMDG‐TFET (d) DMGOSDG‐TFET. Variation in IMD3 with gate bias at different temperatures for (e) DMDG‐TFET
(f) DMGOSDG‐TFET, at VDS = 1.0 V

lower gate bias, DMGOSDG‐TFET is more insensitive with almost temperature insensitive in addition to the lower value of
respect to temperature variation as compared to DMDG‐ HD2. As shown in Figure 10c,d, in terms of HD3, both the
TFET, whereas at the higher gate bias both the devices are devices exhibit almost same trend of temperature sensitivity
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(a) (b)

(c) (d)

(e) (f)

F I G U R E 1 0 Variation in HD2 with gate bias at different temperatures for (a) DMDG‐TFET (b) DMGOSDG‐TFET, Variation in HD3 with gate bias at
different temperatures for (c) DMDG‐TFET (d) DMGOSDG‐TFET, Variation in THD with gate bias at different temperatures for (e) DMDG‐TFET
(f) DMGOSDG‐TFET, at VDS = 1.0 V

that is HD3 is temperature sensitive around the peak occurring from THD shown in Figure10e,f, respectively. From these
at lower gate bias and around the kink occurring at higher gate results it can be viewed that both the devices are almost
bias. Overall impact of temperature variation on harmonic temperature insensitive in terms of harmonic distortion
distortion characteristics of both the devices can be viewed excluding the lower VGS range around the peak. Also, the
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