Microelectronics Journal 98 (2020) 104731

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Analog and radio-frequency performance of nanoscale SOI MOSFET for

RFIC based communication systems
Nilesh Anand Srivastava *, Anjali Priya , Ram Awadh Mishra
PARAM Lab, Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, 211004, India

A R T I C L E I N F O A B S T R A C T

Keywords: Fully-Depleted (FD) Silicon-on-Insulator (FD SOI) MOS structures have attained remarkable attention due to its
Analog/RF immunity over various short-dimension effects and lesser complexity in design as compared to other MOS
FD structures like FinFET. In this work, Dual-Metal-Insulated-Gate (DMIG) technique based FD SOI MOSFETs have
DMIG
been analyzed for the study of low power Analog/RF applications. It has been found that the proposed hetero-
FinFET
RFIC
gate-dielectric based DMIG source-engineered (HGD-DMIGSE) FD SOI MOSFET offers higher transconductance
SOI that allows higher gain and lowers the capacitive effects with broad-range of cutoff frequency as compared to
available devices at same technology node. In next, the performance of the studied MOSFET has also been
analyzed on the basis of admittance Y-parameters in order to investigate the device behaviour at higher fre-
quencies. Further, for the first time, a current-source CMOS-inverter-amplifier has been designed using proposed
HGD-DMIGSE FD SOI MOSFET. All these studies have been performed using ATLAS™ TCAD simulator.

1. Introduction structural level changes are required below 90 nm technology nodes.

Further the quantum mechanical effects need to be considered after 45
Recently, the successive growth of electronics, internet-of-things nm technology node. Also, according to the ITRS roadmap, the further
(IoT), and wireless communication have been advanced due the devel- scaling beyond 22 nm nodes requires much advance and planer tech-
opment of complementary-metal-oxide-semiconductor (CMOS) technol- nologies to overcome the scaling issues and process integration as well
ogy. These developments result in low-power and high-performance [10].
integrated circuit (IC) designs for analog and radio-frequency applica-
tions especially in the area of new generation handheld devices [1–4].
Moreover, in CMOS technology, each IC is made up of millions of MOS 1.1. Related work
transistors. So, it is the primary concern among device designers that the
available MOS technology should provide the necessary and efficient Recently, to investigate these adverse effects, numerous solutions
performance for their implementation with such low-power, wide-- have been provided in recent literatures. Various scaling challenges and
bandwidth, linear and high-speed radio-frequency-integrated-circuits related opportunities for reduction of these effects are listed in Table 1.
(RFICs) based communication systems [5,6]. As subthreshold conduction is one of the major concerns below 100 nm
In order to recognize higher performance, the scaling of MOS tran- node [8]. To overcome this, it is suggested to utilize silicon-on-insulator
sistors has been continuously taking place from two decades. However, as (SOI) substrates [9,10]. Also, as the device dimensions are shrinking
the channel length shrink, the depletion region of drain moves toward down continuously, the increased density profile are causing significant
the source and overlaps further, and results in various adverse effects. reduction in device behaviour in ON state. This could be further opti-
Due to this, in conventional MOSFETs, the endless scaling below sub-100 mized with un-doped channel concept of SOI MOSFETs [10–12]. Also,
nm nodes resulted in various short channel effects (SCEs) [7,8]. SCE is the multi-gate (double-gate, gate-all-around) concept effectively reduces
often measured as the threshold-voltage roll-off in a MOSFET [7,8]. This the DIBL effect [13]. Also, the scaling of the front-gate oxide causes the
results in off-state leakage in subthreshold regime, and hence degrades increment in quantum mechanical tunnelling of the carriers through the
the overall IC performance [8]. To overcome these issues, the various gate that result in off-state leakage in subthreshold region [14]. This
could be effectively solved with the application of multi-metal-gate

* Corresponding author.
E-mail addresses: [email protected] (N.A. Srivastava), [email protected] (A. Priya), [email protected] (R.A. Mishra).

https://doi.org/10.1016/j.mejo.2020.104731
Received 16 October 2018; Received in revised form 13 January 2020; Accepted 22 February 2020
Available online 26 February 2020
1879-2391/© 2020 Elsevier Ltd. All rights reserved.
N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

Table 1 above-discussed Section 1 composed of the recent trends and related

Scaling Challenges and technological advancement. literatures regarding the analyzed problems. Section 2 describes the de-
Scaling Challenges Technology Advancement vice structure and specification, and the desired simulation strategies and
device calibration are mentioned in Section 3. Section 4 discusses the
Subthreshold-Leakage SOI Substrates in place of Si like [9,11]
Density Profile Un-doped Channel (SOI) [9] electrical characteristics of the studied devices. Further, the analog and
Threshold-voltage roll-off/DIBL Multi-gate/Multi-metal-gates [13–18] radiofrequency performance has been taken under study in Section 5 and
Parasitic Effects Re–S/D SOI and FD SOI [10,15–18,23] Section 6 respectively. The analysis of high-frequency Y-parameter and
current source CMOS inverter amplifier using proposed n-/p-HGD-
DMIGSE FD SOI OSFET have been described in Section 7 and 8 respec-
technology, as this offers better immunity towards drain penetrations
tively. Finally, the overall finding of the work has been summarized in
electric field [15].
Section 9.
Recently, multi-gate design based recessed-source/drain (re-S/D)
structures have also been in choice among device designers to reduce the
2. Device structures and specifications
series resistance [16–18]. Further, the parasitic capacitances in nano-
scaled designs can be reduced with ultra-thin body (UTB) MOSFETs.
The two-dimensional view of the proposed HGD-DMIGSE FD SOI
Recently, the concept of UTB and ultra-thin-body-box (UTBB) has been
MOSFET ‘D4’, DMIG-SE FD SOI MOSFET-‘D3’ along with the conventional
utilized in FinFET [19,20] and fully-depleted SOI (FD SOI) MOSFETs
‘D1’ and recent state-of-art ‘D2’ [26] is shown in Fig. 1 and the specifi-
[15–18]. However, FinFET results in better scalability with complex
cations are listed in Table 2. For the comparative analysis, all the devices
structure. Moreover, nanoscaled FD SOI MOS structures solve various
have been modeled with the same parameters at channel length (L) of 50
scaling and process integration issues in much controlled manner as
nm. Moreover, the two metal gates (M1 and M2) of the devices D3 and D4
compared to other technologies, like, FinFET [15–18,21–27]. In next,
are modeled with materials Molybdenum and Titanium with work
multi-metal-gate technique in FD SOI MOSFET further improves the gate
function 4.6eV and 4.4eV respectively, and the insulator-gap is of high-k
control over the channel [15–18].
dielectric Hafnium-dioxide (HfO2) at room temperature. The length of
Further, it is necessary to comment on the device characteristics for
corresponding metal-gates (M1 and M2) and high-k gap are L1 ¼ 20 nm,
analog and radio frequency applications. Various literatures have been
L2 ¼ 20 nm and Lhigh-k ¼ 10 nm (L ¼ L1þLhigh-k þ L2). Also, the
proposed till date for the validation of these performance constraints
multi-doped source regions (Ns þ till Tsi1 ¼ 2 nm and Ns-upto Tsi2 ¼ 3–12
[1–3]. As per recent research, it has been found that the implications of
nm) are taken in both the devices D3 and D4, as shown in Fig. 1 (Tsi ¼
gate metal engineering in FD SOI MOS structures result in superior
Tsi1þTsi2). For the electrical computations, both Vg1 and Vg2 are kept
analog and radio frequency performance [3,4]. This leads to a motivation
equal in devices D3 and D4. For device-D4, the used hetero-gate-dielectric
towards the design of multi-metal gate structures in FD SOI MOSFETs for
is composed with two different gate oxide materials. In which, dielectric
its application in RFICs based systems. In multi-metal-gate technique,
materials are arranged from source to drain side as follows, HfO2 (εr ¼
different work-function metals are placed side-by-side. However, the
32)-SiO2 (εr ¼ 3.9).
process to choose compatible metals and the fabrication complexity may
increase the further challenges at nanometer node [28].
3. Simulation methodology and model calibration
Recently, the incorporation of an insulator in between two metal-
gates has been discussed that results in better short channel effect like,
These devices have been designed and simulated using numerical
DIBL [29]. This also mitigates the fabrication complexities by solving the
simulator ATLAS TCAD simulator from Silvaco [35]. For the precise
problem of compatibility in two metal gates side-by-side by placing an
analysis, all these designs have been simulated under various mathe-
insulator in between them. This dual metal insulated gate (DMIG) tech-
matical models. As for the life-time of majority carriers,
nique has also been studied in our previous work for the analysis of ring
Shockley-Read-Hall (SRH) model has been used, that corresponds to
oscillator circuit and linearity distortion assessment [30,31]. Further, to
carrier generation and recombination. In short-channel MOSFETs,
enhance the device electrostatics, numerous literatures have been re-
mobility becomes temperature dependent. For this, Lombardi mobility,
ported for the utilization of hetero-gate-dielectric (HGD) in place of
and constant voltage and temperature (CVT) model is utilized. The
single gate-dielectric. Like, Choi et al. had designed the HGD based TFET
short-channel effect also results in the higher horizontal electrical field.
and describes the significance of HGD at nanoscaled dimensions [33].
So, FLDMOB model has been taken to study the impact of the electrical
This design evidenced the suppression of abrupt ON-OFF transition and
field on the saturation velocity of the mobile charge carriers. For
enhanced ON-current by placing the high-k dielectric towards the source
current-transport switching characteristics, Gummel-Newton and
side of the channel [33]. However, till now, a less attention has been
drift-diffusion model has been chosen. Also, it is required to include
made to explore the advances of HGD in DMIG technique based source
quantum potential models at nanoscaled dimensions, since the possibil-
engineered FD SOI MOSFETs for the investigation of analog and radio
ities for conversion of particle nature of carriers in wave nature increases
frequency performance. Therefore, it is necessary to analyze the analog,
significantly. For this, BQP (Bohm-quantum-potential) model and QME
and radio-frequency behaviour of hetero-gate dielectric based DMIG
(quantum-mechanical-effect) model have also been taken for the device
source engineered (HGD-DMIGSE) FD SOI MOSFET for its application in
simulations.
analog and radio-electronics based communication systems.
Fig. 2 describes the simulation model calibration of designed FD SOI
MOSFET with extracted experimental data sets of FD SOI MOSFET [11].
1.2. Contribution Fig. 2 (a) shows the device calibration of simulated drain current char-
acteristics of 250 nm n-FD SOI MOSFET with experimental device [11] at
The proposed work aims to analyze the analog and radio frequency Vds ¼ 0.1 V. It is observed that the simulated result almost tracks the
performance of hetero-gate-dielectric based dual-metal-insulated-gate experimental data sets. Similarly, Fig. 2(b) shows the transconductance
source-engineered (HGD-DMIGSE) technique based FD SOI MOSFET. behaviour of the same device with experimental data sets of 350 nm p-FD
Also, for the first time, the HGD-DMIGSE FD SOI MOSFET based current SOI [11] at Vds ¼ 0.1 V. This analysis also signifies and validates the
source CMOS inverter amplifier is designed using mixed-mode TCAD TCAD simulation models in device design, as the simulation result affirms
simulations. It has been successfully demonstrated that the proposed the agreement between TCAD and experimental characteristics. So, these
MOS design could be utilized for high-density analog and radio- models have been taken for the design and analysis of the studied FD SOI
frequency ICs with high-gain, less linearity distortion, and wide- MOSFETs.
bandwidth. This paper has been divided into eight major sections. The

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

Fig. 1. Devices under study (a) Conventional FD SOI MOSFET-D1 (b) referenced FD SOI MOSFET-D2 [26] (c) DMIG-SE FD SOI MOSFET-D3 (d) proposed HGD-DMIGSE
FD SOI MOSFET-D4.

Table 2 length. The transfer characteristic (Id vs. Vgs) of the studied structures is
Parameters and specifications for the devices taken under study. presented in Fig. 3 (a). One can depict that the DMIG based devices D3/D4
Device Specifications Studied FD SOI MOSFETs offer higher drive current with lowest off-state leakage as compared to
device D1 and D2. This is due to the involved DMIG technique in the
Parameter Symbol Unit D1 D2 D3 D4
design of source engineered FD SOI MOSFET. Moreover, the device D2
Channel length La nm 50 50 50 50 exhibits higher On-current as compared to device D2 due to the use of
Silicon film Tsia nm 12 12 12 12
thickness
hetero-gate-dielectric. The devices D1, D2, D3 and D4 offer drive current
Front oxide Tox nm 1 1 1 1 of 0.42 mA, 1.59 mA, 2.03 mA and 2.15 mA, and off-state leakage of 3 
thickness 1012, 2.5  1012,1.25  1014 and 1.10  1014 respectively at BOX
High-k dielectric Lox- nm 50 50 50 30 oxide thickness of 5 nm. These results itself explains the significance of
length HfO2
the proposed structure in nano-scaled RFIC designs, as the leakage issue
Low-k dielectric Lox-SiO2 nm – – – 20
length is one of the critical areas of research in these ICs.
Buried-oxide TBOX nm 5–20 5–20 5–20 5–20 The buried oxide thickness (TBOX) is one of the most crucial parameter
thickness in the design of FD SOI MOS transistors to conquer the drain electric-field
Highly doped Ns þ cm3 1 1 1 1 penetrations effectively. For this, switching ratio performance with
source 1020 1020 1020 1020
Lightly doped Ns - cm 3
– 1 1 1
variation in TBOX at a fixed channel length L ¼ 50 nm for all the devices
source 1017 1017 1017 under consideration are presented in Fig. 3 (b). It is found that both the
Drain Nd þ cm3 1 1 1 1 device D4 and D3 offer Ion/Ioff ratio order of 1012 at TBOX of 20 nm, which
Concentration 1020 1020 1020 1020 is sufficient to completely suppress the off-state conduction, whereas
Substrate Doping Psub cm3 1 1 1 1
device D1 and D2 present the order of 108 and 109 respectively. This also
1016 1016 1016 1016
upholds the implication of the DMIG technique in FD SOI MOSFET at
a
For devices D3 and D4: L1 ¼ 20 nm, L2 ¼ 20 nm, Lhigh-k ¼ 10 nm (L ¼ L1þLhigh-k lower dimensions.
þ L2) and Tsi1 ¼ 2 nm, Tsi2 ¼ 10 nm (Tsi ¼ Tsi1þTsi2).
4.2. Sub-threshold conduction
4. Electrical characteristics of the FD SOI MOSFETs
The sub-threshold slope (SS) variation with channel length at
In this section, the analysis of short-channel electrical characteristics different TBOX is extracted from simulations and shown in Fig. 4 (a). It is
of the proposed FD SOI MOSFET has been taken into account for its observed that the devices D4 and D3 have lesser variability with variation
realization in ultra-low-power, and high-performance analog and radio- in BOX thickness and offer subthreshold-slope nearer to the ideal value at
frequency circuit applications. Simultaneously, the performance of the L ¼ 50 nm. This is due to the adoption of source engineering in DMIG
design has also been compared and contrasted with the conventional and technique based FD SOI MOSFETs. As the source engineering will result
available literature. in a reduction in parasitic capacitance due to change in built-in potential
of the device when an Ns-source is placed below the Ns þ source. This can
also be analyzed from Eq. (1) & Eq. (2) [36],
4.1. Drain current characteristics
Cj
The structures of studied devices (D1, D2, D3 and D4) are shown in CjBS ¼  mj (1)
Fig. 1 and their complete specifications are listed in Table 2. Fig. 3 shows 1  VVBS
bi

the electrical performance comparison of the devices at 50 nm gate

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

Fig. 2. (a) Drain current vs. gate voltage plot for model calibration of 250 nm simulated FD SOI with extracted data sets of experimental n-FD SOI [11] (b) similarly
transconductance behaviour for model calibration with experimental 350 nm p-FD SOI [11].

Fig. 3. (a) Transfer characteristics (log Id vs. Vgs) (b) Switching ratio (Ion/Ioff) performance with variation in TBOX at L ¼ 50 nm and Vds ¼ 1 V of the devices D1:
Conventional FD SOI, D2: FD SOI [26], D3: DMIG-SE FD SOI and D4: proposed HGD-DMIGSE FD SOI.

Fig. 4. (a) Sub-threshold slope (SS) variation with channel length at different BOX oxide thickness (TBOX) (b) Threshold voltage roll-off with variation in chan-
nel length.

where, CjBS & Cj are the source to bulk parasitic capacitance and junc- Threshold voltage (Vth) roll-off is also regarded as the short dimension
effect in nanostructures. Fig. 4 (b) shows the threshold voltage roll-off for
tion capacitance respectively, and built-in-potential (Vbi ) is written as,
variation in channel length at the drain supply voltage of 0.1 V for all the
NA ND devices taken into consideration. It is found that the DMIG-based devices
Vbi ¼ VT ln (2)
n2i D3 and D4 offer very less roll-off even at 20 nm channel length as
compared to other devices.
where, VT is the thermal potential, and NA ; ND & ni are the body doping So, DMIG technique along with source engineering in FD SOI MOS-
level, source diffusion region doping level and intrinsic concentration FET excels the device performance significantly. Further to verify the
respectively. results obtained above, a brief discussion over the surface potential

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

profile of DMIG based devices has also been taken into consideration. function of effective gate-voltage and calculated using Eq. (3) & Eq. (4).
Fig. 5 shows the surface potential profile (SPP) variation along the Higher the transconductance-higher the carrier transport efficiency and
channel for DMIG-SE and HGD-DMIGSE FD SOI MOSFETs. It has been hence improved gain of an amplifier. Moreover, TGF describes the drive
found that the location of the SPP minima is moved more along the current behaviour that in turn gives the effectiveness of transconductance
source side of the channel due to the inclusion of HfO2 gap in between and also represents the linearity behaviour. One can find from Fig. 6(a)
two metal gates in case of both the devices. This step-like function profile and (b) that the devices D3 and D4 have optimum transconductance value
clearly indicates that the weak inversion is taking place at the source side among all in accord with best TGF value in weak inversion region as
of the channel. This will result in more uniform electric field in the compared conventional FD SOI and state-of-the-art [26]. This higher TGF
channel area as the electric field peak will be located towards the source value nearer to ideal value (q/kT ¼ 38 V1) in weak inversion itself
end. Moreover, the corresponding value of minima position is shifted explains the performance of the studied device D3 and D4. As, the higher
more nearer to the source in case of HGD-DMIGSE FD SOI MOSFET. This value of TGF is required for low power analog ICs for less linearity
is due to involved hetero-dielectric technique in the design of DMIG-SE distortion and for better thermal stability. This is due to the minimized
FD SOI MOSFET, as hetero-dielectric will further control and restrict surface roughness and coulomb impurity scattering because of reduced
the tunnelling behaviour of the device in subthreshold region. This type fabrication complexity due the inclusion of high-K gap in between two
of performance shows that the device will offer less variable drive current metal gates [28]. Moreover, proposed device D4 results better among all
(Ion) and suppressed sub-threshold conduction (Ioff). the devices taken under study. Since, the utilization of
Table 3 represents the electrical performance comparison of recently hetero-gate-dielectric will enhance the on-current behaviour of the de-
proposed literature of MOS transistors at the same technology node. The vice and hence improved transconductance.
DMIG based FD SOI MOSFETs offer excellent switching performance at Fig. 7 shows the plot of output conductance versus drain to source
Vds ¼ 1 V. These remarkable features make it a suitable candidate for the voltage at the constant gate to source voltage of 1 V. This has been
design of low power and high-performance ICs. Moreover, these pro- extracted from Eq. (5). It is clear from the characteristics that gd starts
posed solutions towards the performance enhancement in the nanometer decreasing as drain bias applied and it has been found that the output
era of device scaling need precise description and justification for its conductance is lowered for device D4 followed by device D1, D2 and D3,
realization in the real world. Especially in order to utilize these devices in and maintained constant after Vds ¼ 0.2 V and 0.19 V for devices D3 and
the design of RFIC based communication systems; it is necessary that the D4 respectively. The sufficient decrement in output transconductance
devices must offer larger gain, high-linearity, and wide frequency range. will result in a high gain for the DMIG based devices. The devices D3 and
For this, the analog and radio frequency performance of the studied de- D4 attain high gain because of higher output resistance due to DMIG
vices is discussed in Section 5 and Section 6 respectively. concept as compare to conventional SOI devices D1 and D2. This feature
will also result in suppression of small dimension effects like DIBL and
5. Analog performance channel length modulation.

The analog performance of a device depends on its input trans- VEA ¼ ID=g (6)
d
conductance (gm), output conductance (gd), intrinsic gain (Av), trans-
The characteristic of early voltage (VEA) with variation in Vgs for the
conductance generation factor (TGF) and early voltage. Here, these
studied structures is modeled using Eq. (6), and the corresponding result
parameters are extensively analyzed.
is shown in Fig. 8. The VEA variation is changing from Vgs ¼ 0.2 V and
∂ID starts increasing and calculated maximum for the device D4 followed by
gm ¼ (3)
∂VGS D1, D2 and D3. So, the DMIG based devices result in higher VEA at higher
Vgs and hence better analog performance. Also, it proves that the output
TGF ¼ gm=I (4) conductance results as VEA is inversely proportional to gd. It is also worth
D
here to mention that the adoption of hetero-gate-dielectric in DMIG
significantly improves the device performance due to its high Ion and gm
∂ID
gd ¼ (5) that single-gate-dielectric.
∂VDS Also, the computation of intrinsic gain (Av) is essential here for the
Fig. 6(a) and (b) show the plot of transconductance and TGF as a application of the studied devices as OTAs (Operational-trans-
conductance-amplifiers). It is calculated as the ratio of input trans-
conductance to output conductance (Av¼gm/gd), and the corresponding
analysis is presented in Fig. 9. The intrinsic gain variation with Vgs results
in an increment of Av as Vgs>0. Moreover, the DMIG technique and HGD
technique based devices D3 and D4 attain higher intrinsic gain due to the
reduction in effective gate overlap capacitances as compared to devices
D1 and D2. The resulting gain of device D4 is around 10% higher than the
device D3. So, it is advantageous to utilize the hetero-gate-dielectric in
DMIG-SE FD SOI MOSFET. For the accurate analysis, the performance
parameters are listed in Table 4.

6. Radio-frequency performance

For RF or high-frequency circuit applications, the main parameters

like gate overlap capacitances (Cgs and Cgd) and transition/cut-off fre-
quency need to be discussed. For this, AC simulations have been per-
formed using ATLAS Silvaco numerical simulator. The DC voltage of 1 V
with the step of .001 V at 1 MHz frequency has been applied for AC small
signal analysis. The characteristics of overlap capacitances are shown in
Fig. 10. From Fig. 10, the gate to source capacitances starts increasing
Fig. 5. Surface potential profile along the channel of studied DMIG-based
from weak inversion as Vgs is applied, for all the FD SOI based devices
MOS structures.

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

Table 3
Comparison of electrical performance of various short-dimension MOS structures.
Ref. Device L(nm) Ion(mA) Ioff(A) Vth(V) Tox(nm) SS (mv/decade) Ion/Ioff
12
[22] FD SOI 50 0.10 1  10 0.30 1 60 108
[19] FinFET 50 1.0 10  1012 0.27 2 78 108
[32] AM-CGAA 50 .006 – 0.28 2 60 105
[25] FD SOI 50 0.08 5  1012 0.32 2 – 108
[26] FD SOI 50 0.10 0.8  1015 0.38 1 57 109
[27] FD SOI 50 3.0 80  1015 0.30 1 60 1010
This work DMIG-SE FD SOI 50 2.03 0.12  1015 0.40 1 62 1011
HGD-DMIGSE FD SOI 50 2.15 0.10  1015 0.40 1 61 1011

Fig. 6. (a) Plot of input transconductance vs. gate voltage (b) TGF vs. gate voltage at Vds ¼ 0.1 V for the devices under study.

Fig. 7. Plot of output conductance vs. drain to source voltage at constant Vgs of
1V
Fig. 9. Characteristics of Intrinsic gain with variation in gate voltage.

Table 4
Analog Performance of the device taken into consideration.
Device gm (S) gd (S) VEA (V) TGF (V1) Av (dB)
3 4
D1 3.99  10 1.33  10 6.93 33.79 44.72
D2 4.23  103 8.24  105 8.32 33.94 43.32
D3 5.02  103 3.96  105 16.66 34.08 78.49
D4 5.98  103 3.26  105 18.72 36.12 84.12

taken under study. This is due to the effect of the longitudinal electric
field and hence fringing effects. Moreover, in strong inversion, the Cgs
remains lower for the proposed device-D4 HGD-DMIGSE, even though
with further increment in gate bias as compared to other devices studied
here. Similar performance is also observed in case of device D3. This
represents the minimized effects of drain electric-field penetrations due
to the inclusion of high-k in between the two metal gates and utilization of
hetero-dielectric. The same results have also been concluded from Fig. 10
Fig. 8. Characteristics of Early voltage with variation in gate voltage at Vds ¼ for the characteristics of Cgd versus Vgs. As, the devices D3 and D4 offer
0.1 V minimum parasitic capacitance for Cgd variation with Vgs from 0 to 1 V as

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

gm
TFP ¼  fT (9)
ID

gm gm
GTFP ¼   fT (10)
gd ID
It is clear from GFP plot that the DMIG enabled devices offer excellent
performance among the studied MOSFETs. The transconductance-
frequency product (TFP) at different gate voltage is shown in Fig. 12
(b). TFP is the measure of collective performance of a device in regards to
switching frequency and power dissipation. One can also conclude the
same from Eq. (9). As per Fig. 12 (b), TFP starts increasing for all the
MOSFETs taken under study and attains maximum value at 0.40 V, 0.35
V, 0.35 V and 0.35 V for the devices D1, D2, D3 and D4 respectively. Since,
the transconductance of the proposed HGD-DMIGSE FD SOI is the best
among all, the proposed MOSFET results as a better alternative in the
Fig. 10. Gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) vs. design of nanoscaled RF circuit and systems.
Vgs at Vds ¼ 0.1 V Moreover, gain-transconductance-frequency product (GTFP) is the
unique FOM of the device, which describes the device performance with
compared to conventional-D1 and state-of-the-art-D2. trade-off among gain, speed, and power. The calculation of GTFP has
been carried out using Eq. (10). Fig. 12 (c) shows the GTFP variation with
gm
fT ¼
(7) different Vgs. It is clear from the plot that the devices D3 and D4 resemble
2π Cgs þ Cgd
significant performance at lower Vgs with a peak of 1.42  1015 Hz/V at
Further, unity gain transition frequency (fT ) is taken under study. The Vgs ¼ 0.4 V and 1.76  1015 Hz/V at Vgs ¼ 0.47 V respectively.
fT is desired for determination of allowable bandwidth in RFICs. The The values of different RF performance parameters are listed in
calculation of fT is done as per Eq. (7). The plot of fT with respect to Vgs is Table 5. It is clear from Table 5 that the DMIG enables devices D3 and D4
shown in Fig. 11. The value of fT mainly depends on the input trans- offer better radio-frequency performance as compared to other devices
conductance and overlap capacitances. Already, it has been discussed taken under study. So, these devices could be suggested for the radio-
that the immunity of DMIG based devices over other studied devices are frequency-integrated-circuits (RFICs) in radioelectronics based commu-
better, the same has also been proved here. As the devices D3 and D4 are nication systems.
offering the highest unity gain frequency than other studied devices. This The above discussion itself explains that the incorporation of DMIG
is due to the characteristics of Cgs and Cgd. structure excels the performance of the device at the nanometer node.
DMIG technique offers higher immunity towards small dimension effects
and excellent performance at low power with drive current stability and
6.1. Figure-of-merits of radioelectronics low off-state leakage. Also, the inclusion of hetero-dielectric in DMIG
MOSFET has further improved the DC characteristics of the device. These
The different radio-frequency performance figure-of-merits has also devices also offer significant analog and radiofrequency performance. So,
been calculated here and plotted in Fig. 12. The gain-frequency product the hetero-dielectric and DMIG based source engineered FD SOI structure
(GFP) with variation in Vgs is shown in Fig. 12 (a). GFP describes the could be suggested for low-power analog and RFIC designs.
device performance as a trade-off between the frequency and the intrinsic
gain. For example, if low-frequency operation is required then one can 7. High-frequency performance investigation of HGD-DMIGSE FD
use it with high gain of constant GFP else the device can operate at high- SOI MOSFET using Y-parameters
frequency with less compromise in gain. The GFP is calculated as per Eq.
(8). In this section, Y-parameter analysis of proposed HGD-DMIGSE FD SOI
MOSFET has been carried out in order to monitor the high-frequency of
gm
GFP ¼  fT (8) the studied device. Since, at high frequencies, it is a trivial task to
gd compute nodal voltages and current for circuit analysis. So, it is conve-
nient to analyze the small signal parameter methods (Y, Z, S, and h) [31].
Here, the Y-parameters (Y11, Y12, Y21, Y22) have been investigated on the
basis TCAD simulations [35] upto 1 THz in the similar manner as sug-
gested in Ref. [34].
The plot of short-circuit input (Y11) and output admittance (Y22) at
different frequency range is shown in Fig. 13(a) and (b) for proposed
hetero-gate dielectric based HGD-DMIGSE FD SOI MOSFET and compared
against DMIG-SE MOSFET. It is clear from the plot that the studied de-
vices offer comparable performance with lesser values of Y11 and Y22
upto 1 THz range. Moreover, the HGD-DMIGSE exhibits lesser value of Y11
as well as Y22. Similarly, extraction of short-circuit forward (Y12) and
reverse transfer-admittance (Y21) is shown in Fig. 13(c) and (d). It is
evident from the plots that the HGD-DMIGSE based MOS structure results
in higher value of Y21 and Y21. It is desired that a device should offer
lesser value of Y11/Y22 and higher value of Y12/Y21. So, the above
analysis validates that the device could also be proposed for high-
frequency applications. Hence, these novel features of proposed HGD-
DMIGSE FD SOI MOSFET motivate to further analyze the circuit-level
Fig. 11. Unity gain transition frequency fT as a function of gate voltage at Vds ¼ behaviour of the device. For this, in the next section, for the first time,
0.1 V

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

Fig. 12. (a) Gain Frequency Product (GFP) (b) Transconductance-Frequency Product (TFP) (c) Gain-Transconductance-Frequency Product (GTFP) with variation in
gate voltage at Vds ¼ 0.1 V

Table 5 the active load at output node [34]. Here, for the analysis, the fixed gate
RF Performance of the device taken into consideration at Vds ¼ 0.1 V and Vgs ¼ 1 length of 50 nm is taken for n-/p-HGD-DMIGSE MOSFETs and the varia-
V tion in gain is analyzed at different Vb. The proposed MOSFET based
Device Cgs(F) Cgd(F) f T (Hz) GFP(Hz) TFP(Hz/ GTFP(Hz/ circuit is being designed and analyzed using mixed mode simulation
V) V) platform of TCAD simulator [35]. Fig. 14(b) and (c) shows the threshold
D1 6.23  2.96  1.17  5.30  3.35  1.50  voltage and Id vs. Vgs characteristics of both n-/p-HGD-DMIGSE FD SOI
1016 1015 1011 1012 1011 1013 MOSFETs. As shown in figure, the approximately similar threshold
D2 5.58  2.84  1.97  1.01  6.20  1.84  voltage and drive current of 2.1 mA is observed in case of both
1016 1015 1011 1013 1011 1013
n-/p-HGD-DMIGSE MOSFETs. The voltage-transfer-characteristics (VTC)
D3 5.22  9.18  6.35  7.99  7.75  5.13 
1016 1016 1011 1013 1011 1013 of n-/p-HGD-DMIGSE based CS amplifier at supply voltage (Vdd ¼ 1 V)
D4 5.10  8.07  7.22  1.32  8.63  1.58  and different bias conditions (Vb¼0.5 V–1 V) is shown in Fig. 15 (a). It is
1016 1016 1011 1014 1011 1014 being observed, as the Vb is increased from 0.5 V to 1 V, the VTC curve of
CS amplifier resembles near to 0 V point in Vin and 0.5 V in Vout.
Further, the slope of this VTC curve in transition region is taken to
studied device based current source CMOS inverter amplifier is designed
measure the voltage gain of n-/p-HGD-DMIGSE MOSFET based CS
for low power radiofrequency analog applications.
amplifier in the similar manner as discussed in Ref. [34]. The plot of
voltage gain of designed HGD-DMIGSE MOSFETs based CS amplifier with
8. HGD-DMIGSE FD SOI MOSFET-based current source CMOS
variation in bias voltage condition is shown in Fig. 15 (b) and compared
inverter amplifier
with DMIG-SE MOSFET. It is clear from the plot that as the Vb is increased
from the 0.5 V–1 V, the voltage gain of the amplifier is enhanced and
This section represents the design and analysis of n-/p-HGD-DMIGSE
results in better voltage gain of 18 for proposed hetero-dielectric based
FD SOI MOSFET-based current source CMOS inverter amplifier for
DMIG MOSFET. This is due to the adopted dielectric engineering and
analog applications. Fig. 14 (a) shows the configuration of single stage
metal-gate technology in the design of HGD-DMIGSE FD SOI MOSFET.
current source CMOS inverter amplifier, in which the nMOSSE HGD-DMIG is
working as a driver transistor and pMOSSE HGD-DMIG as a active current
9. Conclusion
source load. Here, the bias voltage (Vb) is varied to control the voltage
gain of the common source (CS) stage amplifier. Moreover, as per the CS
This paper presents a novel approach for performance enhancement
amplifier gain formula fAv ¼  gm1 ðr01 =r02 Þg, the output resistance r01
of SOI MOSFETs for low power analog and radioelectronics applications.
of the load may be increased for increment in amplifier gain. This could
For this, first, the impact of hetero-gate-dielectric based DMIG DMIG-SE
be achieved by increasing the length and width of pMOSSE HGD-DMIG current
FD SOI MOSFET is analyzed and simultaneously being compared and
source load, However, the penalty is the larger capacitance introduced by

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

Fig. 13. Extraction of small-signal Y-parameters with variation in frequency for the devices D3 and D4 (a) Re(Y11)/Im(Y11) (b) Re(Y22)/Im(Y22) (c) Re(Y12)/Im(Y12)
(a) Re(Y21)/Im(Y21).

Fig. 14. (a) Circuit diagram of n-/p-HGD-DMIGSE FD SOI-based CS CMOS inverter Amplifier (b) threshold voltage characteristics with variation in channel length (c)
Id vs. Vgs plot of n-/p-HGD-DMIGSE FD SOI MOSFET.

Fig. 15. (a) VTC curve of designed CS CMOS amplifier using n-/p-HGD-DMIGSE FD SOI at different Vb (b) comparison of extracted amplifier gain with variation in Vb
for DMIG-SE and HGD-DMIGSE FD SOI MOSFETs.

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N.A. Srivastava et al. Microelectronics Journal 98 (2020) 104731

contrasted with the recent literature. The proposed HGD-DMIGSE based [6] R. Chaujar, R. Kaur, M. Saxena, M. Gupta, Intermodulation distortion and linearity
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