Application Note

Power Devices

PCB Layout Thermal Design Guide

Thermal design is not only important in designing power circuits, but also an important element in designing the PCB. If an issue
occurs after the design is completed, it requires more time and cost to make a modification. Therefore, it is necessary to perform
the thermal design from the initial phase of the PCB design as well. This application note provides some key points on how to
reduce thermal resistance in designing the PCB.

From here, we change the parameters of each PCB element

150
and check changes in the thermal resistance. The measured
value of each thermal resistance is listed for a 1-, 2-, or 4-layer
PCB that complies with the JEDEC standard JESD51. 100
θJA (°C/W) HTSOP-J8
Subsequently, after confirming consistency between the
measured values as mentioned above and simulations,
50
simulated values are listed for the PCB that are not in
accordance with the JEDEC standard. TO252-3

0
Since the thermal resistance values depend on the PCB 0 200 400 600 800 1000 1200
material, layout, parts configuration, chassis shape, Top Layer Copper Foil Area (mm2)
surrounding environment, and so on, they may not always be
Figure 1. Thermal resistance with varied copper foil areas of
consistent with the values of actual equipment. Therefore,
the 1-layer board
refer to trends of change in the thermal resistance, rather than
the absolute values.
HTSOP-J8
Copper foil area
Figure 1 shows the thermal resistance for the 1-layer board
with varied copper foil areas. PCB layouts with different copper
foil areas are shown in Figure 2. The thermal resistance is
decreased as the copper foil area for heat dissipation is
increased. However, the effect obtained may not be 15.7 mm2 100 mm2 600 mm2 1200 mm2
(Footprint)
proportionate to the area if it is expanded beyond a certain
extent. Figure 3 is a contour diagram showing that the area of TO252-3
the same temperature is increased as the distance from the
heat source is increased. This indicates reduction in the heat
dissipation effect.

49 mm2 300 mm2 600 mm2 1200 mm2

(Footprint)

Figure 2. Layout of the 1-layer PCB

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PCB Layout Thermal Design Guide Application Note

HTSOP-J8 nearest copper foil for heat dissipation, the shorter the
distance along the via, reducing the thermal resistance. Since
this distance is even shorter in the 6- and 8-layer boards, the
thermal resistance is decreased correspondingly.

110
100 HTSOP-J8 package
90 2 layers
80 4 layers
70 6 layers

θJA (°C/W)
8 layers
60
50
40
TO252-3 30
20
10
0
0 1000 2000 3000 4000 5000 6000
Each Layer Copper Foil Area (mm2)

Figure 4. Thermal resistance for the multi-layer boards with

varied copper foil areas except for the top layer

2-layer board
Top layer Bottom layer

Figure 3. Contour diagram for the 1-layer board

Next, look at the change in thermal resistance for the multi-

layer boards. Figure 4 shows the thermal resistance when the
copper foil area is varied. Figure 5 shows the layouts of the 2-
15.7 mm2
and 4-layer boards as typical examples. The layouts of the 6- (Footprint) 100 mm2 1200 mm2 5505 mm2

and 8-layer boards correspond to that of the 4-layer board. As

with the vertical structure shown in Figure 6, a thermal via 4-layer board
penetrates from the top to bottom layers. Depending on the Top layer Middle layer connected with via, bottom layer
number of layers, the middle layers may or may not be
connected with the thermal via. Refer to the respective
diagrams.

As is the case for the change in thermal resistance for the 1-

layer board, the thermal resistance for the multi-layer boards
is decreased as the copper foil area for heat dissipation is 15.7 mm2
(Footprint) 100 mm2 1200 mm2 5505 mm2
increased. However, the effect obtained may not be
proportionate to the area if it is expanded beyond a certain Middle layer isolated from via
extent.

A significant difference in the thermal resistances is observed

between the 2- and 4-layer boards. As can be seen in their
vertical structures (Figure 6), the heat is transmitted from the
heat source to the bottom layer through a via of 1.6 mm in
length in the 2-layer board. In contrast, a large amount of heat
100 mm2 1200 mm2 5505 mm2
is transmitted from the heat source to middle layer 1 over a
shorter distance along the via in the 4-layer board. In other Figure 5. Layout of a multi-layer PCB
words, the shorter the distance from the heat source to the

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PCB Layout Thermal Design Guide Application Note

2-layer board 4-layer board

Top layer Middle layer1 Middle layer2
via
Top layer, 70μm

Bottom layer, 70μm

t = 1.6mm

4-layer board 15.7 mm2

(Footprint) 5505 mm2 5505 mm2
via
Top layer, 70μm Signal layer
Bottom layer
Middle layer 1, 35μm Power plane (ground)

Middle layer 2, 35μm Power plane (power)

Bottom layer, 70μm Signal layer

t = 1.6mm
Insulation distance 0.6mm

6-layer board

via
Top layer, 70μm Signal layer
Middle layer 1, 35μm Power plane (ground) 100 mm2 1200 mm2 5505 mm2
Middle layer 2, 35μm Signal layer
Middle layer 3, 35μm Signal layer Figure 7. Layout of the 4-layer PCB with varied copper foil
Middle layer 4, 35μm Power plane (power) areas only for the bottom layer
Bottom layer, 70μm Signal layer
t = 1.6mm
Insulation distance 0.6mm

110
8-layer board 100
90
via
Top layer, 70μm Signal layer 80
Middle layer 1, 35μm Power plane (ground) 70
θJA (°C/W)

Middle layer 2, 35μm Signal layer

Middle layer 3, 35μm Power plane (power) 60
Middle layer 4, 35μm Signal layer 50
Middle layer 5, 35μm Signal layer
Middle layer 6, 35μm Power plane (ground) 40
Bottom layer, 70μm Signal layer
30
t = 1.6mm
Insulation distance 0.6mm 20
10
Figure 6. Vertical structure of a multi-layer PCB
0
0 1000 2000 3000 4000 5000 6000
Bottom Layer Copper Foil Area (mm2)
Now look at how a large amount of heat is transmitted from
the heat source to the nearest copper foil for heat dissipation. Figure 8. Thermal resistance when the copper foil area is
As shown in Figure 7, use a 4-layer board and lay out a large varied only for the bottom layer in a case where the heat can
copper foil area of 5,505 mm2 only for middle layers 1 and 2.
be sufficiently dissipated in the layer close to the heat source
However, middle layer 2 is not connected with the via. Figure
in the 4-layer board
8 shows the thermal resistance when the copper foil area of
the bottom layer is varied in this situation. As can be seen in
the figure, if the heat can be sufficiently dissipated in a layer
closer to the heat source, only a small effect can be obtained
by securing a larger copper foil area in a layer farther from the
heat source.

Thus, the thermal resistance can be efficiently reduced by

preferentially increasing the copper foil area of layers closer to
the heat source.

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PCB Layout Thermal Design Guide Application Note

Board thickness thermal resistance, increase the board thickness. Figure 10

shows how the heat is conducted with varied board thickness.
Figure 9 shows the thermal resistance for the 1-layer board
This indicates that the heat is conducted farther in a thicker
with varied board thickness (refer to Figure 2 for the PCB). The
board.
vertical axis indicates the rate of change taking the thermal
resistance with a board thickness of 1.6 mm as a reference In Figure 9, the change in thermal resistance against the board
(zero). thickness is reduced in a larger copper foil area of the top layer.
This is because the precedence of the thermal conduction to
The thermal resistance tends to be smaller when the board
the copper foil is increased as the copper foil area is increased,
thickness is larger. In the 1-layer board, the heat cannot be
reducing the relative influence of the board thickness on the
efficiently dissipated through the vertical thermal conduction,
thermal resistance.
because the air layer on the bottom surface has a small
thermal conductivity. Therefore, the horizontal thermal
conduction takes precedence. To reduce the horizontal

HTSOP-J8 TO252-3

20 Thermal Resistance Change Rate (%) 30

Thermal Resistance Change Rate (%)

Top layer copper foil area (mm2) Top layer copper foil area (mm2)
25 49
15.7
15 100
20

10 15 300

600 600
10
5 1200 1200
5

0 0
0.6 0.8 1 1.2 1.4 1.6 0.6 0.8 1 1.2 1.4 1.6
PCB Thickness (mm) PCB Thickness (mm)

Figure 9. Thermal resistance for the 1-layer board with varied board thickness

Heat source
1.6mm

FR4
Low Rth Low Rth

Heat source
0.8mm
FR4
High Rth High Rth

Figure 10. Thermal conduction with varied board thickness in the 1-layer board
(HTSOP-J8, copper foil area of the top layer is 15.7 mm2, both heat sources at the same temperature)

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PCB Layout Thermal Design Guide Application Note

Figure 11 shows the thermal resistance for the 2-layer board Therefore, thermal resistance tends to be smaller when the
layout with varied board thickness, where the heat source is distance along the via is shorter (the thermal resistance along
connected to the copper foil of the bottom layer through a the via is lower), i.e., the board thickness is smaller.
thermal via (refer to Figures 5 and 6 for the PCB). The vertical
The horizontal thermal conduction takes precedence with a
axis indicates the rate of change taking the thermal resistance
smaller copper foil area, whereas the vertical thermal
with a board thickness of 1.6 mm as a reference.
conduction takes precedence with a larger copper foil area.
As is the case for the 1-layer board, the thermal resistance This boundary depends on the PCB conditions.
tends to be smaller when the board thickness is larger,
Figure 12 shows how the heat is conducted with varied board
because the thermal conduction to the board is relatively
thickness. This indicates that the vertical thermal conduction
larger with a smaller copper foil area.
is more effective with a smaller board thickness if a sufficient
As the copper foil area is increased, the thermal conduction to copper foil area for heat dissipation is available in the bottom
the copper foil through the via is relatively increased. layer.

HTSOP-J8 TO252-3

20 30
Thermal Resistance Change Rate (%)

Thermal Resistance Change Rate (%)

Bottom layer copper foil area (mm2)
Bottom layer copper foil area (mm2)
15 25
100
100
20
10
300
15
300
5 600
10
0 600
1200
5
1200
-5 0
5505 5505
-10 -5
0.6 0.8 1 1.2 1.4 1.6 0.6 0.8 1 1.2 1.4 1.6
PCB Thickness (mm) PCB Thickness (mm)

Figure 11. Thermal resistance for the 2-layer board with varied board thickness

Heat source
1.6mm

High Rth FR4

Heat source
0.8mm

Low Rth FR4

Figure 12. Thermal conduction with varied board thickness in the 2-layer board
(HTSOP-J8, copper foil area of the bottom layer is 5,505 mm2, both heat sources with the same power loss)

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PCB Layout Thermal Design Guide Application Note

Number of layers Table 1. Typical layer assignments

Figure 13 shows the thermal resistance with varied numbers Layer assignment
Layer
2-layer PCB 4-layer PCB 6-layer PCB 8-layer PCB
of layers (refer to Figures 5 and 6 for the PCB). The thermal L1
Wiring Wiring Wiring Wiring
resistance tends to be lower with a larger number of layers. (Top)

This reduction in the thermal resistance is due to the increase Ground Ground Ground
L2 Wiring
plane plane plane
in the copper foil area for the thermal conduction and, as
Power
L3 Wiring Wiring
described in the section for “Copper foil area”, the decrease in plane
the distance from the heat source to the nearest middle layer Power
L4 Wiring Wiring
plane
copper foil (plane) as the number of layers is increased with
Power
the same board thickness based on the vertical structure L5 Wiring
plane
(Figure 6).
L6 Wiring Wiring
Table 1 shows typical assignments of the layers. From the EMI Ground
L7
aspect, the plane layers with a low electric impedance (ground Plane

or power supply) are generally placed adjacent to all the wiring L8 Wiring
layers. This configuration is also very effective for the thermal
design, because the heat can be efficiently conducted from the
For example, the thermal conduction is not optimum even with
heat source on the top layer (L1 here) to plane L2, which is the an 8-layer board if the heat source on the top layer is not
middle layer directly below the top layer. connected with the middle layers through the via and a large
copper foil area is provided in the bottom layer (L8 here),
HTSOP-J8 because the vertical thermal resistance along the via is
increased. In this case, the thermal resistance can be reduced
100 to a certain extent by increasing the copper foil thickness of
Middle and Bottom layer
90 the bottom layer.
copper foil area (mm2)
80
70 In the multi-layer boards, the thermal resistance can be
300
efficiently lowered by placing a larger copper foil area for heat
θJA (°C/W)

60
50 600 dissipation on the same layer as the heat source or the
40
1200 adjacent layer.
2000
30 5505
Figure 14 shows the thermal resistance for the 8-layer board
20
when a heat dissipation plane is placed only on a certain layer.
10
It can be seen that the thermal resistance is higher as the
0
distance from the heat source on L1 is increased.
12 2
4 63 4
8 5
Number of Layers

TO252-3 55
HTSOP-J8
80
Middle and Bottom layer
50
70 copper foil area (mm2)
θJA (°C/W)

60
300 45
θJA (°C/W)

50

40 600
40 L8 only
30 1200
2000 L7 only
L8 only, 70μm
20 5505 L2 only
35
10 1000 2000 3000 4000 5000 6000
Copper Foil Area (mm2)
0
12 2
4 63 4
8 5
Number of Layers Figure 14. Change in thermal resistance for the 8-layer board
when a heat dissipation plane is placed only on a certain
Figure 13. Thermal resistance with varied numbers of layers layer (copper foil thickness is 35 µm unless otherwise
specified)

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PCB Layout Thermal Design Guide Application Note

Copper foil thickness HTSOP-J8

Figure 15 shows the trend in the thermal resistance with varied 70

Thermal Resistance Change Rate (%)

60
copper foil thickness. The thicker the copper foil, the lower the 2-layer PCB
50
thermal resistance. This is because the thermal resistance of
40
the copper foil itself, which provides the heat conduction path, 1-layer PCB
30
is decreased.
20
10
In this figure, the variation rate is shown taking the thermal
0
resistance with the copper foil thickness of 70 µm as a
-10 4-layer PCB
reference (zero). The copper foil thickness of the top and
-20
bottom layers is varied, while that of the middle layers is fixed
-30
at 35 µm. The variation rate depends on the number of layers 0 20 40 60 80 100 120 140 160 180
Top and Bottom Layer Copper Foil Thickness (µm)
in the PCB. However, this should be considered as only an
example because it depends on the PCB configuration, such
TO252-3
as the copper foil area.
70
The PCB layouts for this figure are shown in Figures 2, 5, and
Thermal Resistance Change Rate (%) 60
2-layer PCB
6. The copper foil area is footprint size only for the top layer 50
and 5,505 mm2 for the middle and bottom layers. 40
30 4-layer PCB
The effect of the copper foil thickness appears to be small for
20
the 1-layer PCB, because of its small copper foil area with 10
footprint size only. Figure 16 shows the result of increasing the 0
copper foil area to 1,200 mm2. It can be seen that the relative -10 1-layer PCB

influence of the copper foil thickness is increased as the -20

thermal conduction to the copper foil is increased. -30

0 20 40 60 80 100 120 140 160 180
Top and Bottom Layer Copper Foil Thickness (µm)
A larger variation rate in the 2-layer PCB is a result of the
larger relative influence of the copper foil thickness, because Figure 15. Thermal resistance with varied copper foil
the main thermal conduction path is the copper foil of the thickness
bottom layer.

In the 4-layer PCB, the relative influence of the copper foil 70

TO252-3
Thermal Resistance Change Rate (%)

60
thickness of the bottom layer appears to be smaller, because
50
the thermal conduction to the middle layers is larger.
40 1-layer PCB
1200mm2
In any case, the thicker the copper foil, the lower the thermal 30

resistance. 20
10
0
-10
1-layer PCB
-20
Footprint (49mm2)
-30
0 20 40 60 80 100 120 140 160 180
Top and Bottom Layer Copper Foil Thickness (µm)

Figure 16. Rate of variation in the thermal resistance when

the copper foil area is 1,200 mm2 in the 1-layer PCB of
TO252-3

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PCB Layout Thermal Design Guide Application Note

Thermal via 70

Figure 17 shows the change in thermal resistance with the 2-layer PCB
60

θJA (°C/W)
number of thermal vias in the PCB on which the HTSOP-J8 50
package is mounted. The larger the number of vias, the lower
40
the thermal resistance. However, it can be seen that only one 4-layer PCB
30
via has a large effect.
G I J
VIA Layout Drawing
If a via is placed directly under the exposed pad, solder may
be sucked into the via during the reflow process, reducing the G. 3 × 4 I. Stencil J. Placed
around the
fusion ratio. Countermeasures against this issue include exposed pad
designing stencils (metal masks) away from the vias and
placing the vias on the periphery and away from the exposed
pad. Figure 18 shows the changes in thermal resistance with
the respective countermeasures. When the stencil is
engineered (I), the thermal resistance is only slightly increased.
However, when the vias are placed around the exposed pad represents solder on the exposed pad area.

(J), the thermal resistance component of the copper foil is

Figure 18. Change in the thermal resistance with the
added because the heat is first transmitted through the copper
countermeasures against solder being sucked into the vias
foil and then reaches the via. Therefore, since the effect of
thermal vias is decreased as they are separated from the heat
source, place them directly under the heat source as much as
possible.

100

90 2-layer PCB

80
θJA (°C/W)

70

60
4-layer PCB
50

40

30
A B C D E F G H
VIA Layout Drawing

A. No via B. 1 via C. 2 vias D. 4 vias E. 6 vias F. 8 vias G. 12 vias H. 18 vias

represents solder on the exposed pad area.

Figure 17. Change in the thermal resistance with the number of vias
HTSOP-J8 package, via diameter 0.3 mm

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PCB Layout Thermal Design Guide Application Note

Figure 19 shows the thermal resistance with varied via

diameters. The larger the via diameter, the lower the thermal
resistance. This is because of a decrease in the thermal
resistance of the via itself, which provides the heat conduction
path.

In this example, the vias are placed on the same positions for
different via diameters to check their effect. In reality, vias with
a smaller diameter can be placed at narrower pitches.
Therefore, the actual thermal resistance for the via diameters
of 0.3 mm and 0.5 mm is lower compared with this example.
Layout K (0.3 mm) corresponds to layout J on the previous
page.

If vias are placed in the solder area directly under the

exposed pad or FIN, the recommended via diameter is 0.3
mm or less to prevent solder from being sucked into vias.

70
2-layer PCB
60
θJA (°C/W)

50
4-layer PCB
40

30
K L M
VIA Layout Drawing

K. Φ0.3 mm L. Φ0.5 mm M. Φ1.0 mm

represents solder on the exposed pad area.

Figure 19. Thermal resistance with varied via diameters

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PCB Layout Thermal Design Guide Application Note

Position of heat source separately providing the ground for each function block. In
such cases, the copper foil area of the main destination of the
Figure 20 shows the change in thermal resistance with
thermal conduction is decreased. However, since there are
different positions of the heat source on the board. In case A,
other heat dissipation paths, such as the board (FR4), the
the heat source is placed on the center of the board. Since the
increase in the thermal resistance is smaller compared with
heat is conducted in all directions, the thermal resistance is
the case where the heat source is placed on one end.
lowest. In case B, the heat source is placed on one end of the
board. Since the volume for thermal conduction is decreased, Since there are many parts in the actual equipment, it is
the thermal resistance is higher. In case C, the copper foil difficult to secure a large copper foil area for one heat source.
plane, which is the main destination of the thermal conduction, However, it is important to intentionally lay out the heat source
is divided with a slit. It is possible that slits are formed in the on the center so that the copper foil area can be evenly
ground plane as a countermeasure against the EMI or noise, secured around 360°.

76.2mm

Top layer Bottom layer Top layer Bottom layer Top layer Bottom layer
114.3mm

Heat source
Heat source Heat source

Footprint 5505 mm2 Footprint 5505 mm2 Footprint 3213 mm2

θJA = 48.6 °C/W θJA = 56.3 °C/W θJA = 52.4 °C/W

TJ = 64.8 °C TJ = 71.2 °C TJ = 68.0 °C

Slit

A. Placed on the center B. Placed on one end C. Ground plane divided with
slit

Figure 20. Change in the thermal resistance due to difference in the positions of the heat source
Contour diagram viewing the copper foil of the bottom layer in the 2-layer board from the top
The same power loss for the heat sources

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PCB Layout Thermal Design Guide Application Note

Neighboring heat sources

Figure 21 shows the change in thermal resistance when heat Like this example, even when the temperature increase is
sources are closely placed. In this example, three heat below the design target value after the thermal design for each
sources with the same power loss are closely placed in B and heat source, the thermal interference phenomenon should be
C. The thermal resistance is higher compared with A, where considered in the thermal design if the three heat sources
only one heat source is placed. This is because each device operate simultaneously and are thermally influenced by each
experiences thermal interference, increasing the ambient other. Such cases may occur in power supplies with multi-
temperature around the devices. The shorter the distance channel output, LED drivers, motor drivers, etc.
between the heat sources, the stronger the influence they
experience.

PCB layout PCB vertical structure

152.4mm
Top layer Middle layer 1 Middle layer 2 Bottom layer
via
Top layer, 70μm Signal layer
Middle layer 1, 35μm Power plane (ground)
152.4mm

Middle layer 2, 35μm Power plane (power)

Bottom layer, 70μm Signal layer
Heat source Insulation distance 0.6mm t = 1.6mm

Footprint 22022 mm2 22022 mm2 22022 mm2

θJA = 31.7 °C/W θJA = 35.7, 37.4, 35.1 °C/W θJA = 39.7, 41.4, 39.6 °C/W
TJ = 51.8 °C TJ = 55.3, 56.7, 54.7 °C TJ = 58.6, 60.1, 58.5 °C

Heat source Heat source Heat source

A. One heat generation source B. Heat generation sources C. Heat generation sources
on the center at 20 mm intervals at 10 mm intervals

Figure 21. Change in the thermal resistance when heat sources are closely placed
Contour diagram viewing the 4-layer board from the top
The same power loss for the heat sources

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PCB Layout Thermal Design Guide Application Note

Distributed heat sources mitigated by distributing the heat sources. This is because the
thermal resistance is decreased as the thermal conduction
Figure 22 shows the change in thermal resistance if the heat
area is increased.
sources are distributed. In case A, the power loss occurs in
one device and the junction temperature is 107.4°C. In case Thus, distribution of the heat sources (power loss) is an
B, the power loss in case A is evenly distributed to three effective measure to decrease the temperature of each device.
devices. Although the thermal interference occurs between the An IC package is taken as an example here. However, the
devices, it can be seen that the temperature increase is same effect is obtained for passive elements such as resistors.

PCB layout PCB vertical structure

152.4mm
Top layer Middle layer 1 Middle layer 2 Bottom layer
via
Top layer, 70μm Signal layer
Middle layer 1, 35μm Power plane (ground)
152.4mm

Middle layer 2, 35μm Power plane (power)

Bottom layer, 70μm Signal layer
Heat source Insulation distance 0.6mm t = 1.6mm

Footprint 22022 mm2 22022 mm2 22022 mm2

θJA = 32.4 °C/W θJA = 35.7, 37.4, 35.1 °C/W

TJ = 107.4 °C TJ = 55.3, 56.7, 54.7 °C

Heat source Heat source

A. Power loss in one device B. Power is distributed to three devices

Figure 22. Change in the thermal resistance with distributed heat sources
Contour diagram viewing the 4-layer board from the top
Total power loss is the same for the heat sources on the board.

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PCB Layout Thermal Design Guide Application Note

Consideration of passive components package, use FIN for heat dissipation in combination with a
ground terminal. Placing electrolytic capacitors C1 and C2 near
vulnerable to high temperature the device results in the layout as shown in Figure 24. Since
It is known that electrolytic solutions in electrolytic capacitors the copper foil in the heat dissipation area and the ground
tend to evaporate at higher temperatures, reducing the life of wiring are shared, the heat from FIN for heat dissipation is
the capacitors. Therefore, it is necessary to decrease conducted through the wide copper foil to the capacitors as
excessive temperatures in order to extend the life of shown in Figure 25. The temperature at the capacitor
components vulnerable to high temperatures. There are three terminals is 57°C.
paths from a heat source to passive components: thermal As a countermeasure, minimize the thermal conduction by
conduction, convection (heat transmission), and heat radiation. reducing the wiring width to the minimum current capacity
For the convection (heat transmission), ventilate the chassis tolerance and place the capacitors at the same distance from
to decrease the inside temperature. For the heat radiation, the heat source, as shown in Figure 26. Figure 27 is the result,
separate the components from the heat source or provide a showing a decrease in the capacitor terminal temperature to
heat insulating plate to shield the components from heat. For 44°C.
the thermal conduction, the heat is conducted mainly through
copper wiring. Therefore, separate the components from the
heat source or minimize the width of the copper wiring. VIN LDO VOUT

Figure 23 shows an LDO circuit as an example. However, in C1 FIN C2

some cases, an electrolytic capacitor must be placed near a GND GND
heat source device to achieve certain electrical characteristics.
For three-terminal LDO, many pin layouts, such as the TO252 Figure 23. LDO circuit diagram

Heatsink area

FIN

GND GND

VIN C1 C2 VOUT

10mm 10mm 57°C

Figure 24. PCB layout in which the capacitors Figure 25. Contour diagram when the capacitors
are placed in the heat dissipation area are placed in the heat dissipation area

Heatsink area

FIN
10mm

C1 C2

44°C
GND
GND

VOUT
VIN

Figure 26. PCB layout in which the Figure 27. Contour diagram when the
capacitors are placed away from the capacitors are placed away from the
heat dissipation area heat dissipation area

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PCB Layout Thermal Design Guide Application Note

This is because the thermal conduction over the same Temperature increase of copper foil wiring
distance becomes more difficult due to higher thermal
resistance for the board (FR4) compared with the copper foil. For a conductor (copper foil wiring) through which a large
current flows, it is necessary to determine the minimum width
As described above, a layout focusing only on the electrical and thickness based on the required current capacity and the
characteristics may cause a thermal issue. Therefore, it is maximum tolerance for increase in the conductor temperature.
necessary to consider the positional relation of the devices Neglecting this may cause a temperature increase,
that act as heat sources and the devices vulnerable to high deteriorating the PCB or increasing the ambient temperature.
temperature.
Refer to the following figures for the minimum width and
For AC-DC converters and the like, the AC ripple current is thickness of conductors. These figures are produced based on
smoothed with an electrolytic capacitor. However, a large the approximations and figures published in “IPC-2221A,
ripple current and the internal resistance of the capacitor Generic Standard on Printed Board Design” with the units
generate a power loss, causing self-heating of the capacitor. converted to the metric system.
In such cases, contrary to the layout described above,
increase the wiring area and allow the heat to be conducted to
the wiring.

35 35 100 °C

30 75 °C
30
60 °C
25 ΔT 25 45 °C
100 °C
30 °C
Current [A]

20
Current [A]

75 °C 20
60 °C 20 °C
15 45 °C 15
30 °C 10 °C
20 °C
10 10 ΔT
10 °C
5 5

0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Conductor width [mm] Conductor width [mm]

Figure 28. Temperature increase due to the conductor Figure 29. Temperature increase due to the conductor
width and current. width and current.
1- and 2-layer PCB and outer layers of multi-layer PCB. 1- and 2-layer PCB and outer layers of multi-layer PCB.
Conductor thickness 18 µm. Conductor thickness 35 µm.

35 35
30 °C
ΔT ΔT
30 30
20 °C 10 °C

25 25

10 °C
Current [A]

Current [A]

20 20

15 15

10 10

5 5

0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Conductor width [mm] Conductor width [mm]

Figure 30. Temperature increase due to the conductor Figure 31. Temperature increase due to the conductor
width and current. width and current.
1- and 2-layer PCB and outer layers of multi-layer PCB. 1- and 2-layer PCB and outer layers of multi-layer PCB.
Conductor thickness 70 µm. Conductor thickness 105 µm.

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PCB Layout Thermal Design Guide Application Note

Figures 28 to 31 show the temperature increase applied to the In the same way for the thermal resistance of the
1- and 2-layer PCB and the outer layers of the multi-layer PCB semiconductor packages, the values of increases in the
for each conductor thickness. Similarly, Figures 32 to 35 show copper wiring temperature depend on the PCB material, layout,
the temperature increase applied to the middle layers of the parts configuration, chassis shape, surrounding environment,
multi-layer PCB. and so on. Therefore, use these figures as a rough guide.

15
15
14
14
13 ΔT
13
12 12 45 °C
11 11
10 10 30 °C
9 ΔT
9
Current [A]

20 °C

Current [A]
8
45 °C 8
7 7
30 °C 10 °C
6 6
5 20 °C
5
4 10 °C 4
3 3
2 2
1 1
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Conductor width [mm] Conductor width [mm]

Figure 32. Temperature increase due to the Figure 33. Temperature increase due to the
conductor width and current. conductor width and current.
Middle layers of multi-layer PCB Middle layers of multi-layer PCB
Conductor thickness 18 µm. Conductor thickness 35 µm.

15 15
14 ΔT 20 °C 14 ΔT 10 °C
13 13
12 12
11 11
10 °C
10 10
9 9
Current [A]

Current [A]

8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Conductor width [mm] Conductor width [mm]

Figure 34. Temperature increase due to the Figure 35. Temperature increase due to the
conductor width and current. conductor width and current.
Middle layers of multi-layer PCB Middle layers of multi-layer PCB
Conductor thickness 70 µm. Conductor thickness 105 µm.

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PCB Layout Thermal Design Guide Application Note

Summary of key points for reducing the However, care must be taken when placing the vias, because
thermal resistance solder is more likely to be sucked into the vias during the
reflow process if the via diameter is 0.3 mm or more.
Copper foil area
• The larger the copper foil area, the lower the thermal
Position of heat source
resistance.
• Since there are many parts, it is difficult to secure a large
• Select an appropriate size of the copper foil area. If the
copper foil area for one heat source. However, intentionally
copper foil area is expanded more than necessary, the
lay out the heat source on the center so that the copper foil
thermal conduction efficiency is decreased as the distance
area can be evenly secured around 360°.
from the heat source is increased, and the effect obtained
may not be proportionate to the area.
Neighboring heat sources
• In the multi-layer boards, the thermal resistance can be
• If multiple heat sources are closely placed, the thermal
efficiently reduced by preferentially increasing the copper foil
interference phenomenon when all the heat sources are
area of layers closer to the heat source.
operated simultaneously should be considered in designing.

Board thickness
Distributed heat sources
• In the 1-layer boards, since the horizontal thermal conduction
• Distribution of the heat sources (power loss) is an effective
takes precedence, increasing the board thickness reduces
measure to decrease the temperature of each device.
the thermal resistance.
• In the multi-layer boards, the horizontal thermal conduction
Consideration of passive components vulnerable to high
takes precedence if the copper foil area for heat dissipation
temperature
is small. Therefore, increasing a board’s thickness reduces
• A layout focusing only on the electrical characteristics may
the thermal resistance. If the copper foil area is large, since
cause a thermal issue.
the vertical thermal conduction takes precedence,
• It is necessary to consider the positional relation of the
decreasing the board thickness reduces the thermal
devices that act as heat sources and the devices vulnerable
resistance. The boundary between the two situations
to high temperature.
depends on the PCB conditions.
• If a device that acts as a heat source is placed near a device
Number of layers vulnerable to high temperature, keep the wiring width to the
• The thermal resistance tends to be lower when the number minimum necessary in order to prevent the thermal
of layers is increased. However, in the multi-layer boards, the conduction through the copper wiring with a low thermal
thermal resistance can be efficiently lowered by placing a resistance.
larger copper foil area for heat dissipation on the same layer
as the heat source or the adjacent layer. Temperature increase of copper wiring
• For a conductor (copper foil wiring) through which a large
Copper foil thickness current flows, it is necessary to determine the minimum width
• The thicker the copper foil, the lower the thermal resistance. and thickness based on the required current capacity and the
The effect is more significant when the copper foil area is maximum tolerance for increase in the conductor
larger. temperature. Neglecting this may cause the temperature
increase, deteriorating the PCB or increasing the ambient
temperature.
Thermal via
• The larger the number of vias, the lower the thermal
resistance. However, since the effect is reduced if the vias
are separated farther from the heat source, place the vias
near the heat source.
• The larger the via diameter, the lower the thermal resistance.

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PCB Layout Thermal Design Guide Application Note

Challenges
There are various types of power circuits. For a quiet circuit,
such as a linear regulator (LDO), in which the power does not
vary frequently, the PCB layout can be considered while
focusing only on the heat dissipation performance. In contrast,
for a circuit such as a switching regulator, in which the power
varies rapidly, the EMI must also be considered in addition to
the heat dissipation. There are only a few layouts capable of
managing both heat dissipation and the EMI. In most cases, a
point of compromise between them must be found to design
the layout.

The thermal design requires a larger copper foil area. However,

many countermeasures against the EMI are available based
on the frequency band where the countermeasures are taken,
such as using the capacitance between layers and securing
the path for return current. Furthermore, these
countermeasures tend to be applicable on a case-by-case
(cut-and-try) basis. Therefore, it is difficult to provide a guide
for all PCB. If available, refer to the guides for individual PCB.

References
[1] JESD51-3:1996, Low Effective Thermal Conductivity Test
Board for Leaded Surface Mount Packages, JEDEC Solid State
Technology Association
[2] JESD51-5:1999, Extension of Thermal Test Board Standards for
Packages with Direct Thermal Attachment Mechanisms,
JEDEC Solid State Technology Association
[3] JESD51-7:1999, High Effective Thermal Conductivity Test
Board for Leaded Surface Mount Packages, JEDEC Solid State
Technology Association
[4] IPC-2221A: May 2003, Generic Standard on Printed Board
Design, IPC - Association Connecting Electronics Industries

Related application notes

[1] TO252 Package Thermal Resistance Information

[2] HTSOP-J8 Package Thermal Resistance Information (A)

[3] HTSOP-J8 Package Thermal Resistance Information (S)

Pay attention to applicable item numbers

© 2022 ROHM Co., Ltd. No .65AN002E Rev.001

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 Notice

Notes
1) The information contained herein is subject to change without notice.

2) Before you use our Products, please contact our sales representative and verify the latest specifica-
tions :

3) Although ROHM is continuously working to improve product reliability and quality, semicon-
ductors can break down and malfunction due to various factors.
Therefore, in order to prevent personal injury or fire arising from failure, please take safety
measures such as complying with the derating characteristics, implementing redundant and
fire prevention designs, and utilizing backups and fail-safe procedures. ROHM shall have no
responsibility for any damages arising out of the use of our Poducts beyond the rating specified by
ROHM.

4) Examples of application circuits, circuit constants and any other information contained herein are
provided only to illustrate the standard usage and operations of the Products. The peripheral
conditions must be taken into account when designing circuits for mass production.

5) The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly,
any license to use or exercise intellectual property or other rights held by ROHM or any other
parties. ROHM shall have no responsibility whatsoever for any dispute arising out of the use of
such technical information.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified
below), please contact and consult with a ROHM representative : transportation equipment (i.e.
cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety
equipment, medical systems, servers, solar cells, and power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace
equipment, nuclear power control systems, and submarine repeaters.

9) ROHM shall have no responsibility for any damages or injury arising from non-compliance with
the recommended usage conditions and specifications contained herein.

10) ROHM has used reasonable care to ensure the accuracy of the information contained in this
document. However, ROHM does not warrants that such information is error-free, and ROHM
shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.

11) Please use the Products in accordance with any applicable environmental laws and regulations,
such as the RoHS Directive. For more details, including RoHS compatibility, please contact a
ROHM sales office. ROHM shall have no responsibility for any damages or losses resulting
non-compliance with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries,
you must abide by the procedures and provisions stipulated in all applicable export laws and
regulations, including without limitation the US Export Administration Regulations and the Foreign
Exchange and Foreign Trade Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of
ROHM.

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