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MUX508, MUX509
SBAS758C – JANUARY 2016 – REVISED SEPTEMBER 2016

MUX50x
36-V, Low-Capacitance, Low-Charge-Injection, Precision, Analog Multiplexers
1 Features 3 Description
1• Low On-Capacitance The MUX508 and MUX509 (MUX50x) are modern,
complementary metal-oxide semiconductor (CMOS),
– MUX508: 9.4 pF analog multiplexers (muxes). The MUX508 offers 8:1
– MUX509: 6.7 pF single-ended channels, whereas the MUX509 offers
• Low Input Leakage: 10 pA differential 4:1 or dual 4:1 single-ended channels. The
MUX508 and MUX509 work equally well with either
• Low Charge Injection: 0.3 pC
dual supplies (±5 V to ±18 V) or a single supply (10 V
• Rail-to-Rail Operation to 36 V). They also perform well with symmetric
• Wide Supply Range: ±5 V to ±18 V, 10 V to 36 V supplies (such as VDD = 12 V, VSS = –12 V), and
• Low On-Resistance: 125 Ω unsymmetric supplies (such as VDD = 12 V, VSS =
–5 V). All digital inputs have TTL-logic compatible
• Transition Time: 92 ns thresholds, ensuring both TTL and CMOS logic
• Break-Before-Make Switching Action compatibility when operating in the valid supply
• EN Pin Connectable to VDD voltage range.
• Logic Levels: 2 V to VDD The MUX508 and MUX509 have very low on and off
• Low Supply Current: 45 µA leakage currents, allowing these multiplexers to
switch signals from high input impedance sources
• ESD Protection HBM: 2000 V with minimal error. A low supply current of 45 µA
• Industry-Standard TSSOP and SOIC Packages allows for use in portable applications.

2 Applications Device Information(1)


• Factory Automation and Industrial Process PART NUMBER PACKAGE BODY SIZE (NOM)
Controls TSSOP (16) 5.00 mm × 4.40 mm
MUX50x
• Programmable Logic Controllers (PLC) SOIC (16) 9.90 mm × 3.91 mm

• Analog Input Modules (1) For all available packages, see the package option addendum
at the end of the data sheet.
• ATE Test Equipment
• Digital Multimeters
• Battery Monitoring Systems

Simplified Schematic Charge Injection vs Source Voltage


2

VDD = 15 V
1 VSS = ±15 V
Charge Injection (pC)

Bridge Sensor

± VINP
0
Thermocouple MUX509 PGA/INA ADC

+ VINM
VDD = 10 V
VDD = 12 V
±1 VSS = ±10 V
Current VSS = 0 V
Sensing

Photo
±2
LED Detector
±15 ±10 ±5 0 5 10 15
Optical Sensor
Copyright © 2016, Texas Instruments Incorporated
Source Voltage (V) C008
Analog Inputs

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MUX508, MUX509
SBAS758C – JANUARY 2016 – REVISED SEPTEMBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.10 Channel-to-Channel Crosstalk .............................. 21
2 Applications ........................................................... 1 8.11 Bandwidth ............................................................. 22
3 Description ............................................................. 1 8.12 THD + Noise ......................................................... 22
4 Revision History..................................................... 2 9 Detailed Description ............................................ 23
9.1 Overview ................................................................. 23
5 Device Comparison Table..................................... 4
9.2 Functional Block Diagram ....................................... 23
6 Pin Configuration and Functions ......................... 4
9.3 Feature Description................................................. 24
7 Specifications......................................................... 6
9.4 Device Functional Modes........................................ 26
7.1 Absolute Maximum Ratings ...................................... 6
10 Applications and Implementation...................... 27
7.2 ESD Ratings.............................................................. 6
10.1 Application Information.......................................... 27
7.3 Recommended Operating Conditions....................... 6
10.2 Typical Application ............................................... 27
7.4 Thermal Information .................................................. 7
7.5 Electrical Characteristics: Dual Supply ..................... 7 11 Power-Supply Recommendations ..................... 29
7.6 Electrical Characteristics: Single Supply................... 9 12 Layout................................................................... 30
7.7 Typical Characteristics ............................................ 11 12.1 Layout Guidelines ................................................. 30
12.2 Layout Example .................................................... 30
8 Parameter Measurement Information ................ 15
8.1 Truth Tables ............................................................ 15 13 Device and Documentation Support ................. 31
8.2 On-Resistance ........................................................ 16 13.1 Documentation Support ........................................ 31
8.3 Off-Leakage Current ............................................... 16 13.2 Related Links ........................................................ 31
8.4 On-Leakage Current ............................................... 17 13.3 Receiving Notification of Documentation Updates 31
8.5 Transition Time ....................................................... 17 13.4 Community Resources.......................................... 31
8.6 Break-Before-Make Delay....................................... 18 13.5 Trademarks ........................................................... 31
8.7 Turn-On and Turn-Off Time .................................... 19 13.6 Electrostatic Discharge Caution ............................ 31
8.8 Charge Injection ...................................................... 20 13.7 Glossary ................................................................ 31
8.9 Off Isolation ............................................................. 21 14 Mechanical, Packaging, and Orderable
Information ........................................................... 32

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (July 2016) to Revision C Page

• Added D (SOIC) package to document.................................................................................................................................. 1


• Changed last Features bullet to include SOIC package ........................................................................................................ 1
• Changed second sentence of Description section ................................................................................................................. 1
• Added SOIC package to Device Information table ................................................................................................................ 1
• Changed MUX509 description in Device Comparison Table ................................................................................................. 4
• Added D package to Pin Configuration and Functions section .............................................................................................. 4
• Added D package to Thermal Information table .................................................................................................................... 7
• Changed Analog Switch, ID parameter in Electrical Characteristics: Dual Supply table: split parameter into ID(OFF) and
ID(ON) parameters, changed symbols, parameter names, and test conditions ........................................................................ 7
• Changed On-resistance drift parameter in Electrical Characteristics: Single Supply table: changed VS value in test
conditions................................................................................................................................................................................ 9
• Changed Analog Switch, ID parameter in Electrical Characteristics: Single Supply table: split parameter into ID(OFF)
and ID(ON) parameters, changed symbols, parameter names, and ID(ON) test conditions........................................................ 9
• Changed Figure 26: changed switch symbol to a closed switch symbol ............................................................................. 16
• Changed Figure 32: added 0 V line, flipped VS supply symbol............................................................................................ 20
• Changed description of MUX509 in Overview section ........................................................................................................ 23
• Changed Figure 42: changed OPA140 amplifier and charge kickback filter box ................................................................. 27
• Added D package description to Layout Guidelines section ................................................................................................ 30

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MUX508, MUX509
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Changes from Revision A (March 2016) to Revision B Page

• Added TI Design .................................................................................................................................................................... 1


• Changed Analog Switch, IS(OFF) and ID parameter specifications in Electrical Characteristics: Single Supply table.............. 9

Changes from Original (January 2016) to Revision A Page

• Changed from product preview to production data ................................................................................................................ 1

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5 Device Comparison Table

PRODUCT DESCRIPTION
MUX508 8-channel, single-ended analog multiplexer (8:1 mux)
MUX509 4-channel differential or dual 4:1 single-ended analog multiplexer (8:2 mux)

6 Pin Configuration and Functions

MUX508: PW and D Packages


16-Pin TSSOP and SOIC
Top View

A0 1 16 A1

EN 2 15 A2

VSS 3 14 GND

S1 4 13 VDD

S2 5 12 S5

S3 6 11 S6

S4 7 10 S7

D 8 9 S8

Pin Functions: MUX508


PIN
TYPE DESCRIPTION
NAME NO.
A0 1 Digital input Address line 0
A1 16 Digital input Address line 1
A2 15 Digital input Address line 2
D 8 Analog input or output Drain pin. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
EN 2 Digital input
high, the A[2:0] logic inputs determine which switch is turned on.
GND 14 Power supply Ground (0 V) reference
S1 4 Analog input or output Source pin 1. Can be an input or output.
S2 5 Analog input or output Source pin 2. Can be an input or output.
S3 6 Analog input or output Source pin 3. Can be an input or output.
S4 7 Analog input or output Source pin 4. Can be an input or output.
S5 12 Analog input or output Source pin 5. Can be an input or output.
S6 11 Analog input or output Source pin 6. Can be an input or output.
S7 10 Analog input or output Source pin 7. Can be an input or output.
S8 9 Analog input or output Source pin 8. Can be an input or output.
Positive power supply. This pin is the most positive power-supply potential. For reliable
VDD 13 Power supply operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
Negative power supply. This pin is the most negative power-supply potential. In single-
VSS 3 Power supply supply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.

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MUX509: PW and D Packages


16-Pin TSSOP and SOIC
Top View

A0 1 16 A1

EN 2 15 GND

VSS 3 14 VDD

S1A 4 13 S1B

S2A 5 12 S2B

S3A 6 11 S3B

S4A 7 10 S4B

DA 8 9 DB

Pin Functions: MUX509


PIN
TYPE DESCRIPTION
NAME NO.
A0 1 Digital input Address line 0
A1 16 Digital input Address line 1
DA 8 Analog input or output Drain pin A. Can be an input or output.
DB 9 Analog input or output Drain pin B. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
EN 2 Digital input
high, the A[1:0] logic inputs determine which pair of switches is turned on.
GND 15 Power supply Ground (0 V) reference
S1A 4 Analog input or output Source pin 1A. Can be an input or output.
S2A 5 Analog input or output Source pin 2A. Can be an input or output.
S3A 6 Analog input or output Source pin 3A. Can be an input or output.
S4A 7 Analog input or output Source pin 4A. Can be an input or output.
S1B 13 Analog input or output Source pin 1B. Can be an input or output.
S2B 12 Analog input or output Source pin 2B. Can be an input or output.
S3B 11 Analog input or output Source pin 3B. Can be an input or output.
S4B 10 Analog input or output Source pin 4B. Can be an input or output.
Positive power supply. This pin is the most positive power supply potential. For reliable
VDD 14 Power supply operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
Negative power supply. This pin is the most negative power supply potential. In single-
VSS 3 Power supply supply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD –0.3 40
Supply voltage VSS –40 0.3 V
VDD – VSS 40
Voltage VSS – 0.3 VDD + 0.3 V
Digital input pins (2) EN, A0, A1, A2 pins
Current –30 30 mA
Voltage VSS – 2 VDD + 2 V
Analog input pins (2) Sx, SxA, SxB pins
Current –30 30 mA
Voltage VSS – 2 VDD + 2 V
Analog output pins (2) D, DA, DB pins
Current –30 30 mA
Operating, TA –55 150
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Only one pin at a time

7.2 ESD Ratings


VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions


MIN NOM MAX UNIT
Dual supply 5 18
VDD (1) Positive power-supply voltage V
Single supply 10 36
VSS (2) Negative power-supply voltage (dual supply) –5 –18 V
VDD – VSS Supply voltage 10 36 V
VS Source pins voltage (3) VSS VDD V
VD Drain pins voltage VSS VDD V
VEN Enable pin voltage VSS VDD V
VA Address pins voltage VSS VDD V
ICH Channel current (TA = 25°C) –25 25 mA
TA Operating temperature –40 125 °C

(1) When VSS = 0 V, VDD can range from 10 V to 36 V.


(2) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V, and VDD ≥ 5 V.
(3) VS is the voltage on all the S pins.

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7.4 Thermal Information


MUX50x
THERMAL METRIC (1) PW (TSSOP) D (SOIC) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 103.8 78.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.8 37.2 °C/W
RθJB Junction-to-board thermal resistance 49.8 35.7 °C/W
ψJT Junction-to-top characterization parameter 2.7 8.2 °C/W
ψJB Junction-to-board characterization parameter 49.1 35.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics.

7.5 Electrical Characteristics: Dual Supply


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG SWITCH
Analog signal range TA = –40°C to +125°C VSS VDD V
VS = 0 V, ICH = 1 mA 125 170
145 200
RON On-resistance Ω
VS = ±10 V, ICH = 1 mA TA = –40°C to +85°C 230
TA = –40°C to +125°C 250
2.4 6
On-resistance mismatch
ΔRON VS = ±10 V, ICH = 1 mA TA = –40°C to +85°C 9 Ω
between channels
TA = –40°C to +125°C 11
22 45
RFLAT On-resistance flatness VS = 10 V, 0 V, –10 V TA = –40°C to +85°C 53 Ω
TA = –40°C to +125°C 58
On-resistance drift VS = 0 V 0.52 %/°C
–1 0.01 1
Switch state is off,
IS(OFF) Input leakage current TA = –40°C to +85°C –10 10 nA
VS = ±10 V, VD = ±10 V (1)
TA = –40°C to +125°C –25 25
–1 0.01 1
Switch state is off,
ID(OFF) Output off leakage current TA = -40°C to +85°C –10 10 nA
VS = ±10 V, VD = ±10 V (1)
TA = -40°C to +125°C –50 50
–1 0.01 1
Switch state is on,
ID(ON) Output on leakage current TA = –40°C to +85°C –10 10 nA
VD = ±10 V, VS = floating
TA = –40°C to +125°C –50 50
LOGIC INPUT
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
ID Input current 0.15 µA

(1) When VS is positive, VD is negative, and vice versa.

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Electrical Characteristics: Dual Supply (continued)


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCH DYNAMICS (2)
88 136
VS = ±10 V, RL = 300 Ω,
tON Enable turn-on time TA = –40°C to +85°C 144 ns
CL= 35 pF
TA = –40°C to +125°C 151
63 75
VS = ±10 V, RL = 300 Ω,
tOFF Enable turn-off time TA = –40°C to +85°C 83 ns
CL= 35 pF
TA = –40°C to +125°C 90
92 143
VS = 10 V, RL = 300 Ω,
tt Transition time TA = –40°C to +85°C 151 ns
CL= 35 pF,
TA = –40°C to +125°C 157
Break-before-make time
tBBM VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C 30 54 ns
delay
VS = 0 V 0.3
QJ Charge injection CL = 1 nF, RS = 0 Ω pC
VS = –15 V to +15 V ±0.6

RL = 50 Ω, VS = 1 VRMS, Nonadjacent channel to D, DA, DB –96


Off-isolation dB
f = 1 MHz Adjacent channel to D, DA, DB –85

Channel-to-channel RL = 50 Ω, VS = 1 VRMS, Nonadjacent channels –96


dB
crosstalk f = 1 MHz Adjacent channels –88
CS(OFF) Input off-capacitance f = 1 MHz, VS = 0 V 2.4 2.9 pF
MUX508 7.5 8.4
CD(OFF) Output off-capacitance f = 1 MHz, VS = 0 V pF
MUX509 4.3 5

Input/Output on- MUX508 9.4 10.6


CD(ON) f = 1 MHz, VS = 0 V pF
capacitance MUX509 6.7 7.7
POWER SUPPLY
45 59
All VA = 0 V or 3.3 V,
VDD supply current TA = –40°C to +85°C 62 µA
VS = 0 V, VEN = 3.3 V,
TA = –40°C to +125°C 83
25 34
All VA = 0 V or 3.3 V,
VSS supply current TA = –40°C to +85°C 37 µA
VS = 0 V, VEN = 3.3 V,
TA = –40°C to +125°C 57

(2) Specified by design, not production tested.

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7.6 Electrical Characteristics: Single Supply


at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG SWITCH
Analog signal range TA = –40°C to +125°C VSS VDD V
235 340
RON On-resistance VS = 10 V, ICH = 1 mA TA = –40°C to +85°C 390 Ω
TA = –40°C to +125°C 430
3.1 12
ΔRON On-resistance match VS = 10 V, ICH = 1 mA TA = –40°C to +85°C 19 Ω
TA = –40°C to +125°C 23
On-resistance drift VS = 10 V 0.47 %/°C
–1 0.01 1
Switch state is off,
IS(OFF) Input leakage current VS = 1 V and VD = 10 V, TA = –40°C to +85°C –10 10 nA
or VS = 10 V and VD = 1 V (2)
TA = –40°C to +125°C –25 25
–1 0.01 1
Switch state is off,
ID(OFF) Output off leakage current VS = 1 V and VD = 10 V, TA = –40°C to +85°C –10 10 nA
or VS = 10 V and VD = 1 V (2)
TA = –40°C to +125°C –50 50
–1 0.01 1
Switch state is on,
ID(ON) Output on leakage current VD = 1 V and 10 V, TA = –40°C to +85°C –10 10 nA
VS = floating
TA = –40°C to +125°C –50 50
LOGIC INPUT
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
ID Input current 0.15 µA
SWITCH DYNAMIC CHARACTERISTICS
85 140
VS = 8 V, RL = 300 Ω,
tON Enable turn-on time TA = –40°C to +85°C 145 ns
CL= 35 pF
TA = –40°C to +125°C 149
48 83
VS = 8 V, RL = 300 Ω,
tOFF Enable turn-off time TA = –40°C to +85°C 94 ns
CL= 35 pF
TA = –40°C to +125°C 102
VS = 8 V, CL= 35 pF 87 147
VS = 8 V, RL = 300 Ω,
TA = –40°C to +85°C 153
tt Transition time CL= 35 pF, ns
VS = 8 V, RL = 300 Ω,
TA = –40°C to +125°C 155
CL= 35 pF,
Break-before-make time
tBBM VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C 30 54 ns
delay
VS = 6 V 0.15
QJ Charge injection CL = 1 nF, RS = 0 Ω pC
VS = 0 V to 12 V, ±0.4

RL = 50 Ω, VS = 1 VRMS, Nonadjacent channel to D, DA, DB -96


Off-isolation dB
f = 1 MHz Adjacent channel to D, DA, DB -85

Channel-to-channel RL = 50 Ω, VS = 1 VRMS, Nonadjacent channels –96


dB
crosstalk f = 1 MHz Adjacent channels -88
CS(OFF) Input off-capacitance f = 1 MHz, VS = 6 V 2.7 3.2 pF
MUX508 9.1 10
CD(OFF) Output off-capacitance f = 1 MHz, VS = 6 V pF
MUX509 5 5.7

Input/Output on- MUX508 10.8 12


CD(ON) f = 1 MHz, VS = 6 V pF
capacitance MUX509 6.9 8

(1) Specified by design, not production tested.


(2) When VS is 1 V, VD is 10 V, and vice versa.

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Electrical Characteristics: Single Supply (continued)


at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
42 53
All VA = 0 V or 3.3 V,
VDD supply current TA = –40°C to +85°C 56 µA
VS= 0 V, VEN = 3.3 V
TA = –40°C to +125°C 77
23 38
All VA = 0 V or 3.3 V,
VSS supply current TA = –40°C to +85°C 31 µA
VS = 0 V, VEN = 3.3 V
TA = –40°C to +125°C 51

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7.7 Typical Characteristics


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)

250 250
TA = 125ƒC TA = 85ƒC
VDD = 13.5 V VDD = 15 V
200 VSS = ±13.5 V VSS = ±15 V 200
On Resistance (Ÿ)

On Resistance (Ÿ)
150 150
TA = 25ƒC

100 100

50 VDD = 18 V 50
VDD = 16.5 V
VSS = ±18 V VSS = ±16.5 V TA = 0ƒC TA = ±40ƒC

0 0
±20 ±15 ±10 ±5 0 5 10 15 20 ±18 ±12 ±6 0 6 12 18
Source or Drain Voltage (V) C001 Source or Drain Voltage (V) C002

VDD = 15 V, VSS = –15 V

Figure 1. On-Resistance vs Source or Drain Voltage Figure 2. On-Resistance vs Source or Drain Voltage
700 700

600 VDD = 5 V 600


VSS = ±5 V
VDD = 6 V
500 500
On Resistance (Ÿ)
On Resistance (Ÿ)

VSS = ±6 V TA = 125ƒC TA = 85ƒC

400 400

300 300

200 200 TA = 25ƒC

VDD = 7 V
100 VSS = ±7 V 100
TA = 0ƒC
TA = ±40ƒC
0 0
±8 ±6 ±4 ±2 0 2 4 6 8 0 2 4 6 8 10 12
Source or Drain Voltage (V) C003 Source or Drain Voltage (V) C004

VDD = 12 V, VSS = 0 V

Figure 3. On-Resistance vs Source or Drain Voltage Figure 4. On-Resistance vs Source or Drain Voltage
250 700
VDD = 10 V
VDD = 30 V
600 VSS = 0 V
VSS = 0 V
200
VDD = 12 V
500
On Resistance (Ÿ)

On Resistance (Ÿ)

VSS = 0 V
150
400 VDD = 14 V
VSS = 0 V
300
100

200
50 VDD = 33 V VDD = 36 V
VSS = 0 V VSS = 0 V 100

0 0
0 6 12 18 24 30 36 0 2 4 6 8 10 12 14
Source or Drain Voltage (V) C023 Source or Drain Voltage (V) C005

Figure 5. On-Resistance vs Source or Drain Voltage Figure 6. On-Resistance vs Source or Drain Voltage

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Typical Characteristics (continued)


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250 250

200 200

On Resistance (Ÿ)
On Resistance (Ÿ)

150 150

100 100

50 50

0 0
0 6 12 18 24 ±12 ±6 0 6 12
Source or Drain Voltage (V) C029 Source or Drain Voltage (V) C024

VDD = 24 V, VSS = 0 V VDD = 12 V, VSS = –12 V

Figure 7. On-Resistance vs Source or Drain Voltage Figure 8. On-Resistance vs Source or Drain Voltage
900 900
ID(ON)+
ID(ON)+
600 Leakage Current (pA) 600
Leakage Current (pA)

ID(OFF)+ IS(OFF)+
300 300
ID(OFF)+
IS(OFF)+
0 0

IS(OFF)±
±300 ±300 IS(OFF)±
ID(OFF)±
±600 ID(OFF)± ±600 ID(ON)±
ID(ON)±
±900 ±900
±75 ±50 ±25 0 25 50 75 100 125 150 ±75 ±50 ±25 0 25 50 75 100 125 150
Temperature (ƒC) C006 Temperature (ƒC) C007

VDD = 15 V, VSS = –15 V VDD = 12 V, VSS = 0 V

Figure 9. Leakage Current vs Temperature Figure 10. Leakage Current vs Temperature


2 2

VDD = 15 V
1 VSS = ±15 V 1
Charge Injection (pC)

VDD = 15 V
Charge Injection (pC)

VSS = ±15 V

0 0

VDD = 10 V
VDD = 10 V VSS = ±10 V
VDD = 12 V
±1 VSS = ±10 V ±1
VSS = 0 V
VDD = 12 V
VSS = 0 V
±2 ±2
±15 ±10 ±5 0 5 10 15 ±15 ±10 ±5 0 5 10 15
Source Voltage (V) C008 Source Voltage (V) C025

MUX508, source-to-drain MUX509, source-to-drain

Figure 11. Charge Injection vs Source Voltage Figure 12. Charge Injection vs Source Voltage

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Typical Characteristics (continued)


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
9 150
tON (VDD = 15 V, VSS = ±15 V)

Turn On and Turn Off Times (ns)


6 VDD = 15 V
VSS = ±15 V 120
Charge Injection (pC)

VDD = 10 V tON (VDD = 12 V, VSS = 0 V)


3 VSS = ±10 V
90
0
60
±3 VDD = 12 V
VSS = 0 V
30
±6 tOFF (VDD = 15 V, VSS = ±15 V)
tOFF (VDD = 12 V, VSS = 0 V)
±9 0
±15 ±10 ±5 0 5 10 15 ±75 ±50 ±25 0 25 50 75 100 125 150
Drain voltage (V) C011 Temperature (ƒC) C010

Drain-to-source

Figure 13. Charge Injection vs Source or Drain Voltage Figure 14. Turn-On and Turn-Off Times vs Temperature
0 0

±20 ±20

±40 Adjacent Channel to D (Output) ±40 Adjacent Channels


Off Isolation (dB)

Crosstalk (dB)

±60 ±60

±80 ±80

±100 ±100

±120 ±120 Non-Adjacent Channels


Non-Adjacent Channel to D (Output)

±140 ±140
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) C012 Frequency (Hz) C013

Figure 15. Off Isolation vs Frequency Figure 16. Crosstalk vs Frequency


100 3

10 0
On Response (dB)

VDD = 15 V VDD = 5 V
THD+N (%)

VSS = ±15 V VSS = ±5 V

1 ±3

0.1 ±6

0.01 ±9
10 100 1k 10k 100k 100k 1M 10M 100M 1G
Frequency (Hz) C014
Frequency (Hz) C018

Figure 17. THD+N vs Frequency Figure 18. On Response vs Frequency

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Typical Characteristics (continued)


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
18 18

15 15
Capacitance (pF)

Capacitance (pF)
12 12
CD(ON)
CD(OFF)
9 9
CD(ON)

6 6
CD(OFF)
CS(OFF)
3 3
CS(OFF)
0 0
±15 ±10 ±5 0 5 10 15 ±15 ±10 ±5 0 5 10 15
Source Voltage (V) C015 Source or Drain Voltage (V) C026

MUX508, VDD = 15 V, VSS = –15 V MUX509, VDD = 15 V, VSS = –15 V

Figure 19. Capacitance vs Source Voltage Figure 20. Capacitance vs Source Voltage
18 18

15 15
Capacitance (pF)

Capacitance (pF)

12 12
CD(ON)
CD(OFF)
9 9
CD(ON)

6 6
CD(OFF)
3 CS(OFF) 3

CS(OFF)
0 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Source Voltage (V) C016 Source or Drain Voltage (V) C028

MUX508, VDD = 30 V, VSS = 0 V MUX509, VDD = 30 V, VSS = 0 V

Figure 21. Capacitance vs Source Voltage Figure 22. Capacitance vs Source Voltage
18 18

15 15

CD(ON)
Capacitance (pF)
Capacitance (pF)

12 12
CD(OFF)
9 9
CD(ON)

6 CD(OFF) 6

CS(OFF)
3 3
CS(OFF)
0 0
0 3 6 9 12 0 3 6 9 12
Source or Drain Voltage (V) C022 Source or Drain Voltage (V) C027

MUX508, VDD = 12 V, VSS = 0 V MUX509, VDD = 12 V, VSS = 0 V

Figure 23. Capacitance vs Source Voltage Figure 24. Capacitance vs Source Voltage

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Typical Characteristics (continued)


at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
20
15

Drain Current (mA)


10
5
0
±5
±10
±15
±20
±25
±25 ±20 ±15 ±10 ±5 0 5 10 15 20 25
Source Current (mA) C021

Figure 25. Source Current vs Drain Current

8 Parameter Measurement Information


8.1 Truth Tables
Table 1 and Table 2 show the truth tables for the MUX508 and MUX509, respectively.

Table 1. MUX508 Truth Table


EN A2 A1 A0 STATE
0 X (1) X (1) X (1) All channels are off
1 0 0 0 Channel 1 on
1 0 0 1 Channel 2 on
1 0 1 0 Channel 3 on
1 0 1 1 Channel 4 on
1 1 0 0 Channel 5 on
1 1 0 1 Channel 6 on
1 1 1 0 Channel 7 on
1 1 1 1 Channel 8 on

(1) X denotes don't care..

Table 2. MUX509 Truth Table


EN A1 A0 STATE
(1) (1)
0 X X All channels are off
1 0 0 Channels 1A and 1B on
1 0 1 Channels 2A and 2B on
1 1 0 Channels 3A and 3B on
1 1 1 Channels 4A and 4B on

(1) X denotes don't care.

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8.2 On-Resistance
The on-resistance of the MUX50x is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D, DA,
or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is
used to denote on-resistance. The measurement setup used to measure RON is shown in Figure 26. Voltage (V)
and current (ICH) are measured using this setup, and RON is computed as shown in Equation 1.

S D

ICH

VS

Figure 26. On-Resistance Measurement Setup


RON = V / ICH (1)

8.3 Off-Leakage Current


There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source off-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is off. This current is denoted by the symbol IS(OFF).
Drain off-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
off. This current is denoted by the symbol ID(OFF).
The setup used to measure both types of off-leakage currents is shown in Figure 27.

Is (OFF) ID (OFF)
S D
A A

VS VD

Figure 27. Off-Leakage Measurement Setup

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8.4 On-Leakage Current


On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 28 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).

ID (ON)
S D
NC A

NC = No Connection
VD

Figure 28. On-Leakage Measurement Setup

8.5 Transition Time


Transition time is defined as the time taken by the output of the MUX50x to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to the 50% of the transition. Figure 29 shows the setup used to
measure transition time, denoted by the symbol tt.
VDD VSS

3V
VDD VSS
Address
50% 50%
Signal (VIN)
S1 VS1
A0
0V
A1 S2-S7
VIN
A2
tt tt
S8 VS8
VS1
90%
Output
MUX508
Output 2V EN D

GND 300 Ÿ 35 pF
90%
VS8

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Figure 29. Transition-Time Measurement Setup

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8.6 Break-Before-Make Delay


Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX50x is
switching. The MUX50x output first breaks from the on-state switch before making the connection with the next
on-state switch. The time delay between the break and the make is known as a break-before-make delay.
Figure 30 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
VDD VSS

3V

VDD VSS
Address
Signal (VIN)
S1 VS
A0

0V A1 S2-S7
VIN
A2

S8

MUX508
Output
80% 80%
Output 2V EN D

GND 300 Ÿ 35 pF

tBBM

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Figure 30. Break-Before-Make Delay Measurement Setup

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8.7 Turn-On and Turn-Off Time


Turn-on time is defined as the time taken by the output of the MUX50x to rise to a 90% final value after the
enable signal has risen to a 50% final value. Figure 31 shows the setup used to measure turn-on time. Turn-on
time is denoted by the symbol tON.
Turn-off time is defined as the time taken by the output of the MUX50x to fall to a 10% initial value after the
enable signal has fallen to a 50% initial value. Figure 31 shows the setup used to measure turn-off time. Turn-off
time is denoted by the symbol tOFF.
VDD VSS

3V
VDD VSS

Enable
Drive (VIN)
50% 50% S1 VS
A0

A1
S2-S8
0V
A2

tON (EN) tOFF (EN) MUX508

0.9 VS Output
Output EN D

GND
0.1 VS 300 Ÿ 35 pF
VIN

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Figure 31. Turn-On and Turn-Off Time Measurement Setup

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8.8 Charge Injection


The MUX50x have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. Figure 32 shows the setup used to measure charge injection.
VDD VSS

VDD VSS

A0
3V
A1

VEN
A2

MUX508
0V

RS
S D
VOUT

EN
VOUT CL
VOUT VS
1 nF
GND
QINJ = CL × VOUT
VEN

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Figure 32. Charge-Injection Measurement Setup

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8.9 Off Isolation


Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX50x when a 1-VRMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. Figure 33 shows the setup used to measure off
isolation. Use Equation 2 to compute off isolation.
VDD VSS
0.1 µF 0.1 µF

Network Analyzer
VDD VSS

50

S
50 Ÿ
VS

VOUT

RL
50 Ÿ

GND

Figure 33. Off Isolation Measurement Setup

§V ·
Off Isolation 20 ˜ Log ¨ OUT ¸
V
© S ¹ (2)

8.10 Channel-to-Channel Crosstalk


Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,
when a 1-VRMS signal is applied at the source pin of an on-channel. Figure 34 shows the setup used to measure,
and Equation 3 is the equation used to compute, channel-to-channel crosstalk.
VDD VSS
0.1 µF 0.1 µF

VDD VSS
Network Analyzer

VOUT
S1
RL
50 Ÿ

S2 R
50 Ÿ

VS
GND

Figure 34. Channel-to-Channel Crosstalk Measurement Setup

§V ·
Channel-to-Channel Crosstalk 20 ˜ Log ¨ OUT ¸
© VS ¹ (3)

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8.11 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin of an on-channel and the output is measured at the drain pin of the MUX50x. Figure 35 shows the
setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
VDD VSS
0.1 µF 0.1 µF

Network Analyzer
VDD VSS V1

50

VS

V2
D

VOUT

RL
GND 50 Ÿ

Figure 35. Bandwidth Measurement Setup

§V ·
Attenuation 20 ˜ Log ¨ 2 ¸
© V1 ¹ (4)

8.12 THD + Noise


The total harmonic distortion (THD) of a signal is defined as the ratio of the sum of the powers of all harmonic
components to the power of the fundamental frequency at the mux output. The on-resistance of the MUX50x
varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-
impedance load. Total harmonic distortion plus noise is denoted as THD+N. Figure 36 shows the setup used to
measure the THD+N of the MUX50x.
VDD VSS
0.1 µF 0.1 µF

Audio Precision
VDD VSS

RS

S
IN
VS
5 Vrms

VIN D

VOUT

RL
GND 10 NŸ

Figure 36. THD+N Measurement Setup

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9 Detailed Description

9.1 Overview
The MUX50x are a family of analog multiplexers. The Functional Block Diagram section provides a top-level
block diagram of both the MUX508 and MUX509. The MUX508 is an eight-channel, single-ended, analog mux.
The MUX509 is a four-channel, differential or dual 4:1, single-ended, analog mux. Each channel is turned on or
turned off based on the state of the address lines and enable pin.

9.2 Functional Block Diagram

MUX508 MUX509

S1 S1A

S2 S2A

S3 S3A

S4 S4A DA
D
S5 S1B DB

S6 S2B

S7 S3B

S8 S4B

1-of-8 1-of-4
Decoder Decoder

A0 A1 A2 EN A0 A1 EN
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9.3 Feature Description


9.3.1 Ultralow Leakage Current
The MUX50x provide extremely low on- and off-leakage currents. The MUX50x are capable of switching signals
from high source-impedance inputs into a high input-impedance op amp with minimal offset error because of
these ultralow leakage currents. Figure 37 shows typical leakage currents of the MUX50x versus temperature.
900
ID(ON)+
600

Leakage Current (pA)


ID(OFF)+
300
IS(OFF)+
0

IS(OFF)±
±300

±600 ID(OFF)±
ID(ON)±
±900
±75 ±50 ±25 0 25 50 75 100 125 150
Temperature (ƒC) C006

Figure 37. Leakage Current vs Temperature

9.3.2 Ultralow Charge Injection


The MUX50x have a simple transmission gate topology, as shown in Figure 38. Any mismatch in the stray
capacitance associated with the NMOS and PMOS transistors creates an output level change whenever the
switch is opened or closed.

OFF ON

CGSN CGDN

S D

CGSP CGDP

OFF ON

Figure 38. Transmission Gate Topology

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Feature Description (continued)


The MUX50x have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection
to as low as 0.3 pC at VS = 0 V, and ±0.6 pC in the full signal range, as shown in Figure 39.
2

1 VDD = 15 V

Charge Injection (pC)


VSS = ±15 V

VDD = 10 V
VSS = ±10 V
±1
VDD = 12 V
VSS = 0 V
±2
±15 ±10 ±5 0 5 10 15
Source Voltage (V) C025

Figure 39. Source-to-Drain Charge Injection vs Source or Drain voltage

The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux),
where D becomes the input and Sx becomes the output. Figure 40 shows the drain-to-source charge injection
across the full signal range.
9

6 VDD = 15 V
VSS = ±15 V
Charge Injection (pC)

VDD = 10 V
3 VSS = ±10 V

±3 VDD = 12 V
VSS = 0 V
±6

±9
±15 ±10 ±5 0 5 10 15
Drain voltage (V) C011

Figure 40. Drain-to-Source Charge Injection vs Source or Drain voltage

9.3.3 Bidirectional Operation


The MUX50x are operable as both a mux or demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins of
the MUX50x are used either as input or output. Each MUX50x channel has very similar characteristics in both
directions.

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Feature Description (continued)


9.3.4 Rail-to-Rail Operation
A valid analog signal for the MUX50x ranges from VSS to VDD. The input signal to the MUX50x can swing from
VSS to VDD without any significant degradation in performance. The on-resistance of the MUX50x varies with
input signal, as shown in Figure 41.
250

VDD = 13.5 V VDD = 15 V


200 VSS = ±13.5 V VSS = ±15 V

On Resistance (Ÿ) 150

100

50 VDD = 18 V VDD = 16.5 V


VSS = ±18 V VSS = ±16.5 V
0
±20 ±15 ±10 ±5 0 5 10 15 20
Source or Drain Voltage (V) C001

Figure 41. On-Resistance vs Source or Drain Voltage

9.4 Device Functional Modes


When the EN pin of the MUX50x is pulled high, one of the switches is closed based on the state of the address
lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the address
lines. The EN pin can be connected to VDD (as high as 36 V).

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10 Applications and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information


The MUX50x family offers outstanding input/output leakage currents and ultralow charge injection. These devices
operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX50x is very low.
These features makes the MUX50x a precision, robust, high-performance analog multiplexer for high-voltage,
industrial applications.

10.2 Typical Application


Figure 42 shows a 16-bit, differential, four-channel, multiplexed, data-acquisition system. This example is typical
in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a four-channel differential mux. This application
example details the process for optimizing a precision, high-voltage, front-end drive circuit using the MUX509,
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Analog Inputs

REF3140 RC Filter OPA350 RC Filter

Bridge Sensor
Reference Driver
OPA192 Gain Network Gain Network

+
MUX509
Thermocouple
REF
+ OPA140 VINP
Charge
OPA192 Gain Network + Kickback ADS8864
Filter
Gain Network

Current Sensing VINM

Photo
LED Detector
High-Voltage Multiplexed Input High-Voltage Level Translation VCM
Optical Sensor

Copyright © 2016, Texas Instruments Incorporated

Figure 42. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion

10.2.1 Design Requirements


The primary objective is to design a ±20 V, differential, four-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.

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Typical Application (continued)


10.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 42. The
circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output
buffer, attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple
channels using a single ADC, providing a low-cost solution. This design systematically approaches each analog
circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal
input signal at each input channel.

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, see TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System
for High-Voltage Inputs with Lowest Distortion.

10.2.3 Application Curve


1.0
0.8
Integral Non-Linearity (LSB)

0.6
0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.8
±1.0
±20 ±15 ±10 ±5 0 5 10 15 20
ADC Differential Peak-to-Peak Input (V) C030

Figure 43. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block

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11 Power-Supply Recommendations
The MUX50x operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode). The
MUX508 and MUX509 operate equally well with either dual supplies (±5 V to ±18 V), or a single supply (10 V to
36 V). They also perform well with unsymmetric supplies such as VDD = 12 V and VSS = –5 V. For reliable
operation, use a supply decoupling capacitor with a capacitance between 0.1 µF to 10 µF at both the VDD and
VSS pins to ground.
The on-resistance of the MUX50x varies with supply voltage, as shown in Figure 44.
250

VDD = 13.5 V VDD = 15 V


On Resistance (Ÿ) 200 VSS = ±13.5 V VSS = ±15 V

150

100

50 VDD = 18 V VDD = 16.5 V


VSS = ±18 V VSS = ±16.5 V
0
±20 ±15 ±10 ±5 0 5 10 15 20
Source or Drain Voltage (V) C001

Figure 44. On-Resistance Variation With Supply and Input Voltage

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12 Layout

12.1 Layout Guidelines


Figure 45 shows an example of a PCB layout with the MUX508IPW, and Figure 46 shows an example of a PCB
layout with MUX509IPW. The guidelines provided in this section are also applicable to the SOIC MUX508ID and
MUX509ID package variants as well.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as small as possible. For the MUX509 differential signals, make sure the A inputs and B
inputs are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible and only make perpendicular crossings when necessary.

12.2 Layout Example

Via to
A2
EN

ground plane
AO

A1
Via to
ground plane

AO A1
C
EN A2
C
VSS GND
S1 MUX508IPW VDD
S2 S5
S3 S6
S4 S7
D S8

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Figure 45. MUX508IPW Layout Example

Via to Via to
ground plane ground plane
EN
AO

A1

AO A1
C C
EN GND
VSS VDD

S 1A MUX509 IPW S 1B
S 2A S 2B
S 3A S 3B
S 4A S 4B
DA DB

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Figure 46. MUX509IPW Layout Example

30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

Product Folder Links: MUX508 MUX509


MUX508, MUX509
www.ti.com SBAS758C – JANUARY 2016 – REVISED SEPTEMBER 2016

13 Device and Documentation Support

13.1 Documentation Support


13.1.1 Related Documentation
• ADS866x 12-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges
(SBAS492)
• OPAx140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz JFET Op Amp (SBOS498)
• OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with
e-trim™ (SBOS620)

13.2 Related Links


Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.

Table 3. Related Links


TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
MUX508 Click here Click here Click here Click here Click here
MUX509 Click here Click here Click here Click here Click here

13.3 Receiving Notification of Documentation Updates


To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

13.4 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 31


Product Folder Links: MUX508 MUX509
MUX508, MUX509
SBAS758C – JANUARY 2016 – REVISED SEPTEMBER 2016 www.ti.com

14 Mechanical, Packaging, and Orderable Information


The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

32 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

Product Folder Links: MUX508 MUX509


PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MUX508ID ACTIVE SOIC D 16 40 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 M36508D

MUX508IDR ACTIVE SOIC D 16 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 M36508D

MUX508IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 MUX508B

MUX508IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 MUX508B

MUX509ID ACTIVE SOIC D 16 40 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 M36509D

MUX509IDR ACTIVE SOIC D 16 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 M36509D

MUX509IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 MUX509C

MUX509IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 MUX509C

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MUX508IDR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
MUX508IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MUX509IDR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
MUX509IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MUX508IDR SOIC D 16 2500 366.0 364.0 50.0
MUX508IPWR TSSOP PW 16 2000 356.0 356.0 35.0
MUX509IDR SOIC D 16 2500 366.0 364.0 50.0
MUX509IPWR TSSOP PW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
MUX508ID D SOIC 16 40 517 7.87 635 4.25
MUX508IPW PW TSSOP 16 90 530 10.2 3600 3.5
MUX509ID D SOIC 16 40 517 7.87 635 4.25
MUX509IPW PW TSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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Copyright © 2022, Texas Instruments Incorporated

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