Features of 8255 Microprocessor:

Features of 8255 Microprocessor – Here we see programmable

peripheral interface (PPI), 8255, designed by Intel. It is a general
purpose programmable I/O device used for parallel data transfer. It has
24 I/O pins which can be grouped in three 8-bit parallel ports : Port A,
Port B and Port C. The eight bits of port C can be used as individual bits
or be grouped in two 4-bit ports : Cupper (CU) and Clower (CL).
The 8255, primarily, can be programmed in two basic modes : Bit
Set/Reset (BSR) mode and I/O mode. The BSR mode is used to set or
reset the bits in port C.
The I/O mode is further divided into three modes :
Mode 0 : Simple Input/Output
Mode 1 : Input/Output with handshake
Mode 2 : Bi-directional I/O data transfer
The function of I/O pins (input or output) and modes of operation of
I/O ports can be programmed by writing proper control word in the
control word register. Each bit in the control word has a specific
meaning and the status of these bits decides the function and operating
mode of the I/O ports.
The Features of 8255 Microprocessor are namely,
1. The 8255A is a widely used, programmable, parallel I/O device.
2. It can be programmed to transfer data under various conditions,
from simple I/O to interrupt I/O.
3. It is compatible with all Intel and most other microprocessors.
4. It is completely TTL compatible.
5. It has three 8-bit ports : Port A, Port B, and Port C, which are
arranged in two groups of 12 pins. Each port has an unique address,
and data can be read from or written to a port. In addition to the
address assigned to the three ports, another address is assigned to
the control register into which control words are written for
programming the 8255 to operate in various modes.
6. Its bit set/reset mode allows setting and resetting of individual bits of
Port C.
7. The 8255 can operate in 3 I/O modes : (i) Mode 0, (ii) Mode 1, & (iii)
Mode 2.
 a) In Mode 0, Port A and Port B can be configured as simple 8-bit input
or output ports without handshaking. The two  halves of Port C can be
programmed separately as 4-bit input or output ports.
 b) In Mode 1, two groups each of 12 pins are formed. Group A consists
of Port A and the upper half of Port C while Group  B consists of Port B
and the lower half of Port C. Ports A and B can be programmed as 8-bit
Input or Output ports with three lines of Port C in each group used for
handshaking.
8. In Mode 2, only Port A can be used as a bidirectional port. The
handshaking signals are provided on five lines of Port C (PC 3 – PC7 ). Port
B can be used in Mode 0 or in Mode 1.
8. All I/O pins of 8255 has 2.5 mA DC driving capacity (i.e.
sourcing current of 2.5 mA).
8255 Pin Diagram:

Fig. 14.1 shows the 8255 Pin Diagram of Microprocessor.

8255 Block Diagram:

Fig. 14.2 shows the internal 8255 block diagram of 8255 Pin Diagram
Microprocessor. It consists of data bus buffer, control logic and Group A
and Group B controls.
Data Bus Buffer:

This tri-state bi-directional buffer is used to interface the internal data

bus of 8255 Pin Diagram to the system data bus. Input or Output
instructions executed by the CPU either Read data from, or Write data
into the buffer. Output data from the CPU to the ports or control
register, and input data to the CPU from the ports or status register are
all passed through the buffer.
Control Logic:

The control logic block accepts control bus signals as well as inputs
from the address bus, and issues commands to the individual group
control blocks (Group A control and Group B control). It issues
appropriate enabling signals to access the required data/control words
or status word. The input pins for the control logic section are
described here.
Group A and Group B Controls:

Each of the Group A and Group B control blocks receives control words
from the CPU and issues appropriate commands to the ports associated
with it. The Group A control block controls Port A and PC 7-PC4 while the
Group B control block controls Port B and PC3-PC0.
Port A :

This has an 8-bit latched and buffered output and an 8-bit input latch. It
can be programmed in three modes: mode 0, mode 1 and mode 2.
Port B :

This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It
can be programmed in mode 0 and mode 1.
Port C :

This has one 8-bit unlatched input buffer and an 8-bit output
latch/buffer. Port C can be splitted into two parts and each can be used
as control signals for ports A and B in the handshake mode. It can be
programmed for bit set/reset operation.
Modes of Operation of 8255 Microprocessor:

Bit Set-Reset (BSR) Mode:

The individual bits of Port C can be set or reset by sending out a single
OUT instruction to the control register. When Port C is used for
control/status operation, this feature can be used to set or reset
individual bits.
I/O Modes:

Mode 0 : Simple input/output:

In this mode, ports A and B are used as two simple 8-bit I/O ports and
Port C as two 4-bit ports. Each port (or half – port, in case of C) can be
programmed to function as simply an input port or an output port. The
input/output features in Mode 0 are as follows :
1. Outputs are latched.
2. 2. Inputs are buffered, not latched.
3. Ports do not have handshake or interrupt capability.
Mode 1 : Input/Output with handshake:

In this mode, input or output data transfer is controlled by handshaking

signals. Handshaking signals are used to transfer data between devices .
whose data transfer speeds are not same. For example, computer can
send data .to the printer with large speed but printer can’t accept data
and print data with this rate. So computer has to send data with the
speed with which printer can accept. This type of data transfer is
achieved by using handshaking signals along-with data signals. Fig. 14.3
shows data transfer between computer and printer using handshaking
signals.
These handshaking signals are used to tell computer whether printer is
ready to accept the data or not. If printer is ready to accept the data
then after sending data on data bus, computer uses another
handshaking signal (STB) to tell printer that valid data is available on
the data bus.
The 8255 Pin Diagram mode 1 which supports handshaking has
following features.
1. Two ports (A and B) function as 8-bit I/O ports. They, can be
configured either as input or output ports.
2. Each port uses three lines from Port C as handshake signals. The
remaining two lines of. Port C can be used for simple I/O
functions.
3. Input and output data are latched.
4. Interrupt logic is supported.
5. Mode 2 : Bi-directional I/O data transfer:
This mode allows bi-directional data transfer (transmission and
reception) over a single 8-bit data bus using handshaking signals. This
feature is available only in Group A with Port A as the 8-bit bidirectional
data bus; and PC3 – PC7 are used for handshaking purpose. In this mode,
both inputs and outputs are latched. Due to use of a single 8-bit data
bus for bi-directional data transfer, the data sent out by the CPU
through Port A appears on the bus connecting it to the peripheral, only
when the peripheral requests it. The remaining lines of Port C i.e. PC 0-
PC2 can be used for simple I/O functions. The Port B can be
programmed in mode 0 or in mode 1. When Port B is programmed in
mode 1, PC0-PC2 lines of Port C are used as handshaking signals.
Control Word Formats:

A high on the RESET pin causes all 24 lines of the three 8-bit ports to be
in the input mode. All flip-flops are cleared and the interrupts are reset.
This condition is maintained even after the RESET goes low. The ports
of the 8255 Pin Diagram can then be programmed for any other mode
by writing a single control word into the control register, when
required.
For Bit Set/Reset Mode:

Fig. 14.4 shows bit set/reset control word format.

The eight possible combinations of the states of bits D 3 – D1 (B2 B1 B0) in

the Bit Set-Reset format (BSR) determine particular bit in PC 0 –
PC7 being set or reset as per the status of bit D 0. A BSR word is to be
written for each bit that is to be set or reset. For example, if bit PC 3 is to
be set and bit PC4 is to be reset, the appropriate BSR words that will
have to be loaded into the control register will be, 0XXX0111 and
0XXX1000, respectively, where x is don’t care.
The BSR word can also be used for enabling or disabling interrupt
signals generated by Port C when the 8255 Pin Diagram is programmed
for Mode 1 or 2 operation. This is done by setting or resetting the
associated bits of the interrupts. This is described in detail in next
section.

8255 Programming and Operation:

The 8255 Programming and Operation are follows

Programming in Mode 0:

The Ports A, B and C can be configured as simple input or output ports

by writing the appropriate control word in the control word register. In
the control word, D7 is set to ‘1’ (to define a mode set operation) and
D6, D5 and D2 are all set to ‘0’ to configure all the ports in Mode 0
operation The status of bits D4, D3, D1 and D0 then determine (refer to
Fig. 14.5) whether the corresponding ports are to be configured as
Input or Output.
For example in mode 0, if Port A and Port B are to operate as output
ports with Port C lower as input, and Port C upper as output, the
control word that will have to be loaded into the control register will be
as follows.
As mernoned earlier, this mode provides simple input and output
operations for each of the three ports. No handshaking is required, data
is simply written to or read from a specified port.
INPUT MODE :

Fig. 14.6 shows the timing diagram for mode 0 input mode.

After initialization of 8255 Programming and Operation in the input

mode 0, CPU can read data through the input port by initiating read
command with proper port address. Read command activates RD
signal. Upon activation of RD signal CPU reads the data from the
selected input port into the CPU register.
OUTPUT MODE :

Fig. 14.7 shows the timing diagram for mode 0 output mode.
After initialization of 8255 in the output mode 0, CPU can write data
into the output port by initiating write command with proper port
address. CPU sends data on the data bus and upon activation of WR
signal, data on the data bus gets latched on the selected output port.
Mode 0 Configurations :

Programming in Mode 1 (Input / Output With Handshake):

Both Group A and Group B can operate in Mode 1, either together, or

individually, with each port containing an 8-bit latched Input or Output
data port, and a 4-bit port which is used for control and status of the 8-
bit port.
When Port A is to be programmed as an input port, PC 3 , PC4 and
PC5 are used for control. PC6 and PC7 are not used and can be Input or
Output, as programmed by bit D3 of the control word. When Port A is
programmed as an output port, PC3 , PC6, and PC7 are used for control
and PC4 and PC5 can be Input or Output, as programmed by bit D 3, of
the control word.
When port B is to be programmed as an input or output port, PC 0  ,
PC1 and PC2 are used for control.
Mode 1 Input Control Signals :

STB (Strobe Input) : This is an active low input signal for 8255
Programming and Operation and output signal for the input device. The
input device activates this signal to indicate CPU that the data to be
read is already sent on the port lines of 8255 port. Upon activation of
this signal 8255 loads the data from the input port lines into the input
buffer of that port.
IBF (Input Buffer Full) : This is an active high output signal for 8255 and
an input signal for input device. This signal is generated by 8255
Programming and Operation in response to STB signal as an
acknowledgment to input device. It also indicates to the input device
that the input buffer is full and it is not ready to accept next byte from
the input device. Therefore input device sends data on the port lines
only when IBF signal is not active. The IBF signal is deactivated when
CPU reads the data from input buffer of the respective port by
activation of RD signal.
INTR (Interrupt Request) : This is an active high output signal generated
by 8255. A ‘high’ on this output can be used to interrupt the CPU when
an input device is requesting service. The 8255 Programming and
Operation sets the INTR when STB signal is ‘one’, IBF signal is ‘one’ and
INTE is ‘one’, indicating CPU that the data from the input device is
available in the input buffer. This signal is reset by the falling edge of
the RD signal i.e. immediately after reading the data from the input
buffer.
INTE (Interrupt Enable) flip flop is used to enable or disable INTR
(Interrupt request) signal. If INTE flip-flop is set, the interrupt request is
generated depending on the status of STB and IBF signals. If INTE flip
flop is reset, the interrupt request is not generated, allowing masking
facility for the interrupt.
Mode 1 : Port A Input Operation :

Fig. 14.8 (a) (see Fig. on next page) shows Port A as an input port along
with the control word and control signals (for handshaking with a
peripheral). When the control word (as in Fig. 14.8 (a) is loaded into the
control register, Group A is configured in Mode 1 with Port A as an
input port. Port A can accept parallel data from a peripheral (like a
keyboard) and this data can be read by the CPU. The peripheral first
loads data into Port by making the STB A input low. This latches the data
placed by the peripheral on the common data bus into Port A. Port A
acknowledges reception of data by making IBF A (Input Buffer Full) high.
IBFA is set when the STBA input is made low, as shown in Fig. 14.8 (b).
INTRA is an active high output signal which can be used to interrupt the
CPU so that the CPU can suspend its current operation and read the
data written into Port A by the peripheral. INTR A can be enabled or
disabled by the INTEA flip-flop which is controlled by Bit Set-Reset
operation of PC4. INTRA is set (if enabled by setting the INTE A flip-flop)
after the STBA has gone high again, and if IBFA is high.
On receipt of the interrupt, the CPU can be forced to read Port A. The
falling edge of the RD input resets IBFA and it goes low. This can be
used to indicate to the peripheral that the input buffer is empty and
that data can again be loaded into it.
Mode 1 : Port B Input operation:

Fig. 14.9 shows Port B as an input port (when in Mode 1). The timing
diagram and operation of Port B is similar to that of Port A except that
it uses different bits of Port C for control. INTE B is controlled by Bit
Set/Reset of PC2.

If the CPU is busy with other system operations, it can read data from
the input port when it is interrupted. This is often called Interrupt
driven I/O. However, if the CPU is otherwise not busy with other jobs, it
can continuously poll (read) the status word to check for an IBF A. This is
often called Program Controlled I/O. The status word is accessed by
reading Port C (A 1  A 0 must be 10, RD and CS must be low).. The status
word format when Ports A and B are input ports in Mode 1, is shown in
Fig. 14.10.

Mode 1 : Output control signals:

1.OBF (Output Buffer Full) :

This is an active low output signal for 8255 Programming and Operation
and input signal for the output device. The 8255 activates this signal to
indicate output device that data is available on the output port. Upon
activation  of OBF signal, output device reads data from the output port
and acknowledges it by ACK signal. The OBF signal is activated at the
rising edge of the WR signal and de-activated at the falling edge of the
ACK signal.
2.ACK (Acknowledge Input):

This is an active low input signal for 8255 and output signal for the
output device. The output device generates this signal to indicate 8255
that the data from port A or Port B has been accepted.
3.INTR (Interrupt Request) :

This is an active high output signal generated by 8255 A ‘high’ on this

output can be used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. The 8255 Programming and
Operation sets the INTR when ACK signal is ‘one’, OBF is ‘one’ and INTE
is ‘one, indicating that the output device is ready to accept next data
byte. This signal is reset by the falling edge of the WR signal i.e.
immediately after sending the data to the output port.
INTE (Interrupt Enable) flip-flop is used to enable or disable INTR
(Interrupt Request) signal. If  INTE  flip  flop is set, the interrupt request
is generated depending on the status of ACK and OBF signals. If INTE
flip flop is reset, the interrupt request is not generated, allowing
masking facility for the interrupt.
Mode 1 : Port A output operation:
Fig. 14.11 (a) shows Port A configured as an output port (when in Mode
1) along with the control word and control signals (for handshaking
with a peripheral). When the control word (as in Fig. 14.11 (a)) is loaded
into the control register, Group A is configured in Mode 1 with Port A as
an output port The CPU can send data to a peripheral (like a display
device) through Port A of the 8255.
The OBFA output (Output Buffer Full) goes  low on the rising edge of the
WR signal (when the CPU writes data into the 8255). The OBF A output
from 8255 Programming and Operation can be used as a strobe input
to the peripheral to latch the contents of Port A. The peripheral
responds to the receipt of data by making the ACK A input of the 8255
low, thus acknowledging that it has received the data sent by the CPU
through  Port A. The ACKA low sets the OBFA signal, which can be polled
by the CPU through OBFA of the status word to load the next data when
it is high again.

INTRA is an active high output of the 8255 Programming and Operation

which is made high. (if the associated INTE A flip-flop is set) when ACKA is
made high again by the peripheral, and when OBF A goes high again (see
timing diagram in Fig. 14.11). It can be used to interrupt the CPU
whenever the output buffer is empty. It is reset by the falling edge of
WR when the CPU writes data onto Port A. It can be enabled or
disabled by writing a ‘1’ or a’0′ respectively to PC6 in the BSR mode.
Mode 1 : Port B output operation:

Fig. 14.12 shows Port B as an output port when in Mode 1. The

operation of Port B is similar to that of Port A. INTR A is controlled by
writing a ‘1’ or a ‘0’ to PC2 in the BSR mode. The status word is accessed
by issuing a Read to Port C. The format of the status word when Ports A
and B are Output ports in Mode 1 is shown in Fig. 14.13.
Programming in Mode 2 (Strobes Bi-directional Bus I/O):

When the 8255 Programming and Operation is operated in Mode 2 (by

loading the appropriate control word), Port A can be used as a bi-
directional 8-bit I/O bus using for handshaking. Port B can be
programmed in Mode 0 or in Mode 1. When Port B is programmed in
mode 1, PC0 – PC2 lines of Port C are used as handshaking signals.

Fig. 14.14 shows the control word that should be loaded into the
control port to configure 8255 in Mode 2,
Mode 2 : Control signals:

INTR (Interrupt Request).: A ‘high’ on this output can be used to

interrupt the CPU for input or output operations.
Output Control Signals :

OBFA (Output Buffer Full):

This is an active low output which indicates that the CPU has written
data into Port A.
ACKA (Acknowledge):

This is an active low input signal (generated by the peripheral) which

enables the tri-state output buffer of Port A and makes Port A data
available to the peripheral. In Mode 2, Port A outputs are in tri-state
until enabled.
INTE 1:

This is the flip-flop associated with Output Buffer Full. INTE 1 can be
used to enable or disable the interrupt by setting or resetting PC 6 in the
BSR Mode.
Input Control Signals:

STB (Strobe Input):

This is an active low input signal which enables Port A to latch the data
available at its input.
IBF (Input Buffer Full Flip-Flop):

This is an active high output which indicates that data has been loaded
into the input latch of Port A.
INTE 2:

This is an Interrupt enable flip-flop associated with Input Buffer Full. It

can be controlled by setting or resetting PC4 in the BSR Mode.
Mode 2 : Port A operation:

Fig. 14.15 (see Fig. on next page) shows Port A and associated control
signals when 8255 is in Mode 2. Interrupts are generated for both
output and input operations on the same INTRA (PC3) line.
Status Word In Mode 2:

The status word for Mode 2 (accessed by reading Port C) is shown in

Fig. 14.15. D7 – D3 of the status word carry information about OBF A,
INTE1, IBFA ,INTE2 ,INTRA .The status of the bits D2 – D0 depends on the
mode setting of Group B. If B is programmed in Mode 0, D 2 – D0 are the
same as PC2 – PC0 (simple I/O); however if B is in Mode 1, D 2 – D0 carry
information about the control signals for Port B (as in Fig. 14.10, or Fig.
14.13), depending upon whether Port B is an Input port or Output port
respectively.
For I/O Mode:

The mode definition format for I/O mode is shown in Fig. 14.5. The
control words for both, mode definition and Bit Set –Reset are loaded
into the same control register, with bit D 7 used for specifying whether
the word loaded into the control register is a mode definition word or
Bit Set-Reset word. If D7 is high, the word is taken as a mode definition
word, and if it is low, it is taken as a Bit Set-Reset word. The appropriate
bits are set or reset depending on the type of operation desired, and
loaded into the control register.
8255 Interfacing with 8086:

Fig. 14.17 shows the 8255 Interfacing with 8086 Microprocessor and
Interfacing 8255 with 8085 Microprocessor in I/O mapped I/O
technique. Here RD and WR signals are activated when IO/M signal is
high, indicating I/O bus cycle. Reset out signal from 8085 is connected
to the RESET signal of the 8255.

Interfacing 8255 In Memory Mapped I/O:

Fig. 14.18 shows the interfacing of 8255 with 8085 in memory mapped
I/C technique. Here RD and WR signals are activated when 10/M signal
is low, indicating memory bus cycle. To get absolute address, all
remaining address lines (A15 – A2) are used to decode the address for
8255. Other signal connections are same as in I/C mapped I/O.
8255 Interfacing with 8086 in I/O Mapped I/O Mode:

The 8086 has four special instructions IN, INS, OUT, and OUTS to
transfer data through the input/output ports in I/O mapped I/O system.
M/IO signal is always low when 8086 is executing these instructions. So
M/IO signal is used to generate separate addresses for, memory and
input/output. Only 256 (28) I/O addresses can be generated when direct
addressing method is used. By using indirect address method this range
can be extended upto 65536 (216) addresses.
Fig. 14.19 shows the 8255 Interfacing with 8086 in I/O mapped I/O
technique. Here, RD and WR signals are activated when M/IO signal is
low, indicating I/O bus cycle. Only lower data bus (D 0 — D7) is used as
8255 is 8-bit device. Reset out signal from clock generator is connected
to the Reset signal of the 8255. In case of interrupt driven I/O INTR
signal (PC3 or PC0) from 8255 is connected to INTR input of 8088.
8255 Interfacing with 8086 in Memory Mapped I/O:

In this type of I/O interfacing, the 8086 uses 20 address lines to identify
an I/O device; an I/O device is connected as if it is a memory register.
The 8086 uses same control signals and instructions to access I/O as
those of memory. Fig. 14.20 shows the 8255 Interfacing with 8086 in
memory mapped I/O technique. Here RD and WR signals are activated
when M/IO signal is high, indicating memory bus cycle. Address lines
A0 – A1 are used by 8255 for internal decoding. To get absolute address,
all remaining address lines (A3 – A19) are used to decode the address for
8255. Other signal connections are same as in I/O napped I/O.
Applications:

In this section we discuss many useful applications like keyboard and

display interface, traffic light control, printer interface and so on.