Cam Intel 8255A

INTEL 8255A
PROGRAMMABLE
PERIPHERAL
INTERFACE
Gaganjot kaur
CRN:2215040
Programmable peripheral interface
8255
PPI 8255 is a general purpose programmable I/O device
designed to interface the CPU with its outside world such as
keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor. It
consists of three 8-bit bidirectional I/O ports i.e. PORT A,
PORT B and PORT C. We can assign different ports as
input or output functions.
PIN DIAGRAM
CS
It stands for Chip Select. A LOW on this input
selects the chip and enables the
communication between the 8255A and the
CPU. It is connected to the decoded address,
and A0 & A1 are connected to the
microprocessor address lines.
WR
It stands for write. This control signal enables
the write operation. When this signal goes
low, the microprocessor writes into a selected
I/O port or control register.
RESET
This is an active high signal. It clears the
control register and sets all ports in the
input mode.
OPERATING MODES
•Mode 0 − In this mode, Port A and B is used as two 8-bit ports and
Port C as two 4-bit ports. Each port can be programmed in either
input mode or output mode where outputs are latched and inputs
are not latched. Ports do not have interrupt capability.
•Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports.

They can be configured as either input or output ports. Each port
uses three lines from port C as handshake signals. Inputs and
outputs are latched.
•Mode 2 − In this mode, Port A can be configured as the

bidirectional port and Port B either in Mode 0 or Mode 1. Port A
uses five signals from Port C as handshake signals for data
transfer. The remaining three signals from Port C can be used
either as simple I/O or as handshake for port B.
BLOCK DIAGRAM
BLOCK
DIAGRAM
Data Bus Buffer
It is a tri-state 8-bit buffer, which is used to interface the
microprocessor to the system data bus. Data is
transmitted or received by the buffer as per the
instructions by the CPU. Control words and status
information is also transferred using this bus.
Read/Write Control Logic

This block is responsible for controlling the
internal/external transfer of data/control/status
word. It accepts the input from the CPU address and
control buses, and in turn issues command to both
the control groups.
EXPLANATION
It consists of 40 pins and operates in +5V regulated power supply. Port C
is further divided into two 4-bit ports i.e. port C lower and port C upper
and port C can work in either BSR (bit set rest) mode or in mode 0 of
input-output mode of 8255. Port B can work in either mode 0 or in mode 1
of input-output mode. Port A can work either in mode 0, mode 1 or mode
2 of input-output mode. It has two control groups, control group A and
control group B. Control group A consist of port A and port C upper.
Control group B consists of port C lower and port B. Depending upon the
value if CS’, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in
control register (control word D0-D7).
Advantages:
Versatility: The PPI 8255 can be programmed to operate in a variety of modes,
which makes it a versatile component in many different systems. It provides three 8-
bit ports that can be configured as input or output ports, and supports multiple modes
of operation for each port.
Ease of use: The PPI 8255 is relatively easy to use and program, even for novice
programmers. The control register of the PPI can be programmed using simple
commands, which makes it easy to interface with other devices.
Compatibility: The PPI 8255 is widely used and has been around for many years,
which means that it is compatible with a wide range of devices and software.
Low cost: The PPI 8255 is a relatively low-cost component, which makes it an
affordable option for many different applications.
Disadvantages:
Limited functionality: While the PPI 8255 is versatile, it has limited functionality compared
to newer I/O interface components. It is not capable of high-speed data transfer and has
limited memory capacity.
Limited number of ports: The PPI 8255 provides only three 8-bit ports, which may not be
sufficient for some applications that require more I/O ports.
Limited resolution: The PPI 8255 provides only 8 bits of resolution for each port, which
may not be sufficient for some applications that require higher resolution.
Obsolete technology: While the PPI 8255 is still used in some applications, it is considered
an older technology and is being replaced by newer, more advanced I/O interface
components.
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INTEL 8255A

•Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports.

•Mode 2 − In this mode, Port A can be configured as the

Read/Write Control Logic

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