Tlv600X Low-Power, Rail-To-Rail In/Out, 1-Mhz Operational Amplifier For Cost-Sensitive Systems

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TLV6001, TLV6002, TLV6004

SBOS779D – JUNE 2016 – REVISED MAY 2017
TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive

Systems
1 Features 3 Description
•
1 Precision Amplifiers for Cost-Sensitive Systems The TLV600x family of single-, dual-, and quad-
channel operational amplifiers is specifically designed
• Low Quiescent Current: 75 µA/ch for general-purpose applications. Featuring rail-to-rail
• Supply Range: 1.8 V to 5.5 V input and output (RRIO) swings, low quiescent
• Input Voltage Noise Density: 28 nV/√Hz at 1 kHz current (75 μA, typical), wide bandwidth (1 MHz) and
• Rail-to-Rail Input and Output low noise (28 nV/√Hz at 1 kHz), this family is
attractive for a variety of applications that require a
• Gain Bandwidth: 1 MHz good balance between cost and performance, such
• Low Input Bias Current: 1 pA as consumer electronics, smoke detectors, and white
• Low Offset Voltage: 0.75 mV goods. The low-input-bias current (±1.0 pA, typical)
enables the TLV600x to be used in applications with
• Unity-Gain Stable megaohm source impedances.
• Internal RF and EMI Filter
The robust design of the TLV600x provides ease-of-
• Extended Temperature Range: use to the circuit designer: unity-gain stability with
–40°C to +125°C capacitive loads of up to 150 pF, integrated RF/EMI
rejection filter, no phase reversal in overdrive
2 Applications conditions, and high electrostatic discharge (ESD)
• Industrial and Consumer Electronics protection (4-kV HBM).
• Portable Equipment The devices are optimized for operation at voltages
• Portable Blood Glucose Systems as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V),
and are specified over the extended temperature
• Smoke Detectors range of –40°C to +125°C.
• White Goods
The single-channel TLV6001 is available in SC70-5
• Power Banks and SOT23-5 packages. The dual-channel TLV6002
is offered in SOIC-8 and VSSOP-8 packages, and the
CMRR and PSRR vs Temperature quad-channel TLV6004 is offered in a TSSOP-14
110 package.
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
105
PSRR Device Information(1)
100
PART NUMBER PACKAGE BODY SIZE (NOM)
95
SC70 (5) 2.00 mm × 1.25 mm
90 TLV6001
85 CMRR SOT-23 (5) 2.90 mm × 1.60 mm
80 SOIC (8) 4.90 mm × 3.91 mm

TLV6002
75 VSSOP (8) 3.00 mm × 3.00 mm
70 TLV6004 TSSOP (14) 5.00 mm × 4.40 mm
65 (1) For all available packages, see the orderable addendum at
VCM = ±0.2 V to 5.2 V
60 the end of the data sheet.
-50 -25 0 25 50 75 100 125
Temperature (oC) C001
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV6001, TLV6002, TLV6004
SBOS779D – JUNE 2016 – REVISED MAY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 15
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 16
3 Description ............................................................. 1 8.5 Input and ESD Protection ....................................... 16
4 Revision History..................................................... 2 9 Application and Implementation ........................ 17
9.1 Application Information............................................ 17
5 Device Comparison Table..................................... 3
9.2 Typical Application ................................................. 17
6 Pin Configuration and Functions ......................... 3
9.3 System Examples .................................................. 18
7 Specifications......................................................... 7
10 Power Supply Recommendations ..................... 19
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7 11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
7.3 Recommended Operating Conditions....................... 7
11.2 Layout Example .................................................... 20
7.4 Thermal Information: TLV6001 ................................. 8
7.5 Thermal Information: TLV6002 ................................. 8 12 Device and Documentation Support ................. 21
7.6 Thermal Information: TLV6004 ................................. 8 12.1 Documentation Support ........................................ 21
7.7 Electrical Characteristics: VS= 1.8 V to 5 V (±0.9 V to 12.2 Related Links ........................................................ 21
±2.75 V)...................................................................... 9 12.3 Receiving Notification of Documentation Updates 21
7.8 Typical Characteristics: Table of Graphs ................ 10 12.4 Community Resources.......................................... 21
7.9 Typical Characteristics ............................................ 11 12.5 Trademarks ........................................................... 21
8 Detailed Description ............................................ 14 12.6 Electrostatic Discharge Caution ............................ 21
8.1 Overview ................................................................. 14 12.7 Glossary ................................................................ 21
8.2 Functional Block Diagram ....................................... 14 13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision C (December 2016) to Revision D Page
• Changed inverting input pin to noninverting input pin in Pin Functions: TLV6001 table ....................................................... 3
• Changed inverting input pin to noninverting input pin in Pin Functions: TLV6001R table .................................................... 4
• Changed inverting input pin to noninverting input pin in Pin Functions: TLV6001U table .................................................... 4
• Changed "Sample and Buy" to "Order Now" in Related Links table ................................................................................... 21
Changes from Revision B (October 2016) to Revision C Page
• Changed all pin outs in Pin Configuration and Functions section to reflect correct pin names and order............................. 3
Changes from Revision A (July 2016) to Revision B Page
• Added TLV6001R pinout drawing to Pin Configurations and Functions section ................................................................... 4
• Added TLV6001U pinout drawing to Pin Configurations and Functions section ................................................................... 4
Changes from Original (June 2016) to Revision A Page
• Changed Product Status from Product Preview to Production Data ..................................................................................... 1

• Changed formatting of the Related Documentation section. ............................................................................................... 21
• Changed wording of the Receiving Notification of Documentation Updates section ........................................................... 21
2 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: TLV6001 TLV6002 TLV6004

TLV6001, TLV6002, TLV6004
www.ti.com SBOS779D – JUNE 2016 – REVISED MAY 2017
5 Device Comparison Table
PACKAGE-LEADS
NO. OF
DEVICE CHANNELS SC70 SOT-23 SOIC VSSOP TSSOP
TLV6001 1 5 5 — — —
TLV6002 2 — — 8 8 —
TLV6004 4 — — — — 14
6 Pin Configuration and Functions
TLV6001: DCK Package TLV6001: DBV Package

5-Pin SC70 5-Pin SOT-23
Top View Top View
+IN 1 5 V+ OUT 1 5 V+
+
V± 2 V± 2
±
±
±IN 3 4 OUT +IN 3 4 ±IN
Not to scale Not to scale
Pin Functions: TLV6001

PIN
DCK DBV I/O DESCRIPTION
NAME
(SC70) (SOT-23)
–IN 3 4 I Inverting input
+IN 1 3 I Noninverting input
OUT 4 1 O Output
V– 2 2 — Negative (lowest) power supply
V+ 5 5 — Positive (highest) power supply
Copyright © 2016–2017, Texas Instruments Incorporated Submit Documentation Feedback 3

TLV6001, TLV6002, TLV6004
TLV6001R: DBV Package

5-Pin SOT-23
Top View
OUT 1 5 V±
V+ 2
±
+IN 3 4 ±IN
Not to scale
Pin Functions: TLV6001R

PIN
I/O DESCRIPTION
NAME NO.
–IN 4 I Inverting input
+IN 3 I Noninverting input
OUT 1 O Output
V– 5 — Negative (lowest) power supply
V+ 2 — Positive (highest) power supply
TLV6001U: DBV Package

5-Pin SOT-23
Top View
+IN 1 5 V+
+
V± 2
±
±IN 3 4 OUT
Not to scale
Pin Functions: TLV6001U

PIN
I/O DESCRIPTION
NAME NO.
–IN 3 I Inverting input
+IN 1 I Noninverting input
OUT 4 O Output

TLV6001, TLV6002, TLV6004
TLV6002: D, DGK Packages

8-Pin SOIC, 8-Pin VSSOP
TLV6002 Top View
OUT A 1 8 V+
±IN A 2 7 OUT B
+IN A 3 6 ±IN B
V± 4 5 +IN B
Not to scale

PIN
DGK I/O DESCRIPTION
NAME D (SOIC)
(VSSOP)
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
V– 4 4 — Negative (lowest) power supply
V+ 8 8 — Positive (highest) power supply

TLV6001, TLV6002, TLV6004
TLV6004: PW Package
14-Pin TSSOP
Top View
OUT A 1 14 OUT D
±IN A 2 13 ±IN D
+IN A 3 12 +IN D
V+ 4 11 V±
+IN B 5 10 +IN C
±IN B 6 9 ±IN C
OUT B 7 8 OUT C
Not to scale

PIN
I/O DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
–IN B 6 I Inverting input, channel B
–IN C 9 I Inverting input, channel C
–IN D 13 I Inverting input, channel D
+IN A 3 I Noninverting input, channel A
+IN B 5 I Noninverting input, channel B
+IN C 10 I Noninverting input, channel C
+IN D 12 I Noninverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D

TLV6001, TLV6002, TLV6004
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage 7 V
Voltage (2)
Signal input pins, voltage (V–) – 0.5 (V+) + 0.5 V
Signal input pins, current (2) –10 10 mA
Current
Output short-circuit (3) Continuous mA
Operating, TA –40 150 °C
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage 1.8 5.5 V
TA Specified temperature range –40 125 °C

TLV6001, TLV6002, TLV6004
7.4 Thermal Information: TLV6001

TLV6001
THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) UNIT
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 228.5 281.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 99.1 91.6 °C/W
RθJB Junction-to-board thermal resistance 54.6 59.6 °C/W
ψJT Junction-to-top characterization parameter 7.7 1.5 °C/W
ψJB Junction-to-board characterization parameter 53.8 58.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

TLV6002
(1)
THERMAL METRIC D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 138.4 191.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.5 61.9 °C/W
RθJB Junction-to-board thermal resistance 78.6 111.9 °C/W
ψJT Junction-to-top characterization parameter 29.9 5.1 °C/W
ψJB Junction-to-board characterization parameter 78.1 110.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
report.

TLV6004
(1)
THERMAL METRIC PW (TSSOP) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 121.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.4 °C/W
RθJB Junction-to-board thermal resistance 62.8 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 62.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
report.

TLV6001, TLV6002, TLV6004
7.7 Electrical Characteristics: VS= 1.8 V to 5 V (±0.9 V to ±2.75 V) (1)

at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.75 4.5 mV
dVOS/dT VOS vs temperature TA = –40°C to 125°C 2 μV/°C
PSRR Power-supply rejection ratio 86 dB
INPUT BIAS CURRENT
IB Input bias current TA = 25°C ±1.0 pA
IOS Input offset current ±1.0 pA
INPUT IMPEDANCE
ZID Differential 100 || 1 MΩ || pF
ZIC Common-mode 1 || 5 1013Ω || pF
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VCM = –0.2 V to 5.7 V 60 76 dB
OPEN-LOOP GAIN
AOL Open-loop voltage gain 0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ 90 110
Phase margin VS = 5.0 V, G = +1 65 degrees
OUTPUT
RL = 100 kΩ 5 mV
VO Voltage output swing from supply rails
RL = 2 kΩ 75 100 mV
ISC Short-circuit current ±15 mA
RO Open-loop output impedance 2300 Ω
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1 MHz
SR Slew rate 0.5 V/µs
tS Settling time To 0.1%, VS = 5.0 V, 2-V step , G = +1 5 μs
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 6 μVPP
en Input voltage noise density f = 1 kHz 28 nV/√Hz
in Input current noise density f = 1 kHz 5 fA/√Hz
POWER SUPPLY
VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V
IQ Quiescent current per amplifier IO = 0 mA, VS = 5.0 V 75 100 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 10 µs
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over-
temperature limits are based on characterization and statistical analysis.

TLV6001, TLV6002, TLV6004
7.8 Typical Characteristics: Table of Graphs

Table 1. Table of Graphs
TITLE FIGURE
Open-Loop Gain and Phase vs Frequency Figure 1
Quiescent Current vs Supply Voltage Figure 2
Offset Voltage Production Distribution Figure 3
Offset Voltage vs Common-Mode Voltage (Maximum Supply) Figure 4
CMRR and PSRR vs Frequency (RTI) Figure 5
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V) Figure 6
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V) Figure 7
Input Bias and Offset Current vs Temperature Figure 8
Open-Loop Output Impedance vs Frequency Figure 9
Maximum Output Voltage vs Frequency and Supply Voltage Figure 10
Output Voltage Swing vs Output Current (over Temperature) Figure 11
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V) Figure 12
Small-Signal Step Response, Noninverting (1.8 V) Figure 13
Small-Signal Step Response, Noninverting ( 5.5 V) Figure 14
Large-Signal Step Response, Noninverting (1.8 V) Figure 15
Large-Signal Step Response, Noninverting ( 5.5 V) Figure 16
No Phase Reversal Figure 17
EMIRR IN+ vs Frequency Figure 18

TLV6001, TLV6002, TLV6004
7.9 Typical Characteristics

at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
140 180 60
120 Gain 58
Phase
Quiescent Current (µA/ch)

56
100 CL=10pF
C L = 10 pF 135
54
80
Gain (dB)
Phase (o)
52
60 90 50
40 48
46
20 45
C L = 100 pF
CL=100pF 44
0
42
-20 0 40
1 10 100 1k 10k 100k 1M 10M 100M 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Frequency (Hz) Supply Voltage (V) C003
Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Quiescent Current vs Supply
9 1500
Typical Units
8 1200 VS = 5.5 V
900
Percent of Amplifiers (%)
7
Offset Voltage (µV)
600
6
300
5
0
4
-300
3 -600
2 -900
1 -1200
0 -1500
0
2
0.5
1.5
2.5
-2
-1
-2.5
-1.5
-0.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Offset Voltage (mV) C005 Common-Mode Voltage (V) C007
Figure 3. Offset Voltage Production Distribution Figure 4. Offset Voltage vs Common-Mode Voltage
120
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
100
Voltage Noise (1 µV/div)
80
+PSRR
60
CMRR
40
20
-PSRR
0
Time (1 s/div)
10 100 1k 10k 100k 1M
Frequency (Hz) C009 C011
Figure 5. CMRR and PSRR vs Frequency Figure 6. 0.1-Hz to 10-Hz Input Voltage Noise
(Referred-to-Input)

TLV6001, TLV6002, TLV6004
Typical Characteristics (continued)

1000 200
VS = 1.8 V 150 IBN
Input Bias Current (pA)

9ROWDJH 1RLVH Q9 ¥+]
100 100
IBP
50
10 0
VS = 5.5 V
-50 IOS
1 -100
1 10 100 1k 10k 100k -50 -25 0 25 50 75 100 125
Frequency (Hz) C012 Temperature (oC) C014
Figure 7. Input Voltage Noise Spectral Density vs Frequency Figure 8. Input Bias and Offset Current vs Temperature
100k 6
RL = 10 k
CL = 10 pF
5
VS = 5.5 V
Output Impedance ( )
VS = 1.8 V Output Voltage (V) 4
VS = 1.8 V
10k 3
1
VS = 5.5 V
1000 0
1 10 100 1k 10k 100k 1000 10k 100k 1M
Frequency (Hz) C015 Frequency (Hz) C016
Figure 9. Open-Loop Output Impedance vs Frequency Figure 10. Maximum Output Voltage vs Frequency and
Supply Voltage
3 40
2 G = +10 V/V
Output Voltage Swing (V)
1 20
Gain (dB)
G = +1 V/V
+125 oC
+125oC
0 +25oC
+25 oC -40 oC
-40oC
-1 0
-2 G = -1 V/V
VS = 1.8 V
-3 -20
0 5 10 15 20 10 100 1k 10k 100k 1M 10M 100M
Output Current (mA) C017 Frequency (Hz) C018
Figure 11. Output Voltage Swing vs Output Current (Over Figure 12. Closed-Loop Gain vs Frequency (Minimum
Temperature) Supply)

TLV6001, TLV6002, TLV6004
Typical Characteristics (continued)

G = +1 V/V CL = 100 pF G = +1 V/V

VS = 1.8V VS = 5.5 V CL = 100 pF
VCM = 0.5V VIN RL = 10 k VIN
RL = 10 kŸ
Voltage (25 mV/div)

Voltage (25 mV/div)
CL = 10 pF
CL = 10 pF
Time (1 µs/div)
Time (1 µs/div) C004
C023
Figure 13. Small-Signal Pulse Response Figure 14. Small-Signal Pulse Response
(Minimum Supply) (Maximum Supply)
G = +1 V/V G = +1 V/V
VS = 1.8 V VS = 5.5 V
RL = 10 k RL = 10 k
Voltage (250 mV/div)
Voltage (250 mV/div)

VOUT
VOUT
VIN
VIN
Time (2.5 µs/div) Time (2.5 µs/div)

C024 C025
Figure 15. Large-Signal Pulse Response Figure 16. Large-Signal Pulse Response
(Minimum Supply) (Maximum Supply)
120
PRF = -10 dBm
VSUPPLY = 5 V
100 VCM = 2.5 V
Voltage (1 V/div)
EMIRR IN+ (dB)
80
60
VOUT 40
20
VIN
0
Time (125 µs/div)
10 100 1000 10000
C028 Frequency (MHz) C033
Figure 17. No Phase Reversal Figure 18. EMIRR IN+ vs Frequency

TLV6001, TLV6002, TLV6004
8 Detailed Description
8.1 Overview
The TLV600x family of operational amplifiers are general-purpose, low-cost devices that are suitable for a wide
range of portable applications. Rail-to-rail input and output swings, low quiescent current, and wide dynamic
range make the op amps well-suited for driving sampling analog-to-digital converters (ADCs) and other single-
supply applications.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+ VIN–
VBIAS1 Class AB
Control VO
Circuitry
VBIAS2
V–
(Ground)
Copyright © 2017, Texas Instruments Incorporated

TLV6001, TLV6002, TLV6004
8.3 Feature Description

8.3.1 Operating Voltage
The TLV600x series is fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters that vary
with supply voltage are illustrated in the Typical Characteristics section.
8.3.2 Rail-to-Rail Input

The input common-mode voltage range of the TLV600x series extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel
pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small
transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region
may vary up to 300 mV with process variation. Thus, the transition region (both stages on) may range from
(V+) – 1.7 V to (V+) – 1.5 V on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this
transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to device
operation outside this region.
8.3.3 Rail-to-Rail Output

Designed as a micro-power, low-noise operational amplifier, the TLV600x delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. For resistive loads up to 100 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails, as shown in Figure 11.
8.3.4 Common-Mode Rejection Ratio (CMRR)

CMRR for the TLV600x is specified in several ways so the best match for a given application may be used; see
Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transition region
[VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when the
application requires the use of one of the differential input pairs. Second, the CMRR over the entire common-
mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through the
transition region, as shown in Figure 4.
8.3.5 Capacitive Load and Stability

The TLV600x is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the TLV600x may become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or
not an amplifier is stable in operation. An op amp in the unity-gain (!~ +1-V/V) buffer configuration that drives a
capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the TLV600x remains stable with a pure capacitive load up to
approximately 1 nF. The equivalent series resistance (ESR) of some capacitors (CL greater than 1 μF) is
sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing
the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased
capability is evident when observing the overshoot response of the amplifier at higher voltage gains.

TLV6001, TLV6002, TLV6004
Feature Description (continued)

One technique for increasing the capacitive load drive capability of the amplifier when it operates in a unity-gain
configuration is to insert a small resistor, typically 10!~ !~ -Ω to 20!~ !~ -Ω, in series with the output, as shown in
Figure 19. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads.
One possible problem with this technique is that a voltage divider is created with the added series resistor and
any resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the
output that reduces the output swing.
V+
RS
Device VOUT
VIN 10 W to
20 W RL CL
Figure 19. Improving Capacitive Load Drive
8.3.6 EMI Susceptibility and Input Filtering

Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the dc offset observed at the amplifier output may shift from the nominal value
while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions may be affected by EMI, the signal input pins are likely to be the most
susceptible. The TLV600x family incorporates an internal input low-pass filter that reduces the amplifiers
response to EMI. Common-mode and differential mode filtering are provided by this filter. The filter is designed
for a cutoff frequency of approximately 35 MHz (–3 dB), with a !~ roll-off!~ rolloff of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 18 illustrates the results of this
testing on the TLV600x family. Detailed information may be found in EMI Rejection Ratio of Operational
Amplifiers (SBOA128), available for download from www.ti.com.
8.4 Device Functional Modes

The TLV600x have a single functional mode. The devices are powered on as long as the power-supply voltage is
between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
8.5 Input and ESD Protection

The TLV600x incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. The ESD protection diodes provide in-circuit, input overdrive protection, as long as the
current is limited to 10 mA, as stated in the Absolute Maximum Ratings table. Figure 20 shows how a series
input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device VOUT
VIN
5 kW
Figure 20. Input Current Protection

TLV6001, TLV6002, TLV6004
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The TLV600x is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for
portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected
to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
TLV600x to be used in any single-supply application.
9.2 Typical Application

A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 21. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier makes negative input voltages positive on the
output. In addition, amplification may be added by selecting the input resistor RI and the feedback resistor RF.
RF
VSUP+
RI
VOUT
+
VIN
VSUP±
Figure 21. Application Schematic
9.2.1 Design Requirements

The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must be considered.
For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at ±2.5 V is
sufficient to accommodate this application.
9.2.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:
VOUT
AV
VIN (1)
1.8
AV 3.6
0.5 (2)

TLV6001, TLV6002, TLV6004
Typical Application (continued)

When the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that large resistors
(hundreds of kilohms) draw the smallest current but generate the highest noise. Small resistors (100s of ohms)
generate low noise but draw high current. This example uses 10 kΩ for RI, meaning 36 kΩ is used for RF. The
values are determined by Equation 3:
RF
AV
RI (3)
9.2.3 Application Curve
2
Input
1.5 Output
0.5
Voltage (V)
-0.5
-1
-1.5
-2
Time
Figure 22. Inverting Amplifier Input and Output
9.3 System Examples

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as shown in Figure 23.
RG RF
R1 VOUT
VIN
C1
1
f-3 dB =
2pR1C1
VOUT
VIN
= 1+
RF
RG ( (( 1
1 + sR1C1 (
Figure 23. Single-Pole Low-Pass Filter

TLV6001, TLV6002, TLV6004
System Examples (continued)

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter may be used for this
task, as shown in Figure 24. For best results, the amplifier must have a bandwidth that is eight to 10 times the
filter frequency bandwidth. Failure to follow this guideline may result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
R1 R2
Q = Peaking factor
VIN (Butterworth Q = 0.707)
VOUT
C2 1
f-3 dB =
2pRC
RF
RF
RG
RG =
( 2-
1
Q (
Figure 24. Two-Pole, Low-Pass, Sallen-Key Filter
10 Power Supply Recommendations

The TLV600x is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics presents parameters that may exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V may permanently damage the device. (See the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.

TLV6001, TLV6002, TLV6004
11 Layout
11.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise may propagate into analog circuitry through the power pins of the circuit and the operational
amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, refer to Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better
than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input in order to minimize parasitic capacitance, as shown in Figure 25.
• Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example

Run the input traces
as far away from VS+
the supply lines
VIN
as possible.
VS± +IN V+ GND
V± Use a low-ESR,
Use a low-ESR, ceramic bypass
ceramic bypass capacitor.
capacitor. RG
±IN OUT VOUT
GND
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Figure 25. Operational Amplifier Board Layout for Noninverting Configuration
VIN +
RG VOUT
RF
Figure 26. Schematic Representation of Figure 25


TLV6001, TLV6002, TLV6004
12 Device and Documentation Support
12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:

• EMI Rejection Ratio of Operational Amplifiers (SBOA128)
• Circuit Board Layout Techniques (SLOA089)
12.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
TLV6001 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

TLV6001, TLV6002, TLV6004
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLV6001IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 14W2
TLV6001IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 14W2
TLV6001IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 13X
TLV6001IDCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 13X
TLV6001RIDBVR NRND SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 16O2
TLV6001RIDBVT NRND SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 16O2
TLV6001UIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 16P2
TLV6001UIDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 16P2
TLV6002IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 14TV
TLV6002IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 14TV
TLV6002IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 (TL6002, V6002)
TLV6004IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TLV6004
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2021
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV6001, TLV6002 :
• Automotive : TLV6001-Q1, TLV6002-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV6001IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV6001IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV6001IDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV6001IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV6001IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV6001IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV6001IDCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV6001IDCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV6001RIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV6001RIDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV6001UIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV6001UIDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV6002IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV6002IDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV6002IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV6002IDR SOIC D 8 2500 330.0 15.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV6004IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV6004IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2021
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV6001IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV6001IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV6001IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
TLV6001IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV6001IDCKR SC70 DCK 5 3000 180.0 180.0 18.0
TLV6001IDCKR SC70 DCK 5 3000 190.0 190.0 30.0
TLV6001IDCKT SC70 DCK 5 250 180.0 180.0 18.0
TLV6001IDCKT SC70 DCK 5 250 190.0 190.0 30.0
TLV6001RIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV6001RIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV6001UIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV6001UIDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
TLV6002IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
TLV6002IDGKT VSSOP DGK 8 250 366.0 364.0 50.0
TLV6002IDR SOIC D 8 2500 340.5 336.1 25.0
TLV6002IDR SOIC D 8 2500 336.6 336.6 41.3
TLV6004IPWR TSSOP PW 14 2000 366.0 364.0 50.0
TLV6004IPWR TSSOP PW 14 2000 853.0 449.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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80 SOIC (8) 4.90 mm × 3.91 mm

Changes from Revision B (October 2016) to Revision C Page

Changes from Revision A (July 2016) to Revision B Page

Changes from Original (June 2016) to Revision A Page

• Changed Product Status from Product Preview to Production Data ..................................................................................... 1

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5 Device Comparison Table

6 Pin Configuration and Functions

TLV6001: DCK Package TLV6001: DBV Package

Not to scale Not to scale

Pin Functions: TLV6001

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TLV6001R: DBV Package

Pin Functions: TLV6001R

TLV6001U: DBV Package

Pin Functions: TLV6001U

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TLV6002: D, DGK Packages

Pin Functions: TLV6002

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Pin Functions: TLV6004

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7.2 ESD Ratings

7.3 Recommended Operating Conditions

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7.4 Thermal Information: TLV6001

7.5 Thermal Information: TLV6002

7.6 Thermal Information: TLV6004

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7.7 Electrical Characteristics: VS= 1.8 V to 5 V (±0.9 V to ±2.75 V) (1)

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7.8 Typical Characteristics: Table of Graphs

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7.9 Typical Characteristics

Quiescent Current (µA/ch)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

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Typical Characteristics (continued)

VS = 1.8 V 150 IBN

Input Bias Current (pA)

VS = 1.8 V Output Voltage (V) 4

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Typical Characteristics (continued)

G = +1 V/V CL = 100 pF G = +1 V/V

Voltage (25 mV/div)

Voltage (250 mV/div)

Time (2.5 µs/div) Time (2.5 µs/div)

EMIRR IN+ (dB)

Figure 17. No Phase Reversal Figure 18. EMIRR IN+ vs Frequency