D−8 DDA−8 DGN−8

THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

HIGH-VOLTAGE, HIGH SLEW RATE, WIDEBAND

FET-INPUT OPERATIONAL AMPLIFIER
Check for Samples: THS4631

1FEATURES DESCRIPTION
2• High Bandwidth: The THS4631 is a high-speed, FET-input operational
amplifier designed for applications requiring wideband
– 325 MHz in Unity Gain operation, high-input impedance, and high-power
– 210 MHz Gain Bandwidth Product supply voltages. By providing a 210-MHz gain
• High Slew Rate: bandwidth product, ±15-V supply operation, and
100-pA input bias current, the THS4631 is capable of
– 900 V/µs (G = 2)
simultaneous wideband transimpedance gain and
– 1000 V/µs (G = 5) large output signal swing. The fast 1000 V/µs slew
• Low Distortion of –76 dB, SFDR at 5 MHz rate allows for fast settling times and good harmonic
• Maximum Input Bias Current: 100 pA distortion at high frequencies. Low current and
voltage noise allow amplification of extremely
• Input Voltage Noise: 7 nV/√Hz low-level input signals while still maintaining a large
• Maximum Input Offset Voltage: 500 µV at 25°C signal-to-noise ratio.
• Low Offset Drift: 2.5 µV/°C The characteristics of the THS4631 make it ideally
• Input Impedance: 109 || 3.9 pF suited for use as a wideband photodiode amplifier.
• Wide Supply Range: ± 5 V to ± 15 V Photodiode output current is a prime candidate for
transimpedance amplification as shown below. Other
• High Output Current: 95 mA potential applications include test and measurement
systems requiring high-input impedance, ADC and
APPLICATIONS DAC buffering, high-speed integration, and active
• Wideband Photodiode Amplifier filtering.
• High-Speed Transimpedance Gain Stage The THS4631 is offered in an 8-pin SOIC (D), and
the 8-pin SOIC (DDA) and MSOP (DGN) with
• Test and Measurement Systems
PowerPAD™ package.
• Current-DAC Output Buffer
• Active Filtering Related FET Input Amplifier Products
• High-Speed Signal Integrator SLEW VOLTAGE
VS GBWP MINIMUM
DEVICE RATE NOISE
(V) (MHz) GAIN
• High-Impedance Buffer (V/µS) (nV/√Hz)
OPA656 ±5 230 290 7 1
OPA657 ±5 1600 700 4.8 7
Photodiode Circuit OPA627 ±15 16 55 4.5 1
CF THS4601 ±15 180 100 5.4 1

RF

λ _

+ RL

−V(Bias)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
UNITS
VS Supply voltage, VS– to VS+ 33 V
VI Input voltage ±VS
(2)
IO Output current 150 mA
Continuous power dissipation See Dissipation Rating Table
TJ Maximum junction temperature (2) 150°C
(2)
TA Operating free-air temperature, continues operation, long-term reliability 125°C
Tstg Storage temperature range –65°C to 150°C
HBM 1000 V
ESD ratings: CDM 1500 V
MM 100 V

(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.

PACKAGE DISSIPATION RATINGS

POWER RATING (1) (TJ =125°C)
PACKAGE θJC (°C/W) θJA (°C/W)
TA ≤ 25°C TA = 85°C
(2)
D (8) 38.3 95 1.1 W 0.47 W
DDA (8) 9.2 45.8 2.3 W 0.98 W
DGN (8) 4.7 58.4 2.14 W 1.11 W

(1) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance.
(2) This data was taken using the JEDEC standard High-K test PCB.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNITS
Dual Supply ±5 ±15
VS Supply Voltage V
Single Supply 10 30
TA Operating free-air temperature -40 85 °C

2 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

PACKAGE / ORDERING INFORMATION

PACKAGE DEVICES (1) PACKAGE TYPE SOIC – 8 TRANSPORT MEDIA, QUANTITY
THS4631D Rails, 75
SOIC – 8
THS4631DR Tape and Reel, 2500
THS4631DDA Rails, 75
SOIC-PP – 8 (2)
THS4631DDAR Tape and Reel, 2500
THS4631DGN Rails, 100
MSOP-PP – 8 (2)
THS4631DGNR Tape and Reel, 2500

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) PowerPad™ is electrically isolated from all other pins. Connection of the PowerPAD to the PCB ground plane is recommended because
the ground plane is typically the largest copper area on a PCB. However, connection of the PowerPAD to VS- up to VS+ is allowed if
desired.

PIN ASSIGNMENTS
THS4631
TOP VIEW D, DDA, AND DGN

NC 1 8 NC
VIN− 2 7 VS+
VIN+ 3 6 VOUT −
VS− 4 5 NC

NC = No Internal Connection

Copyright © 2004–2011, Texas Instruments Incorporated 3

THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 499 Ω, RL = 1 kΩ, and G = 2 (unless otherwise noted)
TYP OVER TEMPERATURE
PARAMETER TEST CONDITIONS 0°C to –40°C to MIN/
25°C 25°C UNITS
70°C 85°C MAX
AC PERFORMANCE
G = 1, RF = 0 Ω, VO = 200 mVPP 325
G = 2, RF = 499 Ω, VO = 200 mVPP 105
Small signal bandwidth, -3 dB MHz
G = 5, RF = 499 Ω, VO = 200 mVPP 55
G = 10, RF = 499 Ω, VO = 200 mVPP 25
Gain bandwidth product G > 20 210 MHz
0.1 dB bandwidth flatness G = 2, RF = 499 Ω, CF = 8.2 pF 38 MHz
Large-signal bandwidth G = 2, RF = 499 Ω, VO = 2 VPP 105 MHz
G = 2, RF = 499 Ω, VO = 2-V step 550
Slew rate G = 2, RF = 499 Ω, VO = 10-V step 900 V/µs
G = 5, RF = 499 Ω, VO = 10-V step 1000
Rise and fall time 2-V step 5 ns
0.1%, G = -1, VO = 2-V step, CF = 4.7 pF 40
Settling time ns
0.01%, G = -1, VO = 2-V step, CF = 4.7 pF 190
HARMONIC DISTORTION
RL = 100 Ω -65
Second harmonic distortion dBc
G = 2, RL = 1 k Ω -76
VO = 2 VPP,
f = 5 MHz RL = 100 Ω -62
Third harmonic distortion dBc
RL = 1 kΩ -94
Input voltage noise f > 10 kHz 7 nV/√Hz
Input current noise f > 10 kHz 20 fA/√Hz
DC PERFORMANCE
Open-loop gain RL = 1 kΩ 80 70 65 65 dB Min
Input offset voltage (1) 260 500 1600 2000 µV Max
VCM = 0 V
Average offset voltage drift (1) 25°C to 85°C ±2.5 ±10 ±12 ±12 µV/°C Max
Input bias current 50 100 1500 2000 pA Max
VCM = 0 V
Input offset current 25 100 700 1000 pA Max
INPUT CHARACTERISTICS
-12.5 to
Common-mode input range -13 to 12 -12 to 11 -9 to 11 V Min
11.5
Common-mode rejection ratio VCM = 10 V 95 86 80 80 dB Min
Differential input resistance 109 || 3.9 Ω || pF
Common-mode input resistance 109 || 3.9 Ω || pF
OUTPUT CHARACTERISTICS
RL = 100 Ω ±11 ±10 ±9.5 ±9.5
Output voltage swing V Min
RL = 1 kΩ ±13.5 ±13 ±12.8 ±12.8
Static output current (sourcing) RL = 20 Ω 98 90 85 80 mA Min
Static output current (sinking) RL = 20 Ω 95 85 80 80 mA Min
Closed loop output impedance G = 1, f = 1 MHz 0.1 Ω
POWER SUPPLY
±15 ±16.5 ±16.5 ±16.5 V Max
Specified operating voltage
±5 ±4 ±4 ±4 V Min
Maximum quiescent current 11.5 13 14 14 mA Max
Minimum quiescent current 11.5 10 9 9 mA Min
Power supply rejection (PSRR +) VS+ = 15.5 V to 14.5 V, VS– = 15 V 95 85 80 80 dB Min
Power supply rejection (PSRR –) VS+ = 15 V, VS– = -15.5 V to -14..5 V 95 85 80 80 dB Min

(1) Input offset voltage is 100% tested at 25°C. It is specified by characterization and simulation over the listed temperature range.

4 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

TYPICAL CHARACTERISTICS (±15 V GRAPHS)

TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.

+15 V Test Data

Mesurement Point
50 Ω Source
+ 953 Ω 50 Ω Test
49.9 Ω THS4631 Equipment
_
49.9 Ω

−15 V
RG RF

499 Ω 499 Ω

CF
SMALL SIGNAL FREQUENCY SMALL SIGNAL FREQUENCY
RESPONSE RESPONSE 0.1-dB FLATNESS
50 10 6.3
VO = 200 mVPP VO = 200 mVPP CF = 0 pF
9
G = 100, RF = 11.3 kΩ, RG = 115 Ω 6.2
40 CF = 5.6 pF
8
6.1

Signal Gain − dB
7
Signal Gain − dB
Signal Gain − dB

30
CF = 8.2 pF
G = 10, RF = 499 Ω, 6
RG = 54.9 Ω 6
20 5
G = 5, RF = 499 Ω, CF = 8.2 pF 105 MHz
RG = 124 Ω 5.9
4
105 MHz
10 G = 2, RF = 499 Ω,
RG = 499 Ω 3 38 MHz
5.8
G = 1, RF = 0 Ω 2
0 G = 2, RF = 499 Ω,
RG = 499 Ω 5.7
1
−10 0 5.6
100 k 1M 10 M 100 M 1G 100 k 1M 10 M 100 M 1G 100 k 1M 10 M 100 M
f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz

Figure 1. Figure 2. Figure 3.

FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY LARGE SIGNAL FREQUENCY vs
RESPONSE RESPONSE CAPACiTIVE LOAD
5 8 4
VO = 200 mVPP VO = 5 VPP G = 1, RISO = 50 Ω,
4 RF = 0 Ω, CL = 10 pF
CF = 0 pF 7 2 RL = 1 kΩ
3
CF = 2.2 pF 6
0
Signal Gain − dB
Signal Gain − dB

Signal Gain − dB

2 VO = 0.5 VPP
RISO = 30 Ω,
5 CL = 56 pF
1 −2
0 4
105 MHz RISO = 20 Ω,
102 MHz VO = 2 VPP CL = 100 pF
−4
−1
CF = 5.2 pF 3 50 Ω +15 V
Source
−2 −6 RISO
2 THS4631
−3 G = −1, RF = 499 Ω, RL
RG = 499 Ω 1 −8 −15 V CL
−4 0Ω

−5 0 −10
100 k 1M 10 M 100 M 1G 100 k 1M 10 M 100 M 1G 100 k 1M 10 M 100 M 1G
f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz

Figure 4. Figure 5. Figure 6.

Copyright © 2004–2011, Texas Instruments Incorporated 5

THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)

TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
SECOND ORDER THIRD ORDER
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
−30 -30 -50
G = 2,
2nd Order Harmonic Distortion − dB

Gain = 2 Gain = 2 -55 HD2, RL = 100 W

RF = 499 Ω, RF = 499 W,

3rd Order Harmonic Distortion - dB

-40 RF = 499 W CF = 8.2 pF,
−40 CF = 8.2 pF CF = 8.2 pF -60 f = 4 MHz
VO = 2 VPP VO = 2 V PP HD3, RL = 100 W
-50

Harmonic Distortion - dB
-65
−50
-60 RL = 100 W
-70

−60 RL = 100 Ω -70 -75

HD2, RL = 1 kW
-80
-80
−70
-85
-90 RL = 1 kW HD3, RL = 1 kW
RL = 1 kΩ -90
−80
-100 -95

−90 -1 10 -100
1M 10 M 100 M 1M 10 M 100 M 0 0.5 1 1.5 2 2.5 3 3.5 4
f − Frequency − Hz f - Frequency - Hz VO - Output Voltage Swing - VPP

Figure 7. Figure 8. Figure 9.

SLEW RATE OPEN-LOOP GAIN OPEN-LOOP GAIN AND PHASE

vs vs vs
OUTPUT VOLTAGE TEMPERATURE FREQUENCY
1200 82 90 50
G = 5,
RF = 499 Ω, 81 80 25
1000 RG = 124 Ω
80 70 0

Open−Loop Gain − dB
SR − Slew Rate − V/ µs

Open-Loop Gain − dB

79 60 −25
800
78 50 −50

Phase − 5
600 40 −75
77
30 −100
76
400 20 −125
75
10 −150
74
200 −175
0
73
−10 −200
0 72 1k 10 k 100 k 1M 10 M 100 M 1G
0 2 4 6 8 10 12 −40 −30−20 −10 0 10 20 30 40 50 60 70 80 90
f − Frequency − Hz
VO − Output Voltage − VPP TC − Case Temperature − °C

Figure 10. Figure 11. Figure 12.

INPUT VOLTAGE QUIESCENT CURRENT INPUT BIAS CURRENT

vs vs vs
FREQUENCY SUPPLY VOLTAGE TEMPERATURE
100 12 800

TA = 85°C 700
11.5
I IB − Input Bias Current − pA
I Q − Quiescent Current − mA
Hz

600
Input Voltage Noise − nV/

11
500
TA = 25°C

10 10.5 400
TA = −40°C
300
10
200
9.5
100

1 9 0
10 100 1k 10 k 100 k 0 2 4 6 8 10 12 14 16 −40 −30 −20−10 0 10 20 30 40 50 60 70 80 90
f − Frequency − Hz VS − Supply Voltage − +V TA − Free-Air Temperature − °C

Figure 13. Figure 14. Figure 15.

6 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)

TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
INPUT OFFSET CURRENT INPUT OFFSET VOLTAGE OUTPUT VOLTAGE
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
250 300 13.55
Referred to 25°C
225
VO+
I IO − Input Offset Current − pA

200 13.5
200 DDA Package

VO − Output Voltage − |V|

Input Offset Voltage − m V
175 13.45
100
150 D Package
13.4
125 0
13.35
100
−100
75 13.3 VO−
50
−200
13.25
25 DGN Package
0 −300 13.2
−40−30−20−10 0 10 20 30 40 50 60 70 80 90 25 35 45 55 65 75 85 −40−30−20−10 0 10 20 30 40 50 60 70 80 90
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C TC − Case Temperature − °C

Figure 16. Figure 17. Figure 18.

STATIC OUTPUT DRIVE CURRENT

vs SMALL SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT
TEMPERATURE RESPONSE RESPONSE
100 125 1.2
Source 1
100
I O − Output Drive Current − |mA|

98
0.8
V O − Output Voltage − mV

75

V O − Output Voltage − V
96 0.6
50
0.4
94 Sink 25 0.2
92 0 0
−25 −0.2
90
Gain = 2, −0.4
−50 Gain = 2,
CF = 8.2 pF,
88 VI = 100 mVPP, −0.6 CF = 8.2 pF,
−75 VI = 1 VPP,
RL = 1 kΩ −0.8
86 RL = 1 kΩ
−100 −1
84 −125 −1.2
−40−30−20−10 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
TC − Case Temperature − °C t − Time− ns t − Time − ns

Figure 19. Figure 20. Figure 21.

LARGE SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT

RESPONSE RESPONSE RESPONSE
2.5 7 12
10 VPP 20 VPP
2 10
5
8
V O − Output Voltage − V

1.5
V O - Output Voltage - V

V O - Output Voltage - V

6
1 3
4
0.5 1 2
0 0
-1 -2
−0.5
Gain = 5, -4
−1 -3
Gain =
Gain = 2,
2, RF = 499 W, -6 Gain = 5,
CF =
C = 8.2 pF,
pF, RF = 499 W,
−1.5 V F= 28.2V R L = 1 kW
VII = 2 VPP,
PP, -8 RL = 1 kW
R L = 1 kΩ -5
−2 RL = 1 kΩ -10
−2.5 -7 -12
0 25 50 75 100 125 150 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
t − Time− ns t - Time - ns t - Time - ns

Figure 22. Figure 23. Figure 24.

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THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)

TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
SETTLING TIME SETTLING TIME OVERDRIVE RECOVERY
1.5 3 20 4
Input Gain = 5,
1.25 Rising 2.5 Rising
15 RF = 499 Ω, 3
1 2 RG = 124 Ω

V O − Output Voltage − V
V O− Output Voltage − V
1.5
V O− Output Voltage − V

0.75 10 2

V I − Input Voltage − V
0.5 1
5 1
0.25 G = −1, 0.5 G = −1,
CF = 4.7 pF CF = 4.7 pF 0
0 0 0
−0.25 −0.5
−5 −1
−0.5 −1 Output
−0.75 −1.5 −10 −2
Falling Falling
−1 −2
−15 −3
−1.25 −2.5
−1.5 −3 −20 −4
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

t − Time − ns t − Time − ns t − Time − ms

Figure 25. Figure 26. Figure 27.

COMMON-MODE REJECTION RATIO REJECTION RATIO

vs vs
OVERDRIVE RECOVERY INPUT COMMON-MODE RANGE FREQUENCY
20 4 100 100
CMRR − Common-Mode Rejection Ratio − dB

Input
90 90
15 3
80 80
V O − Output Voltage − V

Output CMRR
V I − Input Voltage − V

Rejection Ratio − dB
10 2
70 70
5 1 60 60

0 50 50 PSRR+
0
40 40
−5 −1
PSRR−
30 30
−10 Gain = 5, −2
20 20
RF = 499 Ω,
−15 RG = 124 Ω −3
10 10
−20 −4 0
−0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0
−15 −10 −5 0 5 10 15 10 k 100 k 1M 10 M 100 M
t − Time − ms VICR − Input Common-Mode Range − V f − Frequency − Hz

Figure 28. Figure 29. Figure 30.

OUTPUT IMPEDANCE
vs
FREQUENCY
100
Z o − Output Impedance − Ω

10

0.1

0.01
100 k 1M 10 M 100 M 1G
f − Frequency − Hz
Figure 31.

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 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

APPLICATION INFORMATION

The large gain-bandwidth product of the THS4631

INTRODUCTION provides the capability for simultaneously achieving
The THS4631 is a high-speed, FET-input operational both high-transimpedance gain, wide bandwidth, high
amplifier. The combination of: high gain bandwidth slw rate, and low noise. In addition, the high-power
product of 210 MHz, high slew rate of 1000 V/µs, and supply rails provide the potential for a very wide
trimmed dc precision makes the device an excellent dynamic range at the output, allowing for the use of
design option for a wide variety of applications, input sources which possess wide dynamic range.
including test and measurement, optical monitoring, The combination of these characteristics makes the
transimpedance gain circuits, and high-impedance THS4631 a design option for systems that require
buffers. The applications section of the data sheet transimpedance amplification of wideband, low-level
discusses these particular applications in addition to input signals. A standard transimpedance circuit is
general information about the device and its features shown in Figure 32.
Photodiode Circuit
TRANSIMPEDANCE FUNDAMENTALS
CF
FET-input amplifiers are often used in
transimpedance applications because of their
extremely high input impedance. A transimpedance RF
block accepts a current as an input and converts this
λ _
current to a voltage at the output. The high-input
impedance associated with FET-input amplifiers
minimizes errors in this process caused by the input + RL
bias currents, IIB, of the amplifier.
−V(Bias)
DESIGNING THE TRANSIMPEDANCE
CIRCUIT Figure 32. Wideband Photodiode
Transimpedance Amplifier
Typically, design of a transimpedance circuit is driven
by the characteristics of the current source that
As indicated, the current source typically sets the
provides the input to the gain block. A photodiode is
requirements for gain, speed, and dynamic range of
the most common example of a capacitive current
the amplifier. For a given amplifier and source
source that interfaces with a transimpedance gain
combination, achievable performance is dictated by
block. Continuing with the photodiode example, the
the following parameters: the amplifier
system designer traditionally chooses a photodiode
gain-bandwidth product, the amplifier input
based on two opposing criteria: speed and sensitivity.
capacitance, the source capacitance, the
Faster photodiodes cause a need for faster gain
transimpedance gain, the amplifier slew rate, and the
stages, and more sensitive photodiodes require
amplifier output swing. From this information, the
higher gains in order to develop appreciable signal
optimal performance of a transimpedance circuit
levels at the output of the gain stage.
using a given amplifier is determined. Optimal is
These parameters affect the design of the defined here as providing the required
transimpedance circuit in a few ways. First, the speed transimpedance gain with a maximized flat frequency
of the photodiode signal determines the required response.
bandwidth of the gain circuit. Second, the required
For the circuit shown in Figure 32, all but one of the
gain, based on the sensitivity of the photodiode, limits
design parameters is known; the feedback capacitor
the bandwidth of the circuit. Third, the larger
(CF) must be determined. Proper selection of the
capacitance associated with a more sensitive signal
feedback capacitor prevents an unstable design,
source also detracts from the achievable speed of the
controls pulse response characteristics, provides
gain block. The dynamic range of the input signal
maximized flat transimpedance bandwidth, and limits
also places requirements on the amplifier dynamic
broadband integrated noise. The maximized flat
range. Knowledge of the source output current levels,
frequency response results with CF calculated as
coupled with a desired voltage swing on the output,
shown in Equation 1, where CF is the feedback
dictates the value of the feedback resistor, RF. The
capacitor, RF is the feedback resistor, CS is the total
transfer function from input to output is VOUT = IINRF.
source capacitance (including amplifier input
capacitance and parasitic capacitance at the inverting
node), and GBP is the gain-bandwidth product of the
amplifier in hertz.

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THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

1
p RF G B P
) Ǹǒ 1
p RF G B P
Ǔ
2
)
4C S
p RF G B P
Gain AOL

−20 dB/
C + 20 dB/Decade
F 2 (1) Decade
Rate-of-Closure

Once the optimal feedback capacitor has been

selected, the transimpedance bandwidth can be
Noise Gain
calculated with Equation 2.

F
*3dB
+ Ǹ GBP
2 p RF ǒC S ) CFǓ
20 dB/
Decade
GBP

(2)
0
f
CI(CM) +
CI(DIFF) Zero Pole
_

RF Figure 34. Transimpedance Circuit Bode Plot

CP
The performance of the THS4631 has been
measured for a variety of transimpedance gains with
I(DIODE) CD a variety of source capacitances. The achievable
CF
bandwidths of the various circuit configurations are
summarized numerically in Table 1. The frequency
responses are presented in Figure 35, Figure 36, and
CS = CI(CM) + CI(DIFF) + CP + CD
Figure 37.
A. The total source capacitance is the sum of
Note that the feedback capacitances do not
several distinct capacitances.
correspond exactly with the values predicted by the
Figure 33. Transimpedance Analysis Circuit equation. They have been tuned to account for the
parasitic capacitance of the feedback resistor
Where: (typically 0.2 pF for 0805 surface mount devices) as
well as the additional capacitance associated with the
CI(CM) is the common-mode input capacitance. PC board. The equation should be used as a starting
CI(DIFF) is the differential input capacitance. point for the design, with final values for CF optimized
CD is the diode capacitance. in the laboratory.
CP is the parasitic capacitance at the inverting
node.
The feedback capacitor provides a pole in the noise Table 1. Transimpedance Performance Summary
gain of the circuit, counteracting the zero in the noise for Various Configurations
gain caused by the source capacitance. The pole is SOURCE TRANS- FEEDBACK -3 dB
set such that the noise gain achieves a 20-dB per CAPACITANCE IMPEDANCE CAPACITANCE FREQUENCY
(PF) GAIN (Ω) (PF) (MHZ)
decade rate-of-closure with the open-loop gain
18 10 k 2 15.8
response of the amplifier, resulting in a stable circuit.
As indicated, the formula given provides the feedback 18 100 k 0.5 3
capacitance for maximized flat bandwidth. Reduction 18 1M 0 1.2
in the value of the feedback capacitor can increase 47 10 k 2.2 8.4
the signal bandwidth, but this occurs at the expense 47 100 k 0.7 2.1
of peaking in the ac response. 47 1M 0.2 0.52
100 10 k 3 5.5
100 100 k 1 1.4
100 1M 0.2 0.37

10 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

Table 1. Transimpedance Performance Summary is difficult to measure the frequency response with
for Various Configurations (continued) traditional laboratory equipment because the circuit
10-kΩ TRANSIMPEDANCE RESPONSES
requires a current as an input rather than a voltage.
85
Also, the capacitance of the current source has a
CS = 18 PF direct effect on the frequency response. A simple
CF = 2 PF interface circuit can be used to emulate a capacitive
Transimpedance Gain − dB

80 current source with a network analyzer. With this

circuit, trans- impedance bandwidth measurements
CS = 47 PF
CF = 2.2 PF are simplified, making amplifier evaluation easier and
75 faster.
CS = 100 PF
Network Analizer IO
CF = 3 PF
70
VS = ±15 V 50 W 50 W C2 IO 1
RL = 1 k (s) +
65
RF = 10 k RS
C1
VS 2R S
ǒ1 ) C1
C2
Ǔ
10 k 100 k 1M 10 M 1G VS
(Above the Pole Frequency)
f − Frequency − Hz

Figure 35.
A. The interface network creates a capacitive,
100-kΩ TRANSIMPEDANCE RESPONSES
constant current source from a network
105
analyzer and properly terminates the
CS = 18 PF
network analyzer at high frequencies.
Transimpedance Gain − dB

CF = 0.5 PF
100 Figure 38. Emulating a Capacitive Current Source
With a Network Analyzer
CS = 47 PF
CF = 0.7 PF
95
The transconductance transfer function of the
CS = 100 PF interface circuit is:
CF = 1 PF
90 s
VS = ±15 V
RL = 1 k IO 2 RS ǒ1)C1
C2
Ǔ
RF = 100 k
(s) + 1
85
10 k 100 k 1M 10 M 1G
VS s) 2 R S ǒC1)C2Ǔ
f − Frequency − Hz
(3)

Figure 36. The transfer function contains a zero at dc and a pole

1
1-MΩ TRANSIMPEDANCE RESPONSES
at: 2 R S
( C1 ) C2) . The transconductance is constant
125 1
CS = 18 PF

120
CF = 0 PF
ǒ
2 RS 1 )
C1 Ǔ
Transimpedance Gain − dB

at: C2 , above the pole frequency,

115
providing a controllable ac-current source. This circuit
CS = 47 PF also properly terminates the network analyzer with 50
CF = 0.2 PF
110 Ω at high frequencies. The second requirement for
CS = 100 PF this current source is to provide the desired output
CF = 0.2 PF
105 impedance, emulating the output impedance of a
VS = ±15 V
photodiode or other current source. The output
100 RL = 1 k impedance of this circuit is given by:
RF = 1 M
95
10 k 100 k 1M 10 M ȱs ) 2 R ǒC1)C2
1
Ǔ
ȳ
f − Frequency − Hz Z O(s) + C1 ) C2 ȧ S
ȧ
sǒs ) Ǔ
C1 C2 1
Figure 37. Ȳ ȴ
2 R S C1
(4)
MEASURING TRANSIMPEDANCE Assuming C1 >> C2, the equation reduces to:
BANDWIDTH ZO [ 1
sC2 , giving the appearance of a capacitive
While there is no substitute for measuring the
source at a higher frequency.
performance of a particular circuit under the exact
conditions that are used in the application, the Capacitor values should be chosen to satisfy two
complete system environment often makes requirements. First, C2 represents the anticipated
measurements harder. For transimpedance circuits, it capacitance of the true source. Second C1 is chosen
Copyright © 2004–2011, Texas Instruments Incorporated 11
THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

such that the corner frequency

transconductance network is much less than the
of

transimpedance bandwidth of the circuit. Choosing

the
R E Q + RF 1 ǒ 1)
RF 2
RF 3
Ǔ
(5)
this corner frequency properly leads to more accurate
measurements of the transimpedance bandwidth. If CF
RF3
the interface circuit corner frequency is too close to
the bandwidth of the circuit, determining the power
RF1 RF2
level in the flatband is difficult. A decade or more of
flat bandwidth provides a good basis for determining
λ _
the proper transimpedance bandwidth.

ALTERNATIVE TRANSIMPEDANCE + RL
CONFIGURATIONS
Other transimpedance configurations are possible. −V(Bias)
Three possibilities are shown below.
A. A resistive T-network enables high
The first configuration is a slight modification of the transimpedance gain with reasonable
basic transimpedance circuit. By splitting the resistor values.
feedback resistor, the feedback capacitor value
Figure 40. Alternative Transimpedance
becomes more manageable and easier to control. Configuration 2
This type of compensation scheme is useful when the
feedback capacitor required in the basic configuration
becomes so small that the parasitic effects of the The third configuration uses a capacitive T-network to
board and components begin to dominate the total achieve fine control of the compensation capacitance.
feedback capacitance. By reducing the resistance The capacitor CF3 can be used to tune the total
across the capacitor, the capacitor value can be effective feedback capacitance to a fine degree. This
increased. This mitigates the dominance of the circuit behaves the same as the basic
parasitic effects. transimpedance configuration, with the effective CF
given by Equation 6.
CF

RF1 RF2
1
CF E Q
+ 1
CF 1
ǒ1)
CF 3
CF 2
Ǔ
(6)

λ _ CF3

+ RL CF1 CF2

−V(Bias) RF
A. Splitting the feedback resistor enables use
λ _
of a larger, more manageable feedback
capacitor.
+ RL
Figure 39. Alternative Transimpedance
Configuration 1
−V(Bias)
The second configuration uses a resistive T-network
A. A capacitive T-network enables fine control
to achieve high transimpedance gains using relatively
of the effective feedback capacitance using
small resistor values. This topology can be useful relatively large capacitor values.
when the desired transimpedance gain exceeds the
value of available resistors. The transimpedance gain Figure 41. Alternative Transimpedance
is given by Equation 5. Configuration 3

12 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

SUMMARY OF KEY DECISIONS IN feedback resistors this large or anticipate using an

TRANSIMPEDANCE DESIGN external compensation scheme to stabilize the circuit.
Using a simple capacitor in parallel with the feedback
The following is a simplified process for basic resistor makes the amplifier more stable as shown in
transimpedance circuit design. This process gives a the Typical Characteristics graphs.
start to the design process, though it does ignore
some aspects that may be critical to the circuit.
NOISE ANALYSIS
STEP 1: Determine the capacitance of the source.
High slew rate, unity gain stable, voltage-feedback
STEP 2: Calculate the total source capacitance, operational amplifiers usually achieve their slew rate
including the amplifier input capacitance, CI(CM) at the expense of a higher input noise voltage. The
and CI(DIFF). 7 nV/√Hz input voltage noise for the THS4631 is,
however, much lower than comparable amplifiers
STEP 3: Determine the magnitude of the possible while achieving high slew rates. The input-referred
current output from the source, including the voltage noise, and the input-referred current noise
minimum signal current anticipated and term, combine to give low output noise under a wide
maximum signal current anticipated. variety of operating conditions. Figure 42 shows the
STEP 4: Choose a feedback resistor value such that amplifier noise analysis model with all the noise terms
the input current levels create the desired included. In this model, all noise terms are taken to
output signal voltages, and be noise voltage or current density terms in either
ensure that the output voltages can nV/√Hz or fA/√Hz.
accommodate the dynamic range of the input
ENI
signal.
+
STEP 5: Calculate the optimum feedback EO
capacitance using Equation 1. RS IBN _

STEP 6: Calculate the bandwidth given the ERF

ERS 4kTRS Rf
resulting component values.
STEP 7: Evaluate the circuit to determine if all design Rg
4kT IBI 4kTRf
goals are satisfied. Rg

SELECTION OF FEEDBACK RESISTORS 4kT = 1.6E−20J

at 290K
Feedback resistor selection can have a significant
effect on the performance of the THS4631 in a given Figure 42. Noise Analysis Model
application, especially in configurations with low
closed-loop gain. If the amplifier is configured for The total output noise voltage can be computed as
unity gain, the output should be directly connected to the square root of all square output noise voltage
the inverting input. Any resistance between these two contributors. Equation 7 shows the general form for
points interacts with the input capacitance of the the output noise voltage using the terms shown in
amplifier and causes an additional pole in the Figure 42.
frequency response. For nonunity gain configurations,
low resistances are desirable for flat frequency
response. However, care must be taken not to load
EO + Ǹǒ 2
Ǔ 2
ENI 2 ) ǒIBNRSǓ ) 4kTR S NG 2 ) ǒIBIRfǓ ) 4kTRfNG

the amplifier too heavily with the feedback network if (7)

large output signals are expected. In most cases, a
trade off is made between the frequency response Dividing this expression by the noise gain [NG = (1+
characteristics and the loading of the amplifier. For a Rf/Rg)] gives the equivalent input-referred spot noise
gain of 2, a 499-Ωfeedback resistor is a suitable voltage at the noninverting input, as shown in
operating point from both perspectives. If resistor Equation 8:
values are chosen too large, the THS4631 is subject
to oscillation problems. For example, an inverting
amplifier configuration with a 5-kΩ gain resistor and a
EN + Ǹ E NI 2
2 I R
) ǒI BNRSǓ ) 4kTR S ) BI f
NG
ǒ Ǔ ) 4kTR
NG
2
f

5-kΩ feedback resistor develops an oscillation due to (8)

the interaction of the large resistors with the input
capacitance. In low gain configurations, avoid Using high resistor values can dominate the total
equivalent input-referred noise. Using a 3-kΩ
source-resistance (RS) value adds a voltage noise
term of approximately 7 nV/√Hz. This is equivalent to
the amplifier voltage noise term. Using higher resistor
Copyright © 2004–2011, Texas Instruments Incorporated 13
THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

values dominate the noise of the system. Although performance of the THS4631. Resistors should be
the THS4631 JFET input stage is ideal for a very low reactance type. Surface-mount
high-source impedance because of the low-bias resistors work best and allow a tighter overall
currents, the system noise and bandwidth is limited layout. Again, keep their leads and PC board
by a high-source (RS) impedance. trace length as short as possible. Never use
wirebound type resistors in a high frequency
SLEW RATE PERFORMANCE WITH VARYING application. Since the output pin and inverting
INPUT STEP AMPLITUDE AND RISE/FALL input pins are the most sensitive to parasitic
TIME capacitance, always position the feedback and
series output resistors, if any, as close as possible
Some FET input amplifiers exhibit the peculiar to the inverting input pins and output pins. Other
behavior of having a larger slew rate when presented network components, such as input termination
with smaller input voltage steps and slower edge resistors, should be placed close to the
rates due to a change in bias conditions in the input gain-setting resistors. Even with a low parasitic
stage of the amplifier under these circumstances. capacitance shunting the external resistors,
This phenomena is most commonly seen when FET excessively high resistor values can create
input amplifiers are used as voltage followers. As this significant time constants that can degrade
behavior is typically undesirable, the THS4631 has performance. Good axial metal-film or
been designed to avoid these issues. Larger surface-mount resistors have approximately 0.2
amplitudes lead to higher slew rates, as would be pF in shunt with the resistor. For resistor values >
anticipated, and fast edges do not degrade the slew 2.0 kΩ, this parasitic capacitance can add a pole
rate of the device. The high slew rate of the THS4631 and/or a zero that can effect circuit operation.
allows improved SFDR and THD performance, Keep resistor values as low as possible,
especially noticeable above 5 MHz. consistent with load driving considerations.
• Connections to other wideband devices on the
PRINTED-CIRCUIT BOARD LAYOUT board may be made with short direct traces or
TECHNIQUES FOR OPTIMAL through onboard transmission lines. For short
PERFORMANCE connections, consider the trace and the input to
Achieving optimum performance with high frequency the next device as a lumped capacitive load.
amplifier-like devices in the THS4631 requires careful Relatively wide traces (50 mils to 100 mils) should
attention to board layout parasitic and external be used, preferably with ground and power planes
component types. opened up around them. Estimate the total
capacitive load and determine if isolation resistors
Recommendations that optimize performance include: on the outputs are necessary. Low parasitic
• Minimize parasitic capacitance to any ac ground capacitive loads (< 4 pF) may not need an RS
for all of the signal I/O pins. Parasitic capacitance since the THS4631 is nominally compensated to
on the output and input pins can cause instability. operate with a 2-pF parasitic load. Higher parasitic
To reduce unwanted capacitance, a window capacitive loads without an RS are allowed as the
around the signal I/O pins should be opened in all signal gain increases (increasing the unloaded
of the ground and power planes around those phase margin). If a long trace is required, and the
pins. Otherwise, ground and power planes should 6-dB signal loss intrinsic to a doubly-terminated
be unbroken elsewhere on the board. transmission line is acceptable, implement a
• Minimize the distance (< 0.25”) from the power matched impedance transmission line using
supply pins to high frequency 0.1-µF and 100-pF microstrip or stripline techniques (consult an ECL
de-coupling capacitors. At the device pins, the design handbook for microstrip and stripline layout
ground and power plane layout should not be in techniques). A
close proximity to the signal I/O pins. Avoid 50-Ω environment is not necessary onboard, and
narrow power and ground traces to minimize in fact, a higher impedance environment improves
inductance between the pins and the de-coupling distortion as shown in the distortion versus load
capacitors. The power supply connections should plots. With a characteristic board trace impedance
always be de-coupled with these capacitors. based on board material and trace dimensions, a
Larger (6.8 µF or more) tantalum de-coupling matching series resistor into the trace from the
capacitors, effective at lower frequency, should output of the THS4631 is used as well as a
also be used on the main supply pins. These may terminating shunt resistor at the input of the
be placed somewhat farther from the device and destination device. Remember also that the
may be shared among several devices in the terminating impedance is the parallel combination
same area of the PC board. of the shunt resistor and the input impedance of
• Careful selection and placement of external the destination device: this total effective
components preserve the high frequency impedance should be set to match the trace

14 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

impedance. If the 6-dB attenuation of a doubly

terminated transmission line is unacceptable, a 0.205
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in 0.060
0.017
this case. This does not preserve signal integrity
or a doubly-terminated line. If the input impedance Pin 1 0.013
of the destination device is low, there is some
signal attenuation due to the voltage divider
0.030
formed by the series output into the terminating 0.075 0.025 0.094
impedance.
• Socketing a high-speed part like the THS4631 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket 0.035 0.040
0.010
creates a troublesome parasitic network which
vias
makes it almost impossible to achieve a smooth,
stable frequency response. Best results are Top View
obtained by soldering the THS4631 part directly
onto the board. Figure 44. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD DESIGN CONSIDERATIONS
The THS4631 is available in a thermally-enhanced 0.300
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which 0.100 0.026
the die is mounted [see Figure 43 (a) and Figure 43 0.035 0.010
(b)]. This arrangement results in the lead frame being Pin 1
exposed as a thermal pad on the underside of the
package [see Figure 43 (c)]. Because this thermal 0.030
pad has direct thermal contact with the die, excellent 0.060
thermal performance can be achieved by providing a
0.140 0.050
good thermal path away from the thermal pad 0.176
0.060
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
0.035
(when the leads are being soldered), the thermal pad 0.010
0.080
can also be soldered to a copper area underneath the vias
package. Through the use of thermal paths within this All Units in Inches
copper area, heat can be conducted away from the Top View
package into either a ground plane or other heat
dissipating device. Figure 45. DDA PowerPAD PCB Etch and Via
Pattern
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the mechanical methods of PowerPAD PCB LAYOUT CONSIDERATIONS
heatsinking.
1. PCB with a top side etch pattern is shown in
Figure 44 and Figure 45. There should be etch
DIE
for the leads and for the thermal pad.
Side View (a) Thermal 2. Place the recommended number of holes in the
Pad area of the thermal pad. These holes should be
DIE 10 mils in diameter. Keep them small so that
End View (b)
solder wicking through the holes is not a problem
Bottom View (c) during reflow.
Figure 43. Views of Thermally Enhanced Package 3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
Although there are many ways to properly heatsink the THS4631 IC. These additional vias may be
the PowerPAD package, the following steps illustrate larger than the 10-mil diameter vias directly under
the recommended approach. the thermal pad. They can be larger because
they are not in the thermal pad area to be
Copyright © 2004–2011, Texas Instruments Incorporated 15
THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

soldered so that wicking is not a problem. T max * T A

P D max +
4. Connect all holes to the internal ground plane. qJ A (9)
Although the PowerPAD is electrically isolated
from all pins and the active circuitry, connection where:
to the ground plane is recommended. This is due PDmax is the maximum power dissipation in the
to the fact that ground planes on most PCBs are amplifier (W).
typically the targets copper area. Offering the Tmax is the absolute maximum junction
best thermal path heat to flow out of the device. temperature (°C).
5. When connecting these holes to the ground TA is the ambient temperature (°C).
plane, do not use the typical web or spoke via
θJA = θJC + θCA
connection methodology. Web connections have
a high thermal resistance connection that is θJC is the thermal coefficient from the silicon
useful for slowing the heat transfer during junctions to the case (°C/W).
soldering operations. This makes the soldering of θCA is the thermal coefficient from the case to
vias that have plane connections easier. In this ambient air (°C/W).
application, however, low thermal resistance is
NOTE:
desired for the most efficient heat transfer.
Therefore, the holes under the THS4631 For systems where heat dissipation is more
PowerPAD package should make their critical, the THS4631 is offered in an 8-pin MSOP
connection to the internal ground plane with a with PowerPAD package and an 8-pin SOIC with
complete connection around the entire PowerPAD package with better thermal
circumference of the plated-through hole. performance. The thermal coefficient for the
PowerPAD packages are substantially improved
6. The top-side solder mask should leave the over the traditional SOIC. Maximum power
terminals of the package and the thermal pad dissipation levels are depicted in Figure 46 for the
area with its via holes exposed. The bottom-side available packages. The data for the PowerPAD
solder mask should cover the via holes of the packages assume a board layout that follows the
thermal pad area. This prevents solder from PowerPAD layout guidelines referenced above
being pulled away from the thermal pad area and detailed in the PowerPAD application note
during the reflow process. number SLMA002. Figure 46 also illustrates the
7. Apply solder paste to the exposed thermal pad effect of not soldering the PowerPAD to a PCB.
area and all of the IC terminals. The thermal impedance increases substantially
8. With these preparatory steps in place, the IC is which may cause serious heat and performance
simply placed in position and run through the issues. Be sure to always solder the PowerPAD
solder reflow operation as any standard to the PCB for optimum performance.
surface-mount component. This results in a part 4
that is properly installed. TJ = 125°C
PD − Maximum Power Dissipation − W

3.5

POWER DISSIPATION AND THERMAL 3

θJA = 58.4°C/W
CONSIDERATIONS
2.5
To maintain maximum output capabilities, the θJA = 98°C/W
2
THS4631 does not incorporate automatic thermal
shutoff protection. The designer must take care to 1.5
ensure that the design does not violate the absolute
1
maximum junction temperature of the device. Failure
may result if the absolute maximum junction 0.5
temperature of 150°C is exceeded. For best θJA = 158°C/W
0
performance, design for a maximum junction −40 −20 0 20 40 60 80 100
temperature of 125°C. Between 125°C and 150°C, TA − Free-Air Temperature − °C
damage does not occur, but the performance of the
amplifier begins to degrade. The thermal Figure 46. Maximum Power Dissipation
characteristics of the device are dictated by the vs. Ambient Temperature
package and the PC board. Maximum power
dissipation for a given package can be calculated
using Equation 9.

16 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

Results are with no air flow and PCB size = 3" x 3 "
θJA = 58.4°C/W for the 8-pin MSOP with
PowerPAD (DGN).
θJA = 98°C/W for the 8-pin SOIC high-K test PCB
(D).
θJA = 158°C/W for the 8-pin MSOP with
PowerPAD, without solder.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem

DESIGN TOOLS EVALUATION FIXTURE,

SPICE MODELS, AND APPLICATIONS
SUPPORT
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal an evaluation board has
been developed for the THS4631 operational Figure 48. EVM Layers 2 and 3, Ground
amplifier. The board is easy to use, allowing for
straightforward evaluation of the device. The
evaluation board can be ordered through the Texas
Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. The
board layers are provided in Figure 47, Figure 48,
and Figure 49. The bill of materials for the evaluation
board is provided in Table 2.

Figure 49. EVM Bottom Layer

Figure 47. EVM Top Layer

Copyright © 2004–2011, Texas Instruments Incorporated 17

THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

BILL OF MATERIALS

Table 2. THS4631DDA EVM

SMD REFERENCE PCB MANUFACTURER'S
ITEM DESCRIPTION
SIZE DESIGNATOR QUANTITY PART NUMBER (1)
1 CAP, 2.2 µF, CERAMIC, X5R, 25 V 1206 C3, C6 2 (AVX) 12063D225KAT2A
4 CAP, 0.1µF, CERAMIC, X7R, 50 V 0805 C1, C2 2 (AVX) 08055C104KAT2A
OPEN 0805 R4, Z4, Z6 3
6 RESISTOR, 0 OHM, 1/8 W 0805 Z2 1 (KOA) RK73Z2ATTD
7 RESISTOR, 499 OHM, 1/8 W, 1% 0805 R3, Z5 2 (KOA) RK73H2ATTD4990F
8 OPEN 1206 R8, Z9 2
9 RESISTOR, 0 OHM, 1/4 W 1206 R1 1 (KOA) RK73Z2BLTD
10 RESISTOR, 49.9 OHM, 1/4 W, 1% 1206 R2 1 (KOA) RK73H2BLTD49R9F
11 RESISTOR, 953 OHM, 1/4 W, 1% 1206 Z3 1 (KOA) RK73H2BLTD9530F
13 CONNECTOR, SMA PCB JACK J1, J2, J3 3 (JOHNSON) 142-0701-801
JACK, BANANA RECEPTANCE, 0.25"
14 J4, J5, J6 3 (SPC) 813
DIA. HOLE
15 TEST POINT, BLACK TP1, TP2 2 (KEYSTONE) 5001
TEST POINT, RED TP3 1 (KEYSTONE) 5000
16 STANDOFF, 4-40 HEX, 0.625" LENGTH 4 (KEYSTONE) 1808
17 SCREW, PHILLIPS, 4-40, .250" 4 SHR-0440-016-SN
18 IC, THS4631 U1 1 (TI) THS4631DDA
19 BOARD, PRINTED CIRCUIT 1 (TI) EDGE # 6467873 Rev.A

(1) The manufacturer's part numbers are used for test purposes only.

EVM
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic
capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4631 is
available through either the Texas Instruments web site (www.ti.com). These models help in predicting
small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types
in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the
model file itself.

18 Copyright © 2004–2011, Texas Instruments Incorporated

 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

Figure 50. THS4631 EVM Schematic

Copyright © 2004–2011, Texas Instruments Incorporated 19

THS4631
SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011 www.ti.com

ADDITIONAL REFERENCE MATERIAL

• PowerPAD Made Easy, application brief (SLMA004)
• PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
• Noise Analysis of FET Transimpedance Amplifiers, application bulletin, Texas Instruments Literature Number
SBOA060.
• Tame Photodiodes With Op Amp Bootstrap, application bulletin, Texas Instruments Literature Number
SBBA002.
• Designing Photodiode Amplifier Circuits With OPA128, application bulletin, Texas Instruments Literature
Number SBOA061.
• Photodiode Monitoring With Op Amps, application bulletin, Texas Instruments Literature Number SBOA035.
• Comparison of Noise Performance Between a FET Transimpedance Amplifier and a Switched Integrator,
Application Bulletin, Texas Instruments Literature Number SBOA034.

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.

Input Range, VS+ to VS– 10 V to 30 V

Input Range, VI 10 V to 30 V NOT TO EXCEED VS+ or VS–
Output Range, VO 10 V to 30 V NOT TO EXCEED VS+ or VS–

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Consult the product data sheet or EVM user's guide (if user's guide is available)
prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact
a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265

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 THS4631
www.ti.com SLOS451B – DECEMBER 2004 – REVISED AUGUST 2011

REVISION HISTORY

Changes from Original (December 2004) to Revision A Page

• Changed the Related FET Input Amplifier Products table .................................................................................................... 1

• Changed the Differential input resistance value From: 109 || 6.5 To: 109 || 3.9 ................................................................... 4
• Changed the Common-mode input resistance value From: 109 || 6.5 To: 109 || 3.9 ............................................................ 4
• Changed Figure 8 - From: RL = 499Ω To RF = 499Ω ........................................................................................................... 6
• Changed Figure 9 - From: RL = 499Ω To RF = 499Ω ........................................................................................................... 6
• Added Figure 23 ................................................................................................................................................................... 7
• Added Figure 24 ................................................................................................................................................................... 7
• Added Figure 50 ................................................................................................................................................................. 19

Changes from Revision A (March 2005) to Revision B Page

• Changed the Tstg value in the Absolute Maximum Ratings table From: 65°C to 150°C To: –65°C to 150°C ...................... 2

Copyright © 2004–2011, Texas Instruments Incorporated 21

 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

THS4631D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4631

THS4631DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green SN Level-2-260C-1 YEAR -40 to 85 4631

THS4631DE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4631

THS4631DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADK

THS4631DGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADK

THS4631DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 ADK

THS4631DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ADK

THS4631DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 4631

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4631DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4631DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4631DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4631DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
THS4631DGNR HVSSOP DGN 8 2500 358.0 335.0 35.0
THS4631DR SOIC D 8 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
THS4631D D SOIC 8 75 505.46 6.76 3810 4
THS4631DDA DDA HSOIC 8 75 505.46 6.76 3810 4
THS4631DE4 D SOIC 8 75 505.46 6.76 3810 4
THS4631DGN DGN HVSSOP 8 80 330 6.55 500 2.88
THS4631DGNG4 DGN HVSSOP 8 80 330 6.55 500 2.88

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DGN 8 PowerPAD VSSOP - 1.1 mm max height
3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225482/A

www.ti.com
 PACKAGE OUTLINE
TM
DGN0008D SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
1.89
1.63 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.57
TYPICAL
1.28

4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008D PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.57)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(1.89)

6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225481/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGN0008D PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(1.89)
SYMM BASED ON
0.125 THICK
STENCIL
6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 1.76 X 2.11
0.125 1.57 X 1.89 (SHOWN)
0.15 1.43 X 1.73
0.175 1.33 X 1.60

4225481/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
TM
DGN0008G SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.15
1.95 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.846
TYPICAL
1.646

4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.846)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(2.15)
6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225480/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(2.15)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.06 X 2.40
0.125 1.846 X 2.15 (SHOWN)
0.15 1.69 X 1.96
0.175 1.56 X 1.82

4225480/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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