tps73633 Ep

TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
CAP-FREE NMOS 400 mA LOW-DROPOUT REGULATORS

WITH REVERSE CURRENT PROTECTION
1FEATURES – Adjustable Output from 1.2 V to 5.5 V
• Controlled Baseline
2 – Custom Outputs Available
– One Assembly
– One Test Site APPLICATIONS
• Portable/Battery-Powered Equipment
– One Fabrication Site
• Post-Regulation for Switching Supplies
• Extended Temperature Performance of
• Noise-Sensitive Circuitry Such as VCOs
–55°C to 125°C
• Point of Load Regulation for DSPs, FPGAs,
• Enhanced Diminishing Manufacturing Sources ASICs, and Microprocessors
(DMS) Support
• Enhanced Product-Change Notification
Optional Optional
• Qualification Pedigree (1)
• Stable With No Output Capacitor or Any Value VIN IN OUT VOUT
or Type of Capacitor TPS736xx
• Input Voltage Range of 1.7 V to 5.5 V EN GND NR
• Ultra-Low Dropout Voltage: 75 mV Typical

• Excellent Load Transient Response—With or Optional
Without Optional Output Capacitor
• New NMOS Topology Delivers Low Reverse Typical Application Circuit for Fixed-Voltage Versions
Leakage Current
• Low Noise: 30 µVRMS Typical
(10 Hz to 100 kHz)
• 0.5% Initial Accuracy
• 1% Overall Accuracy Over Line, Load, and
Temperature
• Less Than 1-µA Max IQ in Shutdown Mode
• Thermal Shutdown and Specified Min/Max
Current Limit Protection
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.2 V to 3.3 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits. N/C - No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
DESCRIPTION
The TPS736xx family of low-dropout (LDO) linear voltage regulators uses a new topology—an NMOS pass
element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR and
allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground-pin
current that is nearly constant over all values of output current.
The TPS736xx uses an advanced BiCMOS process to yield high precision while delivering low dropout voltages
and low ground-pin current. Current consumption, when not enabled, is under 1 µA and ideal for portable
applications. The low output noise (30 µVRMS with 0.1-µF CNR) is ideal for powering VCOs. These devices are
protected by thermal shutdown and foldback current limit.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
PRODUCT VOUT (1)
xx is normal output voltage (for example, 25 = 2.5 V, 01 = Adjustable (2)).
TPS736xxMyyyREP yyy is package designator.
z is package quantity.
(1) Additional output voltages from 1.25 V to 4.3 V in 100 mV increments are available on a quick-turn basis using innovative factory
EEPROM programming. Minimum order quantities apply; contact TI for details and availability.
(2) For fixed 1.2-V operation, tie FB to OUT.
ORDERING INFORMATION (1)
TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
TPS73601MDBVREP PJRM
TPS73615MDBVREP T59
TPS73618MDBVREP T60
SOT23 - DBV TPS73625MDBVREP T61
–55°C to 125°C TPS73630MDBVREP T62
TPS73632MDBVREP T63
TPS73633MDBVREP T64
SOT223 - DCQ TPS73601MDCQREP PWZM
SON - DRB TPS73601MDRBREP PMNM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TERMINAL FUNCTIONS
SOT23 SOT223 3x3 SON
NAME (DBV) (DCQ) (DRB) DESCRIPTION
PIN NO. PIN NO. PIN NO.
IN 1 1 8 Unregulated input supply
GND 2 3, 6 4, Pad Ground
EN 3 5 5 Enable. Driving EN high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. See the Shutdown section under Applications Information for more details.
EN can be connected to IN if not used.
NR 4 4 3 Fixed-voltage versions only. Connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap, reducing output noise to low levels.
FB 4 4 3 Feedback. Adjustable-voltage version only. This is the input to the control loop error
amplifier and is used to set the output voltage of the device.
OUT 5 2 1 Output of the regulator. There are no output capacitor requirements for stability.
2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TPS73633-EP
16
14
12
Years estimated life
10
0
100 110 120 130 140 150 160
Continuous TJ − 5C
A. TJ = TJA × W + TA (Standard. JESD 51 conditions)
Figure 1. TPS736xxDBVzEP Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS73633-EP
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted (1)
UNIT
VIN range –0.3 to 6 V
VEN range –0.3 to 6 V
VOUT range –0.3 to 5.5 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, TJ –55 to 150 °C
Storage temperature range –65 to 150 °C
Human-Body Model - HBM 2 kV
ESD rating
Charged-Device Model - CDM 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS (1)

DERATING FACTOR TA ≤ 25°C TA = 70°C TA = 85°C
BOARD PACKAGE RθJC RθJA
ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
Low-K (2) DBV 64°C/W 255°C/W 3.9 mW/°C 392 mW 216 mW 157 mW
High-K (3) DBV 64°C/W 180°C/W 5.6 mW/°C 556 mW 306 mW 222 mW
Low-K (2) DCQ 15°C/W 53°C/W 18.9 mW/°C 1887 mW 1038 mW 755 mW
(3)
High-K DCQ 15°C/W 45°C/W 22.2 mW/°C 2222 mW 1222 mW 889 mW
High-K (3) (4) DRB 1.2°C/W 40°C/W 25.0 mW/°C 2500 mW 1375 mW 1000 mW
(1) See the Thermal Protection section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 in × 3 in, two-layer board with 2 oz copper traces on top of the
board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 in × 3 in, multilayer board with 1 oz internal power and ground
planes, and 2-oz copper traces on the top and bottom of the board.
(4) Based on preliminary thermal simulations.

TPS73633-EP
ELECTRICAL CHARACTERISTICS
over operating temperature range (TA = –55°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range (1) (2)
1.7 5.5 V
VFB Internal reference (TPS73601) TJ = 25°C 1.198 1.2 1.21 V
Output voltage range 5.5 –
VFB V
(TPS73601) VDO
VOUT Nominal TJ = 25°C –0.5% 0.5%
Accuracy (1) Over VIN, IOUT, VOUT + 0.5 V ≤ VIN ≤ 5.5 V,
–1% ±0.5% 1%
and T 10 mA ≤ IOUT ≤ 400 mA
ΔVOUT%/ΔVIN Line regulation (1) VO(nom) + 0.5 V ≤ VIN ≤ 5.5 V 0.01 %/V
1 mA ≤ IOUT ≤ 400 mA 0.002
ΔVOUT%/ΔIOUT Load regulation %/mA
10 mA ≤ IOUT ≤ 400 mA 0.0005
Dropout voltage (3)
VDO IOUT = 400 mA 75 200 mV
(VIN = VOUT(nom) – 0.1 V)
ZO(DO) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO 0.25 Ω
ICL Output current limit VOUT = 0.9 × VOUT(nom) 400 650 800 mA
ISC Short-circuit current VOUT = 0 V 450 mA
IREV Reverse leakage current (4) (–IIN) VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT 0.1 15 µA
IOUT = 10 mA (IQ) 400 550
IGND Ground-pin current µA
IOUT = 400 mA 800 1000
ISHDN Shutdown current (IGND) VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V 0.02 1 µA
IFB FB pin current (TPS73601) 0.1 0.45 µA
Power-supply rejection ratio f = 100 Hz, IOUT = 400 mA 58
PSRR dB
(ripple rejection) f = 10 kHz, IOUT = 400 mA 37
Output noise voltage COUT = 10 µF, No CNR 27 × VOUT
VN µVRMS
BW = 10 Hz to 100 kHz COUT = 10 µF, CNR = 0.01 µF 8.5 × VOUT
VOUT = 3 V, RL = 30 Ω, COUT = 1 µF,
tSTR Startup time 600 µs
CNR = 0.01 µF
VEN(HI) Enable high (enabled) 1.7 VIN V
VEN(LO) Enable low (shutdown) 0 0.5 V
IEN(HI) Enable pin current (enabled) VEN = 5.5 V 0.02 0.1 µA
Shutdown, temperature increasing 160
TSD Thermal shutdown temperature °C
Reset, temperature decreasing 140
TA Operating ambient temperature -55 125 °C
(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.

(2) For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output locks to VIN and may result in a damaging over-voltage level on the output. To avoid
this situation, disable the device before powering down the VIN.
(3) VDO is not measured for the TPS73615 (VOUT(nom) = 1.5 V) since minimum VIN = 1.7 V.
(4) See the Applications section for more information.

TPS73633-EP
FUNCTIONAL BLOCK DIAGRAMS
IN
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
Current
Limit OUT
GND 8 kW
R1
R1 + R2 = 80 kW R2
NR
Figure 2. Fixed-Voltage Version
IN Standard 1% Resistor
Values for Common
Output Voltages
VO R1 R2
4-MHz
Charge Pump 1.2 V Short Open
1.5 V 23.2 kΩ 95.3 kΩ
EN Thermal
1.8 V 28 kΩ 56.2 kΩ
Protection
Ref 2.5 V 39.2 kΩ 36.5 kΩ
Servo 2.8 V 44.2 kΩ 33.2 kΩ
27 kW 3V 46.4 kΩ 30.9 kΩ
Bandgap
Error 3.3 V 52.3 kΩ 30.1 kΩ
Amp
OUT NOTE: VOUT = (R1 + R2)/R2 × 1.204;
Current R1R2 ≅ 19 kΩ for best
Limit accuracy
GND 8 kW 80 kW
R1
FB
R2
Figure 3. Adjustable-Voltage Version

TPS73633-EP
TYPICAL CHARACTERISTICS
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
LOAD REGULATION LINE REGULATION

0.5 0.20
Referred to IOUT = 10 mA Referred to VIN = VOUT + 0.5 V at IOUT = 10 mA
0.4 0.15
0.3 −40°C
25°C 0.10
Change in VOUT (%)

Change in VOUT (%)
0.2 125°C 125°C 25°C

0.05
0.1
0 0
−0.1 −0.05
−0.2 −40°C
−0.10
−0.3
−0.15
−0.4
−0.5 −0.20
0 50 100 150 200 250 300 350 400 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
IOUT (mA) VIN − VOUT (V)
Figure 4. Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE

100 100
TPS73625DBV
TPS73625DBV IOUT = 400 mA
125°C
80 80
60 60
VDO (mV)
VDO (mV)
25°C
40 40
−40°C
20 20
0 0
0 50 100 150 200 250 300 350 400 −50 −25 0 25 50 75 100 125
IOUT (mA) Temperature (°C)
Figure 6. Figure 7.
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM

30 18
IOUT = 10 mA IOUT = 10 mA
16
25 All Voltage Versions
14
Percent of Units (%)
Percent of Units (%)
20 12
10
15
8
10 6
4
5
2
0 0
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
10
20
30
40
50
60
70
80
90
100
VOUT Error (%) Worst Case dVOUT/dT (ppm/°C)

Figure 8. Figure 9.

TPS73633-EP
TYPICAL CHARACTERISTICS (continued)

GROUND-PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE

1000 1000
IOUT = 400 mA
900 900
800 800
700 700
600 600
IGND (µA)
I GND (µA)
500 500
400 400
300 300
200 VIN = 5.5 V 200 VIN = 5.5 V
VIN = 4 V VIN = 3 V
100 VIN = 2 V 100 VIN = 2 V
0 0
0 100 200 300 400 −50 −25 0 25 50 75 100 125
IOUT (mA) Temperature (°C)
Figure 10. Figure 11.
CURRENT LIMIT vs VOUT GROUND PIN CURRENT in SHUTDOWN

(FOLDBACK) vs TEMPERATURE
800 1
VENABLE = 0.5 V
700 VIN = VO + 0.5 V
ICL
600
Current Limit (mA)
500
IGND (µA)
ISC
400 0.1
300
200
100
TPS73633
0 0.01
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 −50 −25 0 25 50 75 100 125
VOUT (V) Temperature (°C)
CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE

800 800
750 750
700 700
Current Limit (mA)
Current Limit (mA)
650 650
600 600
550 550
500 500
450 450
400 400
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100 125
VIN (V) Temperature (°C)

TPS73633-EP

PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN – VOUT

90 40
80 COUT = Any COUT = 1 µF 35
70 IOUT = 1 mA 30
Ripple Rejection (dB)
COUT = 10 µF
60
25
PSRR (dB)
IOUT = 100 mA
50 IOUT = 1 mA COUT = 1 µF
20
COUT = Any
40
15
30
10
20 IOUT = 100 mA Frequency = 100 kHz
COUT = 10 µF
10 IOUT = Any 5 COUT = 10 µF
VIN = VOUT + 1 V COUT = 0 µF VOUT = 2.5 V
0 0
10 100 1k 10k 100k 1M 10M 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency (Hz) VIN − VOUT (V)
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY

CNR = 0 µF CNR = 0.01 µF
1 1
COUT = 1 µF
COUT = 1 µF
eN (µV/√Hz)
eN (µV/√Hz)
COUT = 0 µF
0.1 0.1
COUT = 10 µF
COUT = 0 µF
COUT = 10 µF

0.01 0.01
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR

60 140
VOUT = 5 V
VOUT = 5 V
50 120
100
40
VOUT = 3.3 V
VN (RMS)
VN (RMS)
VOUT = 3.3 V 80
30
60
20
40 VOUT = 1.5 V
VOUT = 1.5 V
10
COUT = 0 µF 20
COUT = 0 µF
10 Hz < Frequency < 100 kHz 10 Hz < Frequency < 100 kHz
0 0
0.1 1 10 1p 10p 100p 1n 10n
COUT (µF) CNR (F)

TPS73633-EP

TPS73633 TPS73633
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
VIN = 3.8 V COUT = 0 µF IOUT = 400 mA
100 mV/tick VOUT
COUT = 0 µF
50 mV/div VOUT
COUT = 1 µF
50 mV/tick VOUT
COUT = 10 µF COUT = 100 µF

20 mV/tick VOUT 50 mV/div VOUT
5.5 V dVIN
400 mA = 0.5 V/µs
I OUT 4.5 V dt
50 mA/tick
10 mA 1 V/div VIN
10 µs/div 10 µs/div
TPS73633 TPS73633
TURNON RESPONSE TURNOFF RESPONSE
RL = 1 kΩ RL = 20 Ω
COUT = 0 µF VOUT
COUT = 10 µF
RL = 20 Ω RL = 20 Ω
1V/div COUT = 1 µF 1 V/div COUT = 1 µF
RL = 1 kΩ
RL = 20 Ω COUT = 0 µF
COUT = 10 µF
VOUT
2V 2V
VEN
1V/div 1 V/div
0V 0V
VEN

TPS73633
POWER UP/POWER DOWN IENABLE vs TEMPERATURE
6 10
5
VIN
4
VOUT
1
3
IENABLE (nA)
Volts
1
0.1
0
−1
−2 0.01
50 ms/div −50 −25 0 25 50 75 100 125
Temperature (°C)

TPS73633-EP

TPS73601 TPS73601
RMS NOISE VOLTAGE vs CADJ IFB vs TEMPERATURE
60 160
55 140
50 120
45 100
VN (rms)
IFB (nA)
40 80
35 60
30 VOUT = 2.5 V 40
COUT = 0 µF
25 R1 = 39.2 kΩ 20
10 Hz < Frequency < 100 kHz
20 0
10p 100p 1n 10n −50 −25 0 25 50 75 100 125
CFB (F) Temperature (°C)
TPS73601 TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10 nF VOUT = 2.5 V
R1 = 39.2 kΩ CFB = 10 nF
COUT = 0 µF COUT = 0 µF
200 mV/div VOUT 100 mV/div VOUT
COUT = 10 µF
100 mV/div VOUT
COUT = 10 µF
200 mV/div VOUT
4.5 V
400 mA 3.5 V
VIN
10 mA
IOUT

TPS73633-EP
APPLICATION INFORMATION
supply near the regulator. This counteracts reactive
The TPS736xx belongs to a family of new-generation input sources and improves transient response, noise
LDO regulators that use an NMOS pass transistor to rejection, and ripple rejection. A higher-value
achieve ultra-low-dropout performance, reverse capacitor may be necessary if large, fast rise-time
current blockage, and freedom from output capacitor load transients are anticipated, or the device is
constraints. These features, combined with low noise located several inches from the power source.
and an enable input, make the TPS736xx ideal for
portable applications. This regulator family offers a The TPS736xx does not require an output capacitor
wide selection of fixed-output voltage versions and an for stability and has maximum phase margin with no
adjustable-output version. All versions have thermal capacitor. It is designed to be stable for all available
and overcurrent protection, including foldback current types and values of capacitors. In applications where
limit. VIN − VOUT < 0.5 V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
Figure 32 shows the basic circuit connections for the COUT and total ESR drops below 50 Ω. Total ESR
fixed-voltage models. Figure 33 shows the includes all parasitic resistance, including capacitor
connections for the adjustable-output version ESR and board, socket, and solder-joint resistance.
(TPS73601). R1 and R2 can be calculated for any In most applications, the sum of capacitor ESR and
output voltage using the formula in Figure 33. Sample trace resistance meets this requirement.
resistor values for common output voltages are
shown in Figure 3. For the best accuracy, make the
parallel combination of R1 and R2 approximately 19 Output Noise
kΩ. A precision band-gap reference is used to generate
Optional input capacitor. Optional output capacitor.
the internal reference voltage, VREF. This reference is
May improve source May improve load transient, the dominant noise source within the TPS736xx and
impedance, noise, or PSRR. noise, or PSRR. it generates approximately 32 µVRMS (10 Hz to
100 kHz) at the reference output (NR). The regulator
VIN IN OUT VOUT
control loop gains up the reference noise with the
TPS736xx same gain as the reference voltage, so that the noise
EN GND NR voltage of the regulator is approximately given by:
Optional bypass
(R1 ) R2) VOUT
V N + 32 mVRMS + 32 mVRMS
capacitor to reduce R2 VREF (1)
output noise
Since the value of VREF is 1.2 V, this relationship
Figure 32. Typical Application Circuit for reduces to:
Fixed-Voltage Versions
V N(mVRMS) + 27
mV RMS
V
ǒ
V OUT(V) Ǔ (2)
Optional input capacitor. Optional output capacitor.
May improve source May improve load transient,
impedance, noise, or PSRR. noise, or PSRR. for the case of no CNR.
VIN IN OUT VOUT An internal 27-kΩ resistor in series with the noise
TPS736xx R1 CFB
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
EN GND FB capacitor, CNR, is connected from NR to ground. For
R2 CNR = 10 nF, the total noise in the 10-Hz to 100-kHz
bandwidth is reduced by a factor of ~3.2, giving the
(R1 + R2) Optional capacitor
VOUT = × 1.204 reduces output noise
approximate relationship:
R1
and improves
transient response. V N(mVRMS) + 8.5
mV RMS
V
ǒ
V OUT(V) Ǔ (3)
Figure 33. Typical Application Circuit for
Adjustable-Voltage Versions for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise
Input and Output Capacitor Requirements Voltage vs CNR in Figure 21.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1-µF to 1-µF low ESR capacitor across the input

TPS73633-EP
The TPS73601 adjustable version does not have the avoid degraded transient response. The boundary of
noise-reduction pin available. However, connecting a this transient dropout region is approximately twice
feedback capacitor, CFB, from the output to the FB pin the dc dropout. Values of
reduces output noise and improves load transient VIN – VOUT above this line ensure normal transient
performance. response.
The TPS736xx uses an internal charge pump to Operating in the transient dropout region can cause
develop an internal supply voltage sufficient to drive an increase in recovery time. The time required to
the gate of the NMOS pass element above VOUT. The recover from a load transient is a function of the
charge pump generates ~250 µV of switching noise magnitude of the change in load current rate, the rate
at ~4 MHz; however, charge-pump noise contribution of change in load current, and the available
is negligible at the output of the regulator for most headroom (VIN to VOUT voltage drop). Under
values of IOUT and COUT. worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
Board Layout Recommendation to Improve the TPS736xx can take a couple of hundred
PSRR and Noise Performance microseconds to return to the specified regulation
accuracy.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that Transient Response
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected The low open-loop output impedance provided by the
only at the GND pin of the device. In addition, the NMOS pass element in a voltage-follower
ground connection for the bypass capacitor should configuration allows operation without an output
connect directly to the GND pin of the device. capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
Internal Current Limit 1 µF) from the output pin to ground reduces
undershoot magnitude but increases duration. In the
The TPS736xx internal current limit helps protect the adjustable version, the addition of a capacitor, CFB,
regulator during fault conditions. Foldback helps to from the output to the adjust pin also improves the
protect the regulator from damage during output transient response.
short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 12 for a graph of The TPS736xx does not have active pulldown when
IOUT vs VOUT. the output is overvoltage. This allows applications
that connect higher voltage sources, such as
Shutdown alternate power supplies, to the output. This also
results in an output overshoot of several percent if
The enable (EN) pin is active high and is compatible load current quickly drops to zero when a capacitor is
with standard TTL-CMOS levels. VEN below 0.5 V connected to the output. The duration of overshoot
(max) turns the regulator off and drops the ground-pin can be reduced by adding a load resistor. The
current to approximately 10 nA. When shutdown overshoot decays at a rate determined by output
capability is not required, EN can be connected to capacitor COUT and the internal/external load
VIN. When a pullup resistor is used, and operation resistance. The rate of decay is given by:
down to 1.8 V is required, use pullup resistor values Fixed-voltage version:
below 50 kΩ. VOUT
dVńdt +
Dropout Voltage C OUT 80 kW ø R LOAD (4)
The TPS736xx uses an NMOS pass transistor to Adjustable-voltage version:

achieve extremely low dropout. When (VIN – VOUT) is V OUT
dVńdt +
less than the dropout voltage (VDO), the NMOS pass C OUT 80 kW ø (R 1 ) R 2) ø R LOAD (5)
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
For large step changes in load current, the TPS736xx
requires a larger voltage drop from VIN to VOUT to

TPS73633-EP
Reverse Current 35°C above the maximum expected ambient

condition of the application. This produces a
The NMOS pass element of the TPS736xx provides worst-case junction temperature of 125°C at the
inherent protection against current flow from the highest expected ambient temperature and
output of the regulator to the input when the gate of worst-case load.
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element, The internal protection circuitry of the TPS736xx has
EN must be driven low before the input voltage is been designed to protect against overload conditions.
removed. If this is not done, the pass element may be It was not intended to replace proper heatsinking.
left on due to stored charge on the gate. Continuously running the TPS736xx into thermal
shutdown degrades reliability.
After EN is driven low, no bias voltage is needed on
any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out Power Dissipation
of the IN pin due to voltage applied on the OUT pin. The ability to remove heat from the die is different for
There is additional current flowing into the OUT pin each package type, presenting different
due to the 80-kΩ internal resistor divider to ground considerations in the PCB layout. The PCB area
(see Figure 2 and Figure 3). around the device that is free of other components
moves the heat from the device to the ambient air.
For the TPS73601, reverse current may flow when
Performance data for JEDEC low- and high-K boards
VFB is more than 1 V above VIN.
are shown in the Power Dissipation Ratings table.
Using heavier copper increases the effectiveness in
Thermal Protection removing heat from the device. The addition of plated
Thermal protection disables the output when the through-holes to heat-dissipating layers also
junction temperature rises to approximately 160°C, improves the heatsink effectiveness.
allowing the device to cool. When the junction Power dissipation depends on input voltage and load
temperature cools to approximately 140°C, the output conditions. Power dissipation is equal to the product
circuitry is again enabled. Depending on power of the output current times the voltage drop across
dissipation, thermal resistance, and ambient the output pass element (VIN to VOUT):
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator, P D + (VIN * VOUT) I OUT (6)
protecting it from damage due to overheating. Power dissipation can be minimized by using the
Any tendency to activate the thermal protection circuit lowest-possible input voltage necessary to ensure the
indicates excessive power dissipation or an required output voltage.
inadequate heatsink. For reliable operation, junction
temperature should be limited to 125°C maximum. To Package Mounting
estimate the margin of safety in a complete design
Solder-pad footprint recommendations for the
(including heatsink), increase the ambient
TPS736xx are presented in application bulletin Solder
temperature until the thermal protection is triggered;
Pad Recommendations for Surface-Mount Devices
use worst-case loads and signal conditions. For good
(AB-132), available from the TI web site at
reliability, thermal protection should trigger at least
www.ti.com.

TPS73633-EP
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS73601MDBVREP ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 PJRM Samples
TPS73601MDCQREP ACTIVE SOT-223 DCQ 6 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 PWZM Samples
TPS73601MDRBREP ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 PMNM Samples
TPS73615MDBVREP ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T59 Samples
TPS73633MDBVREPG4 ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -55 to 125 Samples
V62/06626-01XE ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 PJRM Samples
V62/06626-01YE ACTIVE SOT-223 DCQ 6 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 PWZM Samples
V62/06626-01ZE ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 PMNM Samples
V62/06626-02XE ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T59 Samples
(1)
The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73601MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73601MDCQREP SOT-223 DCQ 6 2500 330.0 12.4 7.1 7.45 1.88 8.0 12.0 Q3
TPS73601MDRBREP SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73601MDBVREP SOT-23 DBV 5 3000 200.0 183.0 25.0
TPS73601MDCQREP SOT-223 DCQ 6 2500 346.0 346.0 41.0
TPS73601MDRBREP SON DRB 8 3000 367.0 367.0 38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCQ0006A SCALE 2.000
SOT - 1.8 mm max height
PLASTIC SMALL OUTLINE
7.26
6.86
0.08 3.6
B
3.4 A
PIN 1 NOTE 3
INDEX AREA
1.27
TYP
6.6
6.4
NOTE 3
5.08 6
3.05
2.95
0.1 C A B
5
0.51
5X
0.10 0.41
(1.6)
0.02 0.1 C A B
1.8 MAX
0.32
0.25 0.24
GAGE PLANE
1.14 SEATING PLANE

C 0 -8 0.91
TYP
4214845/C 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DCQ0006A SOT - 1.8 mm max height
(6)
1
0.2 TYP
4X (1.27)
(1.35)
SYMM
(3.2)
6
(R0.05) TYP
5X (0.65) (0.775) TYP
5
(2.05)
5X (2.05) PKG
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MAX 0.07 MIN
ALL AROUND ALL AROUND
SOLDER MASK DETAILS
4214845/C 11/2021
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCQ0006A SOT - 1.8 mm max height
(6)
1
(0.56) TYP
(1.27) TYP
(0.755)
SYMM
(R0.05) TYP 4X (1.31)
4X (0.92)
5X (0.65)
5
5X (2.05) SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214845/C 11/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/F 06/2021
NOTES:
per ASME Y14.5M.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)

SCALE:15X
4214839/F 06/2021
NOTES: (continued)
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRB0008A SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
PIN 1 INDEX AREA

3.1
2.9
C
1 MAX
SEATING PLANE
0.05 DIM A
0.00 0.08 C
OPT 1 OPT 2
1.5 0.1 (0.1) (0.2)
4X (0.23)
EXPOSED (DIM A) TYP
THERMAL PAD
4 5
2X
1.95 1.75 0.1
8
1
6X 0.65
0.37
8X
0.25
PIN 1 ID 0.1 C A B
(OPTIONAL)
(0.65) 0.05 C
0.5
8X
0.3
4218875/A 01/2018
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
DRB0008A VSON - 1 mm max height
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8X (0.31) 1 8
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP (0.23)
(0.5)
(2.8)

EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
EXPOSED EXPOSED
METAL METAL
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
DRB0008A VSON - 1 mm max height
(0.65)
4X (0.23)
SYMM
METAL
8X (0.6) TYP
4X
(0.725)
8X (0.31) 1 8
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)

EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

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TPS73601-EP, TPS73615-EP, TPS73618-EP

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP

CAP-FREE NMOS 400 mA LOW-DROPOUT REGULATORS

or Type of Capacitor TPS736xx

• Input Voltage Range of 1.7 V to 5.5 V EN GND NR

• Ultra-Low Dropout Voltage: 75 mV Typical

2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

ABSOLUTE MAXIMUM RATINGS

POWER DISSIPATION RATINGS (1)

4 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.

Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

FUNCTIONAL BLOCK DIAGRAMS

Figure 2. Fixed-Voltage Version

Figure 3. Adjustable-Voltage Version

6 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

LOAD REGULATION LINE REGULATION

Change in VOUT (%)

0.2 125°C 125°C 25°C

DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE

OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM

Percent of Units (%)

VOUT Error (%) Worst Case dVOUT/dT (ppm/°C)

Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

TYPICAL CHARACTERISTICS (continued)

GROUND-PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE

CURRENT LIMIT vs VOUT GROUND PIN CURRENT in SHUTDOWN

CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE

Current Limit (mA)

8 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TYPICAL CHARACTERISTICS (continued)

PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN – VOUT

NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY

IOUT = 150 mA IOUT = 150 mA

RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR

Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

TYPICAL CHARACTERISTICS (continued)

COUT = 10 µF COUT = 100 µF

100 µs/div 100 µs/div

10 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

TYPICAL CHARACTERISTICS (continued)

Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

12 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

The TPS736xx uses an NMOS pass transistor to Adjustable-voltage version:

Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Reverse Current 35°C above the maximum expected ambient

14 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated

Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP

ACTIVE: Product device recommended for new designs.

TAPE AND REEL INFORMATION

*All dimensions are nominal

*All dimensions are nominal