TM

HC55185

Data Sheet April 2000 File Number 4831.2

VoIP Ringing SLIC Family Features

The RSLIC-VoIP family of • Onboard Ringing Generation
ringing subscriber line • Compatible with Existing HC5518x Devices
interface circuits (RSLIC)
• Low Standby Power Consumption (75V, 65mW)
supports analog Plain Old
• Reduced Idle Channel Noise
Telephone Service (POTS) in
short and medium loop length, wireless and wireline • Programmable Transient Current Limit
applications. Ideally suited for remote subscriber units, this • Improved Off Hook Software Interface
family of products offers flexibility to designers with high • Integrated MTU DC Characteristics
ringing voltage and low power consumption system • Low External Component Count
requirements.
• Silent Polarity Reversal
The RSLIC-VoIP family operates to 100V which translates • Pulse Metering and On Hook Transmission
directly to the amount of ringing voltage supplied to the end • Tip Open Ground Start Operation
subscriber. With the high operating voltage, subscriber loop
• Thermal Shutdown with Alarm Indicator
lengths can be extended to 500Ω (i.e., 5,000 feet) and
• 28 Lead Surface Mount Packaging
beyond.
• Dielectric Isolated (DI) High Voltage Design
Other key features across the product family include: low
power consumption, ringing using sinusoidal or trapezoidal Applications
waveforms, robust auto-detection mechanisms for when
subscribers go on or off hook, and minimal external discrete • Voice Over Internet Protocol (VoIP)
application components. Integrated test access features are • Cable Modems
also offered on selected products to support loopback • Voice Over DSL (VoDSL)
testing as well as line measurement tests. • Short Loop Access Platforms
There are five product offerings of the HC55185 with each • Remote Subscriber Units
version providing voltage grades of high battery voltage and • Terminal Adapters
longitudinal balance. The voltage feed amplifier design uses
low fixed loop gains to achieve high analog performance with Related Literature
low susceptibility to system induced noise. • AN9814, User’s Guide for Development Board
• AN9824, Modeling of the AC Loop
• Interfacing to DSP CODECs (Contact Factory)

Block Diagram
POL CDC VBL VBH

ILIM DC BATTERY RINGING

CONTROL SWITCH PORT VRS

TIP 2-WIRE
PORT VRX
RING TRANSMIT 4-WIRE VTX
SENSING PORT -IN
TRANSIENT
VFB
TL CURRENT
LIMIT

SW+ F2
TEST DETECTOR CONTROL
ACCESS LOGIC LOGIC F1
SW- F0

RTD RD E0 DET ALM BSEL SWC

4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
RSLIC18™ is a trademark of Intersil Corporation.
 HC55185

Ordering Information (PLCC Package Only)

LONGITUDINAL FULL TEMP. PACKAGE
PART NUMBER HIGH BATTERY (VBH) BALANCE TEST RANGE oC PACKAGE NO.

100V 85V 75V 58dB 53dB

HC55185AIM • • • -40 to 85 28 Ld PLCC N28.45

HC55185BIM • • • -40 to 85 28 Ld PLCC N28.45

HC55185CIM • • • -40 to 85 28 Ld PLCC N28.45

HC55185DIM • • • -40 to 85 28 Ld PLCC N28.45

HC55185ECM • • 0 to 75 28 Ld PLCC N28.45

HC55185FCM • • • 0 to 85 28 Ld PLCC N28.45

HC5518XEVAL1 Evaluation board platform, including CODEC.

Also available in Tape and Reel

Device Operating Modes

MODE F2 F1 F0 E0 = 1 E0 = 0 HC55185A HC55185B HC55185C HC55185D HC55185E HC55185F

Low Power Standby 0 0 0 SHD GKD • • • • • •

Forward Active 0 0 1 SHD GKD • • • • • •
Unused 0 1 0 n/a n/a

Reverse Active 0 1 1 SHD GKD • • • • • •

Ringing 1 0 0 RTD RTD • • • • • •
Forward Loop Back 1 0 1 SHD GKD • • • •
Tip Open 1 1 0 SHD GKD • • • •
Power Denial 1 1 1 n/a n/a • • • • • •

Device Pinout
HC55185
(PLCC)
TOP VIEW
BGND

RING

ILIM
VBH
VBL

RD
TIP

4 3 2 1 28 27 26

SW+ 5 25 RTD
SW- 6 24 CDC

SWC 7 23 VCC
F2 8 22 -IN
F1 9 21 VFB
F0 10 20 VTX
E0 11 19 VRX
12 13 14 15 16 17 18
BSEL

TL
POL

VRS
DET

ALM

AGND

4-2
 HC55185

Absolute Maximum Ratings TA = 25oC Thermal Information

Maximum Supply Voltages Thermal Resistance (Typical, Note 1) θJA
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53oC/W
VCC - VBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150oC
Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(PLCC - Lead Tips Only)
Operating Conditions
Temperature Range Die Characteristics
Commercial (C suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBH
Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . +5V, ±5%
Low Battery Power Supply (VBL) . . . . . . . . . . . . . -16V to -52V, ±5%
High Battery Power Supply (VBH)
AIM, CIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VBL to 100V, ±5%
BIM, DIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBL to -85V, ±10%
EIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBL to -75V, ±10%
Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC for industrial (I) grade and TA = 0oC to 85oC for commercial
(C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA.
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RINGING PARAMETERS

VRS Input Impedance (Note 2) 450 - - kΩ

Differential Ringing Gain (Note 3) VRS to 2-wire, RLOAD = ∞ 78 80 82 V/V

Ringing Voltage Total Distortion RL = 1.3 kΩ, VT-R = |VBH| -5 - - 3.0 %

4-Wire to 2-Wire Ringing Off Isolation Active mode, referenced to VRS input - 90 - dB

2-Wire to 4-Wire Transmit Isolation Ringing mode referenced to the differential ringing - 80 - dB
amplitude

Centering Voltage Accuracy Tip, Referenced to VBH/2 + 0.5 - 2.5 - V

Ring, Referenced to VBH/2 + 0.5 - 2.5 - V

AC TRANSMISSION PARAMETERS

Receive Input Impedance (Note 2) 160 - - kΩ

Transmit Output Impedance (Note 2) - - 1 Ω

4-Wire Port Overload Level THD = 1% 3.1 3.5 - VPK

2-Wire Port Overload Level THD = 1% 3.1 3.5 - VPK

2-Wire Return Loss 300Hz - 24 - dB

1kHz - 40 - dB

3.4kHz - 21 - dB

2-Wire Longitudinal Balance (Notes 4, 5) Forward Active, Grade A and B 58 62 - dB

Forward Active, Grade C, D and E 53 59 - dB

4-Wire Longitudinal Balance Forward Active, Grade A and B 58 67 - dB

Forward Active, Grade C, D and E 53 64 - dB

4-3
 HC55185

Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC for industrial (I) grade and TA = 0oC to 85oC for commercial
(C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA.
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

2-Wire to 4-Wire Level Linearity +3 to -40dBm, 1kHz - 0.025 - dB
4-Wire to 2-Wire Level Linearity
-40 to -50dBm, 1kHz - 0.050 - dB
Referenced to -10dBm
-50 to -55dBm, 1kHz - 0.100 - dB

Longitudinal Current Capability (Per Wire) (Note 2) Test for False Detect 20 - - mARMS

Test for False Detect, Low Power Standby 10 - - mARMS

4-Wire to 2-Wire Insertion Loss -0.20 0.00 +0.20 dB

2-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB

4-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB

Forward Active Idle Channel Noise (Note 5) 2-Wire C-Message, T = 25oC - 10 13 dBrnC

4-Wire C-Message, T = 25oC - 4 7 dBrnC

Reverse Active Idle Channel Noise (Note 5) 2-Wire C-Message, T = 25oC - 11 14 dBrnC

4-Wire C-Message, T = 25oC - 5 8 dBrnC

DC PARAMETERS

Off Hook Loop Current Limit Programming Accuracy -8.5 - +8.5 %

Programming Range 15 - 45 mA

Off Hook Transient Current Limit Programming Accuracy -10 - +10 %

Programming Range 40 - 100 mA

Loop Current During Low Power Standby Forward Polarity Only 18 - 26 mA

Open Circuit Voltage VBL = -16V - 8.0 - VDC

(|Tip - Ring|)
VBL = -24V 14 15.5 17 VDC

VBH > -60V 43 49 - VDC

Low Power Standby VBL = -48V - 44.5 - VDC

Open Circuit Voltage
VBH > -60V 43 51.5 - VDC
(Tip - Ring)

Absolute Open Circuit Voltage VRG in LPS and FA - -53 -56 VDC
VTG in RA
VBH > -60V

TEST ACCESS FUNCTIONS

Switch On Voltage IOL = 45mA - 0.30 0.60 V

Loopback Max Battery - - 52 V

LOOP DETECTORS AND SUPERVISORY FUNCTIONS

Switch Hook Programming Range 5 - 15 mA

Switch Hook Programming Accuracy Assumes 1% External Programming Resistor -10 - +10 %

Dial Pulse Distortion - - 1 %

Ring Trip Comparator Threshold 2.3 2.45 2.9 V

Ring Trip Programming Current Accuracy -10 - +10 %

Ground Key Threshold - 12 - mA

Thermal Alarm Output IC Junction Temperature - 175 - oC

4-4
 HC55185

Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC for industrial (I) grade and TA = 0oC to 85oC for commercial
(C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA.
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (F0, F1, F2, E0, SWC)

Input Low Voltage - - 0.8 V

Input High Voltage 2.0 - - V

Input Low Current VIL = 0.4V -20 - - µA

Input High Current VIH = 2.4V - - 1 µA

LOGIC OUTPUTS (DET, ALM)

Output Low Voltage IOL = 5mA - .15 0.4 V

Output High Voltage IOH = 100µA 2.4 3.5 - V

SUPPLY CURRENTS

Low Power Standby, BSEL = 1 ICC - 3.9 6.0 mA

IBH - 0.66 0.90 mA

Forward or Reverse, BSEL = 0 ICC - 4.9 6.5 mA

IBL - 1.2 2.5 mA

Forward, BSEL = 1 ICC - 7.0 9.5 mA

IBL - 0.9 2.0 mA

IBH - 2.2 3.0 mA

Ringing, BSEL = 1 ICC - 6.4 9.0 mA

IBL - 0.3 1.0 mA

IBH - 2.0 3.0 mA

Forward Loopback, BSEL = 0 ICC - 10.3 13.5 mA

IBL - 23.5 32 mA

Tip Open, BSEL = 0 ICC - 3.8 5.5 mA

IBL - .3 1.0 mA

Power Denial, BSEL = 0 or 1 ICC - 4.0 6.0 mA

IBL - 0.22 0.5 mA

ON HOOK POWER DISSIPATION (Note 6)

Forward or Reverse VBL = -24V - 55 - mW

Low Power Standby VBH = -100V - 85 - mW

VBH = -85V - 75 - mW

VBH = -75V - 65 - mW

Ringing VBH = -100V - 250 - mW

VBH = -85V - 230 - mW

VBH = -75V - 225 - mW

OFF HOOK POWER DISSIPATION (Note 6)

Forward or Reverse VBL = -24V - 305 - mW

POWER SUPPLY REJECTION RATIO

4-5
 HC55185

Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC for industrial (I) grade and TA = 0oC to 85oC for commercial
(C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA.
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VCC to 2-Wire f = 300Hz - 40 - dB

f = 1kHz - 35 - dB

f = 3.4kHz - 28 - dB

VCC to 4-Wire f = 300Hz - 45 - dB

f = 1kHz - 43 - dB

f = 3.4kHz - 33 - dB

VBL to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 30 - dB

VBL to 4-Wire 300Hz ≤ f ≤ 3.4kHz - 35 - dB

VBH to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 33 - dB

VBH to 4-Wire 300Hz ≤ f ≤ 1kHz - 40 - dB

1kHz < f ≤ 3.4kHz - 45 - dB

NOTES:
2. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial
design release and upon design changes which would affect these characteristics.
3. Differential Ringing Gain is measured with VRS = 0.795VRMS for -100V devices, VRS = 0.663 VRMS for -85V devices and VRS = 0.575VRMS
for -75V devices.
4. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring terminal.
5. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical
characterization and design.
6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current
limits.

Product Family Cross Reference feature. This programming resistor is connected from pin 16
(TL) to ground. In addition some component values have
The following table provides an ordering and functional cross
been changed to improve overall device performance. The
reference for the existing HC55180 thru HC55184 products
table below lists the component value changes required for
and the new and improved HC55185 product.
the HC55185 application circuit.
TABLE 1. PRODUCT CROSS REFERENCE
TABLE 2. COMPONENT VALUE CHANGES
EXISTING DEVICES FUNCTIONAL EQUIVALENT
REFERENCE HC55180 - 184 HC55185
HC55180CIM, HC55180DIM None Offered
RS 210kΩ 66.5kΩ
HC55181AIM, HC55182AIM HC55185AIM
RP1 ≥ 35Ω ≥ 49Ω
HC55181BIM, HC55182BIM HC55185BIM
RP2 ≥ 35Ω ≥ 49Ω
HC55181CIM, HC55182CIM HC55185CIM
CFB 0.47µ 4.7µ
HC55181DIM, HC55182DIM HC55185DIM

HC55183ECM, HC55184ECM HC55185ECM

The value of RS is based on a 600Ω termination impedance
and RP1 = RP2 = 49.9Ω. Design equations are provided to
Any of the HC55185 products may be used without the calculate RS for other combinations of termination and
battery switch function by shorting the supply pins VBL and protection resistance.
VBH together. This provides compatibility with HC55180
The CFB capacitor must be non-polarized for proper device
type applications which do not require the battery switch.
operation in Reverse Active. Ceramic surface mount
capacitors (1206 body style) are available from Panasonic
Application Circuit Modifications with a 6.3V voltage rating. These can be used for CFB since
The HC55185 basic application circuit is nearly identical to it is internally limited to approximately 3V. The CDC
that of the HC55180 thru HC55184.The HC55185 requires capacitor may be either polarized or non polarized.
an additional resistor to program the transient current limit

4-6
 HC55185

Parametric Improvements FUNCTIONAL DESCRIPTION

The most significant parametric improvement of the Each amplifier is designed to limit source current and sink
HC55185 is reduction in Idle Channel Noise. This current. The diagram below shows the functionality of the
improvement was accomplished by redistributing gains in circuit for the case of limiting the source current. A similar
the impedance matching loop. The impact to the application diagram applies to the sink current limit with current polarity
circuit is the change in the impedance programming resistor changed accordingly.
RS. The redistribution of gains also improves AC
IO/K
performance at the upper end of the voice band.
IREF = 1.21/TL IERR
Functional Improvements 200k

In addition to parametric improvements, internal circuit

changes and application circuit changes have been made to TIP or RING
-
improve the overall device functionality. +
20 IO
ISIG VB/2
Off Hook Interface
The transient behavior of the device in response to mode
changes has been significantly improved. The benefit to the
FIGURE 1. CURRENT LIMIT FUNCTIONAL DIAGRAM
application is reduction or more likely elimination of DET
glitches when off hook events occur. In addition to internal During normal operation, the error current (IERR) is zero and
circuit modifications, the change of CFB value contributes to
the output voltage is determined by the signal current (ISIG)
this functional improvement.
multiplied by the 200k feedback resistor. With the current
Transient Current Limit polarity as shown for ISIG, the output voltage moves positive
The drive current capability of the output amplifiers is with respect to half battery. Assuming the amplifier output is
determined by an externally programmable output current driving a load at a more negative potential, the amplifier
limit circuit which is separate from the DC loop current limit output will source current.
function and programmed at the pin TL. The current limit During excessive output source current flow, the scaled
circuit works in both the source and sink direction, with an output current (IO/K) exceeds the reference current (IREF)
internally fixed offset to prevent the current limit functions forcing an error current (IERR). With the polarity as shown
from turning on simultaneously. The current limit function is the error current subtracts from the signal current, which
provided by sensing line current and reducing the voltage reduces the amplifier output voltage. By reducing the output
drive to the load when the externally set threshold is voltage the source current to the load is decreased and the
exceeded, hence forcing a constant source or sink current. output current is limited.
SOURCE CURRENT PROGRAMMING
DETERMINING THE PROPER SETTING
The source current is externally programmed as shown in
Since this feature programs the maximum output current of
Equation 1.
the device, the setting must be high enough to allow for
1780 (EQ. 1)
R TL = ------------- detection of ring trip or programmed off hook loop current,
I SRC
whichever is greater.
For example a source current limit setting of 50mA is To allow for proper ring trip operation, the transient current
programmed with a 35.6kΩ resistor connected from pin 16 of limit setting should be set at least 25% higher than the peak
the device to ground. This setting determines the maximum ring trip current setting. Setting the transient current 25%
amount of current which flows from Tip to Ring during an off higher should account for programming tolerances of both
hook event until the DC loop current limit responds. In
the ring trip threshold and the transient current limit.
addition this setting also determines the amount of current
which will flow from Tip or Ring when external battery faults If loop current is larger than ring trip current (low REN
occur. applications) then the transient current limit should be set at
least 35% higher than the loop current setting. The slightly
SINK CURRENT PROGRAMMING
higher offset accounts for the slope of the loop current limit
The sink current limit is internally offset 20% higher than the function.
externally programmed source current limit setting.
Attention to detail should be exercised when programming
I SNK = 1.20 × I SRC (EQ. 2)
the transient current limit setting. If ring trip detect does not
If the source current limit is set to 50mA, the sink current occur while ringing, then re-examine the transient current
limit will be 60mA. This setting will determine the amount of limit and ring trip threshold settings.
which flows into Tip or Ring when external ground faults
occur.

4-7
 HC55185

Design Equations 4-WIRE TO 2-WIRE GAIN

The 4-wire to 2-wire gain is defined as the receive gain. It is
Loop Supervision Thresholds
a function of the terminating impedance, synthesized
SWITCH HOOK DETECT impedance and protection resistors. Equation 8 calculates
The switch hook detect threshold is set by a single external the receive gain, G42.
resistor, RSH . Equation 3 is used to calculate the value of RSH.  ZL 
G 42 = – 2  ------------------------------------------ (EQ. 8)
R SH = 600 ⁄ I SH (EQ. 3)  Z O + 2R P + Z L

The term ISH is the desired DC loop current threshold. The When the device source impedance and protection resistors
loop current threshold programming range is from 5mA to equals the terminating impedance, the receive gain equals
15mA. unity.

GROUND KEY DETECT 2-WIRE TO 4-WIRE GAIN

The ground key detector senses a DC current imbalance The 2-wire to 4-wire gain (G24) is the gain from tip and ring to
between the Tip and Ring terminals when the ring terminal is the VTX output. The transmit gain is calculated in Equation 9.
connected to ground. The ground key detect threshold is not  ZO  (EQ. 9)
G 24 = –  ------------------------------------------
externally programmable and is internally fixed to 12mA  Z O + 2R P + Z L
regardless of the switch hook threshold.

RING TRIP DETECT When the protection resistors are set to zero, the transmit
The ring trip detect threshold is set by a single external gain is -6dB.
resistor, RRT. IRT should be set between the peak ringing TRANSHYBRID GAIN
current and the peak off hook current while still ringing. In
The transhybrid gain is defined as the 4-wire to 4-wire gain
R RT = 1800 ⁄ I RT (EQ. 4) (G44).

addition, the ring trip current must be set below the transient  ZO  (EQ. 10)
G 44 = –  ---------------------------------------
current limit, including tolerances. The capacitor CRT, in  O
Z + 2R P + Z L
parallel with RRT, will set the ring trip response time.

Loop Current Limit When the protection resistors are set to zero, the transhybrid
gain is -6dB.
The loop current limit of the device is programmed by the
external resistor RIL. The value of RIL can be calculated COMPLEX IMPEDANCE SYNTHESIS
using Equation 5. Substituting the impedance programming resistor, RS, with a
1760 (EQ. 5) complex programming network provides complex
R IL = -------------
I LIM
impedance synthesis.
The term ILIM is the desired loop current limit. The loop 2-WIRE PROGRAMMING
current limit programming range is from 15mA to 45mA. NETWORK NETWORK
C2 CP
Impedance Matching R1 RS
The impedance of the device is programmed with the
R2 RP
external component RS . RS is the gain setting resistor for
the feedback amplifier that provides impedance matching. If
complex impedance matching is required, then a complex FIGURE 2. COMPLEX PROGRAMMING NETWORK
network can be substituted for RS .
The reference designators in the programming network
RESISTIVE IMPEDANCE SYNTHESIS match the evaluation board. The component RS has a
The source impedance of the device, ZO , can be calculated different design equation than the RS used for resistive
in Equation 6. impedance synthesis. The design equations for each
(EQ. 6) component are provided below.
R S = 133.3 ( Z O )
R S = 133.3 × ( R 1 – 2 ( R P ) ) (EQ. 11)

The required impedance is defined by the terminating

R P = 133.3 × R 2 (EQ. 12)
impedance and protection resistors as shown in Equation 7.
(EQ. 7) (EQ. 13)
Z O = Z L – 2R P C P = C 2 ⁄ 133.3
˙

4-8
 HC55185

Low Power Standby Ring terminal will be clamped by the internal reference. The
same Ring relationships apply when operating from the low
Overview battery voltage. For high battery voltages (VBH) less than or
The low power standby mode (LPS, 000) should be used equal to the internal MTU reference threshold:
during idle line conditions. The device is designed to operate (EQ. 14)
V RING = V BH + 4
from the high battery during this mode. Most of the internal
circuitry is powered down, resulting in low power dissipation.
Loop Current
If the 2-wire (tip/ring) DC voltage requirements are not
critical during idle line conditions, the device may be During LPS, the device will provide current to a load. The
operated from the low battery. Operation from the low current path is through resistors and switches, and will be
battery will decrease the standby power dissipation. function of the off hook loop resistance (RLOOP). This
includes the off hook phone resistance and copper loop
TABLE 3. DEVICE INTERFACES DURING LPS resistance. The current available during LPS is determined
INTERFACE ON OFF NOTES by Equation 15.
Receive x AC transmission, impedance I LOOP = ( – 1 – ( – 49 ) ) ⁄ ( 600 + 600 + R LOOP ) (EQ. 15)
matching and ringing are
Ringing x disabled during this mode.
Internal current limiting of the standby switches will limit the
Transmit x
maximum current to 20mA.
2-Wire x Amplifiers disabled.
Another loop current related parameter is longitudinal
Loop Detect x Switch hook or ground key. current capability. The longitudinal current capability is
reduced to 10mARMS per pin. The reduction in longitudinal
2-Wire Interface
current capability is a result of turning off the Tip and Ring
During LPS, the 2-wire interface is maintained with internal amplifiers.
switches and voltage references. The Tip and Ring
amplifiers are turned off to conserve power. The device will On Hook Power Dissipation
provide MTU compliance, loop current and loop supervision. The on hook power dissipation of the device during LPS is
Figure 3 represents the internal circuitry providing the 2-wire determined by the operating voltages and quiescent currents
interface during low power standby. and is calculated using Equation 16.
GND (EQ. 16)
P LPS = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ
600Ω
The quiescent current terms are specified in the electrical
TIP AMP
tables for each operating mode. Load power dissipation is
TIP not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
RING current may be a charging current required for modern
telephone electronics.
RING AMP
Standby Current Power Dissipation
600Ω
Any standby line current, ISLC , introduces an additional
MTU REF power dissipation term PSLC . Equation 17 illustrates the
FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM power contribution is zero when the standby line current is
zero.
MTU Compliance (EQ. 17)
P SLC = I SLC × ( V BH – 49 + 1 + I SLC x1200 )
Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
If the battery voltage is less than -49V (the MTU clamp is
line conditions. The minimum idle voltage is 42.75V. The
off), the standby line current power contribution reduces to
high side of the MTU range is 56V. The voltage is expressed
Equation 18.
as the difference between Tip and Ring.
P SLC = I SLC × ( V BH + 1 + I SLC x1200 ) (EQ. 18)
The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is limited to a maximum of
Most applications do not specify charging current
-49V (by MTU REF) when operating from either the high or
requirements during standby. When specified, the typical
low battery. A switch and 600Ω resistor connect the MTU
charging current may be as high as 5mA.
reference to the Ring terminal. When the high battery
voltage exceeds the MTU reference of -49V (typically), the

4-9
 HC55185

Forward Active filter is set by the external capacitor CDC . The value of the
external capacitor should be 4.7µF.
Overview
Most applications will operate the device from low battery
The forward active mode (FA, 001) is the primary AC
while off hook. The DC feed characteristic of the device will
transmission mode of the device. On hook transmission, DC
drive Tip and Ring towards half battery to regulate the DC
loop feed and voice transmission are supported during forward
loop current. For light loads, Tip will be near -4V and Ring
active. Loop supervision is provided by either the switch hook
will be near VVBL + 4V. The following diagram shows the DC
detector (E0 = 1) or the ground key detector (E0 = 0). The
feed characteristic.
device may be operated from either high or low battery for on-
hook transmission and low battery for loop feed. VTR(OC) m = (∆VTR/∆IL) = 11.1kΩ

VTR , DC (V)
On-Hook Transmission
The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 3.5VPEAK .
ILOOP (mA) ILIM
When operating from the high battery, the DC voltages at Tip
FIGURE 5. DC FEED CHARACTERISTIC
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for The point on the y-axis labeled VTR(OC) is the open circuit
battery voltages less than -60V as shown in Equation 19. Tip to Ring voltage and is defined by the feed battery
V RING = V BH + 4 (EQ. 19) voltage.
V TR ( OC ) = V BL – 8 (EQ. 20)
Loop supervision is provided by the switch hook detector at
the DET output. When DET goes low, the low battery should The curve of Figure 5 determines the actual loop current for
be selected for DC loop feed and voice transmission. a given set of loop conditions. The loop conditions are
determined by the low battery voltage and the DC loop
Feed Architecture
impedance. The DC loop impedance is the sum of the
The design implements a voltage feed current sense
protection resistance, copper resistance (ohms/foot) and the
architecture. The device controls the voltage across Tip and
telephone off hook DC resistance.
Ring based on the sensing of load current. Resistors are
ISC IA
placed in series with Tip and Ring outputs to provide the
current sensing. The diagram below illustrates the concept. ILIM IB
RB RA
ILOOP (mA)

VIN

RCS
-
VOUT +

RL RC
2RP RLOOP (Ω) RKNEE

FIGURE 6. ILOOP VERSUS RLOOP LOAD CHARACTERISTIC

-
+
KS The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM
loop as the short circuit current ISC.
V TR ( OC ) – 2R P I LIM
By monitoring the current at the amplifier output, a negative I SC = I LIM + ------------------------------------------------------ (EQ. 21)
feedback mechanism sets the output voltage for a defined 1.1e4
load. The amplifier gains are set by resistor ratios (RA , RB , The term ILIM is the programmed current limit, 1760/RIL.
RC) providing all the performance benefits of matched The line segment IA represents the constant current region
resistors. The internal sense resistor, RCS , is much smaller of the loop current limit function.
than the gain resistors and is typically 20Ω for this device.
V TR ( OC ) – R LOOP I LIM
The feedback mechanism, KS , represents the amplifier I A = I LIM + -------------------------------------------------------------- (EQ. 22)
1.1e4
configuration providing the negative feedback.

DC Loop Feed The maximum loop impedance for a programmed loop

current is defined as RKNEE .
The feedback mechanism for monitoring the DC portion of
V TR ( OC )
the loop current is the loop detector. A low pass filter is used R KNEE = ------------------------ (EQ. 23)
I LIM
in the feedback to block voice band signals from interfering
with the loop current limit function. The pole of the low pass

4-10
 HC55185

When RKNEE is exceeded, the device will transition from maintain voice quality. Most applications will use a summing
constant current feed to constant voltage, resistive feed. The amplifier in the CODEC front end as shown below to cancel
line segment IB represents the resistive feed portion of the the echo signal.
load characteristic.
V TR ( OC ) R
I B = ------------------------ (EQ. 24)
R LOOP VRX RA RX OUT
R
Voice Transmission 1:1 RF
VTX RB
The feedback mechanism for monitoring the AC portion of -
TA +
the loop current consists of two amplifiers, the sense TX IN
RS

+
amplifier (SA) and the transmit amplifier (TA). The AC

-
+2.4V
feedback signal is used for impedance synthesis. A detailed -IN
model of the AC feed back loop is provided below. CODEC
HC5518x

R R FIGURE 8. TRANSHYBRID BALANCE INTERFACE

VRX
20
- R The resistor ratio, RF /RB , provides the final adjustment for
TIP +
1:1 the transmit gain, GTX . The transmit gain is calculated using
20 VTX Equation 27.
RING +
- TA  R F
TX = – G 24  -------
-
RS (EQ. 27)
 R B
+
-

R 4R 3R -IN
Most applications set RF = RB , hence the device 2-wire to
4R CFB
- 8K 4-wire equals the transmit gain. Typically RB is greater than
4R + VFB 20kΩ to prevent loading of the device transmit output.
VSA
4R 3R
The resistor ratio, RF /RA , is determined by the transhybrid
gain of the device, G44 . RF is previously defined by the
transmit gain requirement and RA is calculated using
FIGURE 7. AC SIGNAL TRANSMISSION MODEL
Equation 28.
RB
The gain of the transmit amplifier, set by RS , determines the R A = ---------- (EQ. 28)
G 44
programmed impedance of the device. The capacitor CFB
blocks the DC component of the loop current. The ground
Power Dissipation
symbols in the model represent AC grounds, not actual DC
The power dissipated by the device during on hook
potentials.
transmission is strictly a function of the quiescent currents
The sense amp output voltage, VSA , as a function of Tip and for each supply voltage during Forward Active operation.
Ring voltage and load is calculated using Equation 25.
P FAQ = V BH × I + V BL × I BLQ + V CC × I CCQ (EQ. 29)
BHQ
30 (EQ. 25)
V SA = – ( V T – V R ) ------
ZL
Off hook power dissipation is increased above the quiescent
The transmit amplifier provides the programmable gain power dissipation by the DC load. If the loop length is less
required for impedance synthesis. In addition, the output of than or equal to RKNEE , the device is providing constant
this amplifier interfaces to the CODEC transmit input. The current, IA , and the power dissipation is calculated using
output voltage is calculated using Equation 26. Equation 30.
RS P FA ( IA ) = P FA ( Q ) + ( V BL xI A ) – ( R LOOP xI 2 A )
V VTX = – V SA  ---------- (EQ. 26) (EQ. 30)
 8e3

Once the impedance matching components have been If the loop length is greater than RKNEE , the device is
selected using the design equations, the above equations operating in the constant voltage, resistive feed region. The
provide additional insight as to the expected AC node power dissipated in this region is calculated using Equation 31.
voltages for a specific Tip and Ring load. P FA ( IB ) = P FA ( Q ) + ( V BL xI B ) – ( R LOOP xI 2 B ) (EQ. 31)

Transhybrid Balance
Since the current relationships are different for constant
The final step in completing the impedance synthesis design
current versus constant voltage, the region of device
is calculating the necessary gains for transhybrid balance.
operation is critical to valid power dissipation calculations.
The AC feed back loop produces an echo at the VTX output
of the signal injected at VRX . The echo must be cancelled to

4-11
 HC55185

Reverse Active Ringing

Overview Overview
The reverse active mode (RA, 011) provides the same The ringing mode (RNG, 100) provides linear amplification
functionality as the forward active mode. On hook to support a variety of ringing waveforms. A programmable
transmission, DC loop feed and voice transmission are ring trip function provides loop supervision and auto
supported. Loop supervision is provided by either the switch disconnect upon ring trip. The device is designed to operate
hook detector (E0 = 1) or the ground key detector (E0 = 0). from the high battery during this mode.
The device may be operated from either high or low battery.
Architecture
During reverse active the Tip and Ring DC voltage The device provides linear amplification to the signal applied
characteristics exchange roles. That is, Ring is typically 4V to the ringing input, VRS . The differential ringing gain of the
below ground and Tip is typically 4V more positive than device is 80V/V. The circuit model for the ringing path is
battery. Otherwise, all feed and voice transmission shown in the following figure.
characteristics are identical to forward active.
R
R/8
Silent Polarity Reversal -
+
20 - VRS
Changing from forward active to reverse active or vice versa TIP +
is referred to as polarity reversal. Many applications require
5:1 600K
slew rate control of the polarity reversal event. Requirements
+ VBH
range from minimizing cross talk to protocol signalling. 20
+
-
RING 2
-
The device uses an external low voltage capacitor, CPOL , to
set the reversal time. Once programmed, the reversal time R
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC FIGURE 10. LINEAR RINGING MODEL
loop, therefore loop stability is not impacted.
The voltage gain from the VRS input to the Tip output is
The internal circuitry used to set the polarity reversal time is 40V/V. The resistor ratio provides a gain of 8 and the current
shown below. mirror provides a gain of 5. The voltage gain from the VRS
I1 input to the Ring output is -40V/V. The equations for the Tip
POL and Ring outputs during ringing are provided below.
V BH
V T = ----------- + ( 40 × VRS ) (EQ. 33)
2
75kΩ CPOL
V BH
I2 V R = ----------- – ( 40 × VRS ) (EQ. 34)
2

When the input signal at VRS is zero, the Tip and Ring
FIGURE 9. REVERSAL TIMING CONTROL
amplifier outputs are centered at half battery. The device
During forward active, the current from source I1 charges the provides auto centering for easy implementation of
external timing capacitor CPOL and the switch is open. The sinusoidal ringing waveforms. Both AC and DC control of the
internal resistor provides a clamping function for voltages on Tip and Ring outputs is available during ringing. This feature
the POL node. During reverse active, the switch closes and allows for DC offsets as part of the ringing waveform.
I2 (roughly twice I1) pulls current from I1 and the timing Ringing Input
capacitor. The current at the POL node provides the drive to
The ringing input, VRS , is a high impedance input. The high
a differential pair which controls the reversal time of the Tip
impedance allows the use of low value capacitors for AC
and Ring DC voltages.
coupling the ring signal. The VRS input is enabled only
∆time (EQ. 32)
C POL = ---------------- during the ringing mode, therefore a free running oscillator
75000
may be connected to VRS at all times.
Where ∆time is the required reversal time. Polarized
When operating from a battery of -100V, each amplifier, Tip
capacitors may be used for CPOL . The low voltage at the
and Ring, will swing a maximum of 95VP-P. Hence, the
POL pin and minimal voltage excursion ±0.75V, are well
maximum signal swing at VRS to achieve full scale ringing is
suited to polarized capacitors.
approximately 2.4VP-P. The low signal levels are compatible
Power Dissipation with the output voltage range of the CODEC. The digital
The power dissipation equations for forward active operation nature of the CODEC ideally suits it for the function of
also apply to the reverse active mode. programmable ringing generator. See Applications Section.

4-12
 HC55185

Logic Control Forward Loop Back

Ringing patterns consist of silent intervals. The ringing to
Overview
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any The Forward Loop Back mode (FLB, 101) provides test
other operating mode. The most likely candidates are low capability for the device. An internal signal path is enabled
power standby or forward active. Depending on system allowing for both DC and AC verification. The internal 600Ω
requirements, the low or high battery may be selected. terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
Loop supervision is provided with the ring trip detector. The ring mode.
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the Architecture
ringing current, which is then filtered with external components When the forward loop back mode is initiated internal
RRT and CRT. The resistor RRT sets the trip threshold and the switches connect a 600Ω load across the outputs of the Tip
capacitor CRT sets the trip response time. Most applications will and Ring amplifiers.
require a trip response time less than 150ms.
TIP
Three very distinct actions occur when the devices detects a
TIP AMP
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the 600Ω
detector output. The latch is cleared when the operating RING AMP
mode is changed externally. Second, the VRS input is
RING
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode. FIGURE 11. FORWARD LOOP BACK INTERNAL TERMINATION

Power Dissipation DC Verification

The power dissipation during ringing is dictated by the load When the internal signal path is provided, DC current will
driving requirements and the ringing waveform. The key to valid flow from Tip to Ring. The DC current will force DET low,
power calculations is the correct definition of average and RMS indicating the presence of loop current. In addition, the ALM
currents. The average current defines the high battery supply output will also go low. This does not indicate a thermal
current. The RMS current defines the load current. alarm condition. Rather, proper logic operation is verified in
The cadence provides a time averaging reduction in the the event of a thermal shutdown. In addition to verifying
peak power. The total power dissipation consists of ringing device functionality, toggling the logic outputs verifies the
power, Pr , and the silent interval power, Ps . interface to the system controller.
tr ts
P RNG = P r × -------------- + P s × -------------- (EQ. 35) AC Verification
t +t r t +t
s r s
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
The terms tR and tS represent the cadence. The ringing
capability is provided. Depending on the transhybrid balance
interval is tR and the silent interval is tS . The typical cadence
implementation, test coverage is provided by a one or two
ratio tR :tS is 1:2.
step process.
The quiescent power of the device in the ringing mode is
System architectures which cannot disable the transhybrid
defined in Equation 36.
function would require a two step process. The first step
P r ( Q ) = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ (EQ. 36) would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
The total power during the ringing interval is the sum of the the test level times the gain RF /RA of the transhybrid
quiescent power and loading power: amplifier. Since the device would not be terminated,
2 cancellation would not occur. The second step would be to
V RMS
P r = P r ( Q ) + V BH × I AVG – ------------------------------------------ (EQ. 37) program the device to FLB and resend the test tone. The
Z +R REN LOOP
return signal would be much lower in amplitude than the first
For sinusoidal waveforms, the average current, IAVG , is step, indicating the device was active and the internal
defined in Equation 38. termination attenuated the return signal.
V RMS × 2 System architectures which disable the transhybrid function
I AVG =  --- ------------------------------------------
2 (EQ. 38)
 π Z +R would achieve test coverage with a signal step. Once the
REN LOOP
transhybrid function is disable, program the device for FLB
The silent interval power dissipation will be determined by and send the test tone. The return signal level is determined
the quiescent power of the selected operating mode. by the 4-wire to 4-wire gain of the device.

4-13
 HC55185

Tip Open Functionality

The logic control is independent of the operating mode
Overview
decode. Independent logic control provides the most
The tip open mode (110) is intended for compatibility for flexibility and will support all application configurations.
PBX type interfaces. Used during idle line conditions, the
device does not provide transmission. Loop supervision is When changing device operating states, battery switching
provided by either the switch hook detector (E0 = 1) or the should occur simultaneously with or prior to changing the
ground key detector (E0 = 0). The ground key detector will operating mode. In most cases, this will minimize overall
be used in most applications. The device may be operated power dissipation and prevent glitches on the DET output.
from either high or low battery. The only external component required to support the battery
Functionality switch is a diode in series with the VBH supply lead. In the
event that high battery is removed, the diode allows the
During tip open operation, the Tip switch is disabled and the
device to transition to low battery operation.
Ring switch is enabled. The minimum Tip impedance is
30kΩ. The only active path through the device will be the Low Battery Operation
Ring switch. All off hook operating conditions should use the low battery.
In keeping with the MTU characteristics of the device, Ring The prime benefit will be reduced power dissipation. The
will not exceed -56V when operating from the high battery. typical low battery for the device is -24V. However this may
Though MTU does not apply to tip open, safety requirements be increased to support longer loop lengths or high loop
are satisfied. current requirements. Standby conditions may also operate
from the low battery if MTU compliance is not required,
Power Denial further reducing standby power dissipation.

Overview High Battery Operation

The power denial mode (111) will shutdown the entire device Other than ringing, the high battery should be used for
except for the logic interface. Loop supervision is not standby conditions which must provide MTU compliance.
provided. This mode may be used as a sleep mode or to During standby operation the power consumption is typically
shut down in the presence of a persistent thermal alarm. 85mW with -100V battery. If ringing requirements do not
Switching between high and low battery will have no effect require full 100V operation, then a lower battery will result in
during power denial. lower standby power.

Functionality High Voltage Decoupling

During power denial, both the Tip and Ring amplifiers are The 100V rating of the device will require a capacitor of
disabled, representing high impedances. The voltages at higher voltage rating for decoupling. Suggested decoupling
both outputs are near ground. values for all device pins are 0.1µF. Standard surface mount
ceramic capacitors are rated at 100V. For applications driven
Thermal Shutdown at low cost and small size, the decoupling scheme shown
In the event the safe die temperature is exceeded, the ALM below could be implemented.
output will go low and DET will go high and the part will
automatically shut down. When the device cools, ALM will 0.22µ 0.22µ
go high and DET will reflect the loop status. If the thermal
fault persists, ALM will go low again and the part will shut
down. Programming power denial will permanently
shutdown the device and stop the self cooling cycling. VBL VBH
HC5518X
Battery Switching FIGURE 12. ALTERNATE DECOUPLING SCHEME

Overview It is important to place the external diode between the VBH

The integrated battery switch selects between the high pin and the decoupling capacitor. Attaching the decoupling
battery and low battery. The battery switch is controlled capacitor directly to the VBH pin will degrade the reliability of
with the logic input BSEL. When BSEL is a logic high, the the device. Refer to Figure 12 for the proper arrangement.
high battery is selected and when a logic low, the low This applies to both single and stacked and decoupling
battery is selected. All operating modes of the device will arrangements.
operate from high or low battery except forward loop back.
If VBL and VBH are tied together to override the battery
switch function, then the external diode is not needed and
the decoupling may be attached directly to VBH.

4-14
 HC55185

Uncommitted Switch Basic Application Circuit

CPS1
Overview
CPS2
The uncommitted switch is a three terminal device designed D1
CPS3
for flexibility. The independent logic control input, SWC,
allows switch operation regardless of device operating
VCC VBL VBH
mode. The switch is activated by a logic low. The positive CRX
and negative terminals of the device are labeled SW+ and RP1 VRX
U1
SW- respectively. TIP
VRS
HC55185 CRS
Relay Driver RP2
RING VTX
The uncommitted switch may be used as a relay driver by RS CTX
SW+
connecting SW+ to the relay coil and SW- to ground. The -IN
switch is designed to have a maximum on voltage of 0.6V CRT SW-
CFB
with a load current of 45mA. RRT
VFB
RTD
+5V
RSH SWC
RELAY RD BSEL
RIL
ILIM E0

SW+ CDC F0
VCC CDC F1
SWC
SW- CPOL
POL F2

RTL DET
TL ALM
FIGURE 13. EXTERNAL RELAY SWITCHING
AGND BGND

Since the device provides the ringing waveform, the relay

functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external FIGURE 15. HC55185 BASIC APPLICATION CIRCUIT
snubber diode is not required when using the uncommitted
switch as a relay driver. TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST

Test Load COMPONENT VALUE TOL RATING

The switch may be used to connect test loads across Tip U1 - Ringing SLIC HC55185 N/A N/A
and Ring. The test loads can provide external test
RTL 18.7kΩ 1% 0.1W
termination for the device. Proper connection of the
uncommitted switch to Tip and Ring is shown below. RRT 23.7kΩ 1% 0.1W
RSH 49.9kΩ 1% 0.1W
TIP
RIL 71.5kΩ 1% 0.1W
RS 66.5kΩ 1% 0.1W
RING
CRX , CRS , CTX , CRT , CPOL 0.47µF 20% 10V
CDC, CFB 4.7µF 20% 10V
TEST
LOAD CPS1 0.1µF 20% >100V
SW+ CPS2 , CPS3 0.1µF 20% 100V
SWC D1 1N400X type with breakdown > 100V.
SW-
RP1 , RP2
FIGURE 14. TEST LOAD SWITCHING Standard applications will use ≥ 49Ω per side. Protection resistor
values are application dependent and will be determined by
The diode in series with the test load blocks current from protection requirements.
flowing through the uncommitted switch when the polarity of Design Parameters: Ring Trip Threshold = 76mAPEAK , Switch
the Tip and Ring terminals are reversed. In addition to the Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize
reverse active state, the polarity of Tip and Ring are reversed Device Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω
for half of the ringing cycle. With independent logic control protection resistors, impedance across Tip and Ring
terminals = 599Ω. Transient current limit = 95mA.
and the blocking diode, the uncommitted switch may be
continuously connected to the Tip and Ring terminals.

4-15
 HC55185

Pin Descriptions
PLCC SYMBOL DESCRIPTION

1 TIP TIP power amplifier output.

2 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.

3 VBL Low battery supply connection.

4 VBH High battery supply connection for the most negative battery.

5 SW+ Uncommitted switch positive terminal.

6 SW- Uncommitted switch negative terminal.

7 SWC Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and
logic “1” disabling the switch.

8 F2 Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of
operation of the device.

9 F1 Mode control input.

10 F0 Mode control input.

11 E0 Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0)
comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table
shown on page 2).

12 DET Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode.
The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on
page 2).

13 ALM Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature
(approximately 175oC) and the device has been powered down automatically.

14 AGND Analog ground reference. This pin should be externally connected to BGND.

15 BSEL Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.

16 TL Programming pin for the transient current limit feature, set by an external resistor to ground.

17 POL External capacitor on this pin sets the polarity reversal time.

18 VRS Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.

19 VRX Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC.

20 VTX Transmit Output Voltage - Output of impedance matching amplifier, AC couples to CODEC.

21 VFB Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.
22 -IN Impedance matching amplifier summing node.

23 VCC Positive voltage power supply, usually +5V.

24 CDC DC Biasing Filter Capacitor - Connects between this pin and VCC.

25 RTD Ring trip filter network.

26 ILIM Loop Current Limit programming resistor.

27 RD Switch hook detection threshold programming resistor.

28 RING RING power amplifier output.

4-16
 HC55185

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)
0.042 (1.07) N28.45 (JEDEC MS-018AB ISSUE A)
0.048 (1.22) 0.004 (0.10) C 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.056 (1.42)
PIN (1) IDENTIFIER
0.050 (1.27) TP 0.025 (0.64) INCHES MILLIMETERS
R
C 0.045 (1.14)
L SYMBOL MIN MAX MIN MAX NOTES
A 0.165 0.180 4.20 4.57 -
A1 0.090 0.120 2.29 3.04 -
D2/E2
D 0.485 0.495 12.32 12.57 -
C
L D1 0.450 0.456 11.43 11.58 3
E1 E
D2 0.191 0.219 4.86 5.56 4, 5
D2/E2
E 0.485 0.495 12.32 12.57 -
VIEW “A”
E1 0.450 0.456 11.43 11.58 3
E2 0.191 0.219 4.86 5.56 4, 5
0.020 (0.51)
MIN N 28 28 6
D1 A1
D A Rev. 2 11/97

0.020 (0.51) MAX SEATING

-C- PLANE
3 PLCS 0.026 (0.66)
0.032 (0.81) 0.013 (0.33)
0.021 (0.53)

0.025 (0.64)
0.045 (1.14) MIN
MIN
VIEW “A” TYP.

NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com

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Melbourne, FL 32902 100, Rue de la Fusee Taipei, Taiwan
TEL: (321) 724-7000 1130 Brussels, Belgium Republic of China
FAX: (321) 724-7240 TEL: (32) 2.724.2111 TEL: (886) 2 2716 9310
FAX: (32) 2.724.22.05 FAX: (886) 2 2715 3029

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