Opax990 40-V Rail-To-Rail Input/Output, Low Offset Voltage, Low Power Op Amp

OPA990, OPA2990, OPA4990
www.ti.com OPA990,
SBOS933G – FEBRUARY OPA2990,
2019 – REVISED OPA4990
DECEMBER 2020
SBOS933G – FEBRUARY 2019 – REVISED DECEMBER 2020
OPAx990 40-V Rail-to-Rail Input/Output, Low Offset Voltage, Low Power Op Amp
1 Features 3 Description
• Low offset voltage: ±300 µV The OPAx990 family (OPA990, OPA2990, and
• Low offset voltage drift: ±0.6 µV/°C OPA4990) is a family of high voltage (40-V) general
• Low noise: 30 nV/√ Hz at 1 kHz purpose operational amplifiers. These devices offer
• High common-mode rejection: 115 dB excellent DC precision and AC performance, including
rail-to-rail input/output, low offset (±300 µV, typ), and
• Low bias current: ±10 pA
low offset drift (±0.6 µV/°C, typ).
• Rail-to-rail input and output
• MUX-friendly/comparator inputs Unique features such as differential and common-
– Amplifier operates with differential inputs up to mode input voltage range to the supply rail, high
supply rail short-circuit current (±80 mA), high slew rate (4.5 V/
µs), and shutdown make the OPAx990 an extremely
– Amplifier can be used in open-loop or as
flexible, robust, and high-performance op amp for
comparator
high-voltage industrial applications.
• Wide bandwidth: 1.1-MHz GBW
• High slew rate: 4.5 V/µs The OPAx990 family of op amps is available in micro-
• Low quiescent current: 120 µA per amplifier size packages (such as X2QFN, WSON, and
SOT-553), as well as standard packages (such as
• Wide supply: ±1.35 V to ±20 V, 2.7 V to 40 V
SOT-23, SOIC, and TSSOP), and is specified from –
• Robust EMIRR performance: 78 dB at 1.8 GHz 40°C to 125°C.
• Differential and common-mode input voltage range
to supply rail Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
2 Applications SOT-23 (5) 2.90 mm × 1.60 mm
• Multiplexed data-acquisition systems SOT-23 (6) 2.90 mm × 1.60 mm
OPA990
• Test and measurement equipment SC70 (5) 2.00 mm × 1.25 mm
• Motor drive: power stage and control modules SOT-553 (5)(2) 1.60 mm × 1.20 mm
• Power delivery: UPS, server, and merchant SOIC (8) 4.90 mm × 3.90 mm
network power SOT-23 (8) 2.90 mm × 1.60 mm
• ADC driver and reference buffer amplifier
TSSOP (8) 3.00 mm × 4.40 mm
• Programmable logic controllers
OPA2990 VSSOP (8)(2) 3.00 mm × 3.00 mm
• Analog input and output modules
VSSOP (10) 3.00 mm x 3.00 mm
• High-side and low-side current sensing
WSON (8) 2.00 mm × 2.00 mm
• High precision comparator
X2QFN (10) 2.00 mm × 1.50 mm
SOIC (14) 8.65 mm × 3.90 mm
TSSOP (14) 5.00 mm × 4.40 mm
OPA4990
WQFN (16)(2) 3.00 mm × 3.00 mm
X2QFN (14) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) This package is preview only.
Analog Inputs
REF3140 RC Filter OPA375 RC Filter
Bridge Sensor
Reference Driver
OPA990 Gain Network Gain Network
+
MUX509
Thermocouple
REF
+ OPA990 VINP
OPA990 Gain Network + Antialiasing
Filter ADS8860
Gain Network
Current Sensing VINM
Photo
LED Detector
High-Voltage Multiplexed Input High-Voltage Level Translation VCM
Optical Sensor
OPAx990 in a High-Voltage, Multiplexed, Data-Acquisition System
An©IMPORTANT
Copyright NOTICEIncorporated
2020 Texas Instruments at the end of this data sheet addresses availability, warranty, changes, use in safety-critical
Submit Document applications,
Feedback 1
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: OPA990 OPA2990 OPA4990
OPA990, OPA2990, OPA4990
SBOS933G – FEBRUARY 2019 – REVISED DECEMBER 2020 www.ti.com
Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 35
2 Applications..................................................................... 1 8.1 Application Information............................................. 35
3 Description.......................................................................1 8.2 Typical Applications.................................................. 35
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................37
5 Pin Configuration and Functions...................................4 10 Layout...........................................................................37
6 Specifications................................................................ 10 10.1 Layout Guidelines................................................... 37
6.1 Absolute Maximum Ratings ..................................... 10 10.2 Layout Example...................................................... 37
6.2 ESD Ratings ............................................................ 10 11 Device and Documentation Support..........................40
6.3 Recommended Operating Conditions ......................10 11.1 Device Support........................................................40
6.4 Thermal Information for Single Channel .................. 11 11.2 Documentation Support.......................................... 40
6.5 Thermal Information for Dual Channel ..................... 11 11.3 Related Links.......................................................... 40
6.6 Thermal Information for Quad Channel ................... 12 11.4 Receiving Notification of Documentation Updates.. 40
6.7 Electrical Characteristics ..........................................13 11.5 Support Resources................................................. 40
6.8 Typical Characteristics.............................................. 17 11.6 Trademarks............................................................. 40
7 Detailed Description......................................................25 11.7 Electrostatic Discharge Caution.............................. 41
7.1 Overview................................................................... 25 11.8 Glossary.................................................................. 41
7.2 Functional Block Diagram......................................... 25 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................26 Information.................................................................... 41
7.4 Device Functional Modes..........................................33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2020) to Revision G (December 2020) Page
• Updated the numbering format for tables, figures and cross-references throughout the document ..................1
• Removed preview notation from OPA2990 SOT-23 (8) package from Device Information table....................... 1
• Added OPA2990 VSSOP (10) package to Device Information table..................................................................1
• Clarified SHDN notation on OPA990S Pin Functions ........................................................................................ 4
• Removed preview notation from OPA2990 DDF package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview notation from OPA2990S DGS package (VSSOP) in the Pin Configuration and Functions
section ............................................................................................................................................................... 4
• Clarified SHDN notation for OPA2990S in the Pin Functions section ................................................................4
• Clarified SHDN notation for OPA4990S in the Pin Functions section ................................................................4
Changes from Revision E (December 2019) to Revision F (May 2020) Page

• Removed preview notation from OPA2990 X2QFN (10) package from Device Information table .....................1
• Removed preview notation from OPA2990S RUG package (X2QFN) in the Pin Configuration and Functions
section ............................................................................................................................................................... 4
• Changed RUG (X2QFN) in Thermal Information for Dual Channel section....................................................... 4
2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

OPA990, OPA2990, OPA4990
www.ti.com SBOS933G – FEBRUARY 2019 – REVISED DECEMBER 2020
Changes from Revision D (July 2019) to Revision E (December 2019) Page

• Changed the OPA990 and OPA4990 device statuses from Advance Information to Production Data ..............1
• Removed preview notation from OPA990 SOT-23 (5) package from Device Information table......................... 1
• Removed preview notation from OPA990S SOT-23 (6) package from Device Information table....................... 1
• Removed preview notation from OPA990 SC70 (5) package from Device Information table.............................1
• Removed preview notation from OPA4990 SOIC (14) package from Device Information table......................... 1
• Removed preview notation from OPA4990 TSSOP (14) package from Device Information table..................... 1
• Removed preview notation from OPA990 DBV package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview notation from OPA990 DCK package (SC70) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Removed preview notation from OPA4990 D (SOIC) and TSSOP (PW) packages in the Pin Configuration and
Functions section................................................................................................................................................4
• Removed preview notation from OPA990S DBV package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Changes from Revision C (May 2019) to Revision D (July 2019) Page

• Removed preview notation from OPA2990 WSON (8) package from Device Information table........................ 1
• Removed preview notation from OPA2990 DSG package (WSON) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
• Added SHUTDOWN to Electrical Characteristics table.................................................................................... 13
• Added Shutdown section to the Detailed Description section.......................................................................... 33
Changes from Revision B (April 2019) to Revision C (May 2019) Page

• Removed preview notation from OPA2990 TSSOP (8) package from Device Information table....................... 1
• Removed preview notation from OPA2990 PW package (TSSOP) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Changes from Revision A (March 2019) to Revision B (April 2019) Page

• Removed preview notation from OPA2990 SOIC (8) package from Device Information table........................... 1
• Removed preview notation from OPA2990 D package (SOIC) in the Pin Configuration and Functions section..
4
Changes from Revision * (February 2019) to Revision A (March 2019) Page

• Changed the OPA2990 device status from Advance Information to Production Data .......................................1
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

OPA990, OPA2990, OPA4990
5 Pin Configuration and Functions
OUT 1 5 V+ IN+ 1 5 V+
V± 2 V± 2
IN+ 3 4 IN± IN± 3 4 OUT
Not to scale Not to scale
A. DRL package is preview only. OPA990 DCK Package 5-Pin SC70 Top View
OPA990 DBV and DRL Package(1) 5-Pin SOT-23 and
SOT-553 Top View
Table 5-1. Pin Functions: OPA990

PIN
I/O DESCRIPTION
NAME DBV and DRL DCK
IN+ 3 1 I Noninverting input
IN– 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
OUT 1 6 V+
V– 2 5 SHDN
+IN 3 4 –IN
Not to scale
A. DRL package is preview only.
Figure 5-1. OPA990S DBV and DRL Package(1) 6-Pin SOT-23 and SOT-563 Top View
Table 5-2. Pin Functions: OPA990S

PIN
I/O DESCRIPTION
NAME DBV and DRL
IN+ 3 I Noninverting input
IN– 4 I Inverting input
OUT 1 O Output
Shutdown: low = amplifier enabled, high = amplifier disabled. See Shutdown
SHDN 5 I
section for more information.
V+ 6 — Positive (highest) power supply
V– 2 — Negative (lowest) power supply

OPA990, OPA2990, OPA4990
OUT1 1 8 V+
OUT1 1 8 V+
IN1± 2 7 OUT2
IN1± 2 7 OUT2
Thermal
IN1+ 3 6 IN2±
Pad
IN1+ 3 6 IN2±
V± 4 5 IN2+
V± 4 5 IN2+
Not to scale
Not to scale
A. DGK package is preview only.
Figure 5-2. OPA2990 D, DDF, DGK, PW, and TDDF A. Connect thermal pad to V–. See Packages with an Exposed
Packages(1) 8-Pin SOIC, SOT-23-8, TSSOP, and Thermal Pad section for more information.
VSSOP Top View Figure 5-3. OPA2990 DSG Package(1) 8-Pin WSON
With Exposed Thermal Pad Top View

PIN
SOIC, TSSOP, I/O DESCRIPTION
NAME VSSOP, and
WSON
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
OUT1 1 O Output, channel 1
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply

OPA990, OPA2990, OPA4990
IN1+
OUT1 1 10 V+
V– 1 9 IN1–
IN1– 2 9 OUT2
10
IN1+ 3 8 IN2–
SHDN1 2 8 OUT1
V– 4 7 IN2+
SHDN1 5 6 SHDN2
SHDN2 3 7 V+
5
Not to scale
Figure 5-4. OPA2990S DGS Package 10-Pin VSSOP IN2+ 4 6 OUT2

Top View
Not to scale
IN2–
Figure 5-5. OPA2990S RUG Package 10-Pin X2QFN
Top View

PIN
I/O DESCRIPTION
NAME VSSOP X2QFN
IN1+ 3 10 I Noninverting input, channel 1
IN1– 2 9 I Inverting input, channel 1
IN2+ 7 4 I Noninverting input, channel 2
IN2– 8 5 I Inverting input, channel 2
OUT1 1 8 O Output, channel 1
OUT2 9 6 O Output, channel 2
Shutdown, channel 1: low = amplifier enabled, high = amplifier
SHDN1 5 2 I
disabled. See Shutdown section for more information.
Shutdown, channel 2: low = amplifier enabled, high = amplifier
SHDN2 6 3 I
V+ 10 7 — Positive (highest) power supply
V– 4 1 — Negative (lowest) power supply

OPA990, OPA2990, OPA4990
OUT1
OUT4
IN1±
IN4±
OUT1 1 14 OUT4
IN1± 2 13 IN4±
IN1+ 3 12 IN4+
16
15
14
13
V+ 4 11 V± IN1+ 1 12 IN4+
IN2+ 5 10 IN3+ V+ 2 11 V±
Thermal
IN2± 6 9 IN3± IN2+ 3 Pad 10 IN3+
OUT2 7 8 OUT3 IN2± 4 9 IN3±
8
Not to scale
Figure 5-6. OPA4990 D and PW Packages 14-Pin
OUT2
NC
NC
OUT3
SOIC and TSSOP Top View Not to scale
A. Connect thermal pad to V–. See Packages with an Exposed

Thermal Pad section for more information.
B. Package is preview only.
Figure 5-7. OPA4990 RTE Package(1)(2) 16-Pin
WQFN With Exposed Thermal Pad Top View
OUT1
OUT4
IN1± 1 12 IN4±
14
13
IN1+ 2 11 IN4+
V+ 3 10 V±
IN2+ 4 9 IN3+
6
IN2± 5 8 IN3±
OUT2
OUT3
Not to scale
Figure 5-8. OPA4990 RUC Packages 14-Pin X2QFN With Exposed Thermal Pad Top View

PIN
SOIC and I/O DESCRIPTION
NAME WQFN X2QFN
TSSOP
IN1+ 3 1 2 I Noninverting input, channel 1
IN1– 2 16 1 I Inverting input, channel 1

OPA990, OPA2990, OPA4990
Table 5-5. Pin Functions: OPA4990 (continued)

PIN
SOIC and I/O DESCRIPTION
NAME WQFN X2QFN
TSSOP
NC — 6, 7 — — Do not connect
OUT1 1 15 14 O Output, channel 1
V+ 4 2 3 — Positive (highest) power supply
V– 11 11 10 — Negative (lowest) power supply

OPA990, OPA2990, OPA4990
OUT1
OUT4
IN1–
IN4–
16
15
14
13
IN1+ 1 12 IN4+
V+ 2 11 V–
Thermal
IN2+ 3 Pad 10 IN3+
IN2– 4 9 IN3–
8
OUT2
SHDN12
SHDN34
OUT3
Not to scale
A. Connect thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information.
B. Package is preview only.
Figure 5-9. OPA4990S RTE Package(1) 16-Pin WQFN With Exposed Thermal Pad Top View

PIN
I/O DESCRIPTION
NAME WQFN
Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers
SHDN12 6 I
Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers
SHDN34 7 I
VCC+ 2 — Positive (highest) power supply
VCC– 11 — Negative (lowest) power supply

OPA990, OPA2990, OPA4990
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 0 42 V
Common-mode voltage(3) (V–) – 0.5 (V+) + 0.5 V
Signal input pins Differential voltage(3) VS + 0.2 V
Current(3) –10 10 mA
Shutdown pin voltage(4) V– (V–) + 20 V
Output short-circuit(2) Continuous
Operating ambient temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause
excessive heating and eventual destruction. See the Thermal Protection section for more information.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(4) Cannot exceed V+.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage, (V+) – (V–) 2.7 40 V
VI Input voltage range (V–) – 0.2 (V+) + 0.2 V
VIH High level input voltage at shutdown pin (amplifier enabled) (V–) + 1.1 (V–) + 20 V(1) V
VIL Low level input voltage at shutdown pin (amplifier disabled) (V–) (V–) + 0.2 V
TA Specified temperature –40 125 °C
(1) Cannot exceed V+.

OPA990, OPA2990, OPA4990
6.4 Thermal Information for Single Channel

OPA990, OPA990S
DBV DCK DRL(2)
THERMAL METRIC(1) UNIT
(SOT-23) (SC70) (SOT-553)
5 PINS 6 PINS 5 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 192.1 1174.5 204.6 TBD TBD °C/W
RθJC(top) Junction-to-case (top) thermal resistance 113.6 113.4 116.5 TBD TBD °C/W
RθJB Junction-to-board thermal resistance 60.5 55.8 51.8 TBD TBD °C/W
ψJT Junction-to-top characterization parameter 37.2 39.6 24.9 TBD TBD °C/W
Junction-to-board characterization
ψJB 60.3 55.6 51.5 TBD TBD °C/W
parameter
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A TBD TBD °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for OPA990.
6.5 Thermal Information for Dual Channel

OPA2990, OPA2990S
D DDF DGK(2) DGS DSG PW RUG
(SOIC) (SOT-23-8) (VSSOP) (VSSOP) (WSON) (TSSOP) (X2QFN)
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 10 PINS
Junction-to-ambient
RθJA 138.7 150.4 189.3 152.2 81.6 188.4 149.6 °C/W
thermal resistance
Rθ Junction-to-case (top)
78.7 85.6 75.8 67.3 101.6 77.1 58.3 °C/W
JC(top) thermal resistance
Junction-to-board
RθJB 82.2 70.0 111.0 95.5 48.3 119.1 77.7 °C/W
thermal resistance
Junction-to-top
ψJT characterization 27.8 8.1 15.4 67.9 6.0 14.2 1.3 °C/W
parameter
Junction-to-board
ψJB characterization 81.4 69.6 109.3 94.3 48.3 117.4 77.5 °C/W
parameter
Junction-to-case
Rθ
(bottom) thermal N/A N/A N/A N/A 22.8 N/A N/A °C/W
JC(bot)
resistance
report, SPRA953.

OPA990, OPA2990, OPA4990
6.6 Thermal Information for Quad Channel

OPA4990, OPA4990S
D PW RTE(2) RUC
(SOIC) (TSSOP) (WQFN) (WQFN)
14 PINS 14 PINS 16 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 105.2 134.7 53.5 143.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.2 55.0 58.3 46.4 °C/W
RθJB Junction-to-board thermal resistance 61.1 79.0 28.6 81.8 °C/W
ψJT Junction-to-top characterization parameter 21.4 9.2 2.1 1.0 °C/W
Junction-to-board characterization
ψJB 60.7 78.1 28.6 81.5 °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bot) N/A N/A 12.6 N/A °C/W
resistance
report, SPRA953.

OPA990, OPA2990, OPA4990
6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO
UT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
±0.3 ±1.5
VOS Input offset voltage VCM = V– TA = –40°C to mV
±1.75
125°C
TA = –40°C to
dVOS/dT Input offset voltage drift ±0.6 µV/℃
125°C
VCM = V–, VS = 4 V to 40 V ±0.1 ±1.3
Input offset voltage TA = –40°C to
PSRR VCM = V–, VS = 2.7 V to 40 µV/V
versus power supply 125°C ±0.75 ±6.6
V(2)
Channel separation f = 0 Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±5 pA
NOISE
6 µVPP
EN Input voltage noise f = 0.1 Hz to 10 Hz
1 µVRMS
Input voltage noise f = 1 kHz 30

eN nV/√Hz
density f = 10 kHz 28
iN Input current noise f = 1 kHz 2 fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage
VCM (V–) – 0.2 (V+) + 0.2 V
range
VS = 40 V, (V–) – 0.1 V <
VCM < (V+) – 2 V (PMOS 100 115
pair)
VS = 4 V, (V–) – 0.1 V < VCM
75 90
< (V+) – 2 V (PMOS pair)
VS = 2.7 V, (V–) – 0.1 V < dB
Common-mode TA = –40°C to
CMRR VCM < (V+) – 2 V (PMOS 70 90
rejection ratio 125°C
pair)(2)
VS = 2.7 – 40 V, (V+) – 1 V <
VCM < (V+) + 0.1 V (NMOS 80
pair)
(V+) – 2 V < VCM < (V+) – 1 See Offset Voltage (Transition Region) in
V the Typical Characteristics section
INPUT CAPACITANCE
ZID Differential 540 || 3 GΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF

OPA990, OPA2990, OPA4990
6.7 Electrical Characteristics (continued)

UT= VS / 2, unless otherwise noted.
OPEN-LOOP GAIN
VS = 40 V, VCM = VS / 2, 120 145

(V–) + 0.1 V < VO < (V+) – TA = –40°C to
0.1 V 142
125°C
dB
VS = 4 V, VCM = VS / 2, 104 130
AOL Open-loop voltage gain (V–) + 0.1 V < VO < (V+) – TA = –40°C to
0.1 V 125
125°C
VS = 2.7 V, VCM = VS / 2, 101 118 dB

(V–) + 0.1 V < VO < (V+) – TA = –40°C to
0.1 V(2) 117 dB
125°C
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1.1 MHz
SR Slew rate VS = 40 V, G = +1, CL = 20 pF 4.5 V/μs
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL =
4
20 pF
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20
2
pF
tS Settling time µs
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL =
5
20 pF
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL =
3
20 pF
Phase margin G = +1, RL = 10 kΩ, CL = 20 pF 60 °
Overload recovery time VIN × gain > VS 600 ns
Total harmonic
THD+N VS = 40 V, VO = 1 VRMS, G = 1, f = 1 kHz 0.00162%
distortion + noise
OUTPUT
VS = 40 V, RL = no
2
load
VS = 40 V, RL = 10
45 60
kΩ
VS = 40 V, RL = 2
200 300
Voltage output swing Positive and negative kΩ
mV
from rail rail headroom VS = 2.7 V, RL = no
1
load
VS = 2.7 V, RL = 10
5 20
kΩ
VS = 2.7 V, RL = 2
25 50
kΩ
ISC Short-circuit current ±80 mA
See Small-Signal Overshoot vs Capacitive Load
CLOAD Capacitive load drive
in the Typical Characteristics section
Open-loop output
ZO f = 1 MHz, IO = 0 A 575 Ω
impedance

OPA990, OPA2990, OPA4990
6.7 Electrical Characteristics (continued)

UT= VS / 2, unless otherwise noted.
POWER SUPPLY
120 150
OPA2990, OPA4990, IO = 0
A TA = –40°C to
160
Quiescent current per 125°C
IQ µA
amplifier 130 170
OPA990, IO = 0 A TA = –40°C to
175
125°C
Turn-on time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs 40 μs
SHUTDOWN
Quiescent current per VS = 2.7 V to 40 V, all amplifiers disabled, SHDN =
IQSD 20 30 µA
amplifier V– + 2 V
Output impedance VS = 2.7 V to 40 V, amplifier disabled, SHDN = V–
ZSHDN 10 || 12 GΩ || pF
during shutdown +2V
Logic high threshold For valid input high, the SHDN pin voltage should
VIH voltage (amplifier be greater than the maximum threshold but less (V–) + 0.8 (V–) + 1.1 V
disabled) than or equal to (V–) + 20 V
Logic low threshold For valid input low, the SHDN pin voltage should
VIL voltage (amplifier be less than the minimum threshold but greater (V–) + 0.2 (V–) + 0.8 V
enabled) than or equal to V–
tON Amplifier enable time (1) G = +1, VCM = V–, VO = 0.1 × VS / 2 11 µs
tOFF Amplifier disable time (1) VCM = V–, VO = VS / 2 2.5 µs
VS = 2.7 V to 40 V, (V–) + 20 V ≥ SHDN ≥ (V–) +
SHDN pin input bias 500
0.9 V nA
current (per pin)
VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150
(1) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(2) Specified by characterization only.

OPA990, OPA2990, OPA4990
Table 6-1. Table of Graphs

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 6-1
Offset Voltage Drift Distribution Figure 6-2
Offset Voltage vs Temperature Figure 6-3, Figure 6-4
Offset Voltage vs Common-Mode Voltage Figure 6-5, Figure 6-6, Figure 6-7, Figure 6-8
Offset Voltage vs Power Supply Figure 6-9
Open-Loop Gain and Phase vs Frequency Figure 6-10
Closed-Loop Gain and Phase vs Frequency Figure 6-11
Input Bias Current vs Common-Mode Voltage Figure 6-12
Input Bias Current vs Temperature Figure 6-13
Output Voltage Swing vs Output Current Figure 6-14, Figure 6-15, Figure 6-16, Figure 6-17
CMRR and PSRR vs Frequency Figure 6-18
CMRR vs Temperature Figure 6-19
PSRR vs Temperature Figure 6-20
0.1-Hz to 10-Hz Noise Figure 6-21
Input Voltage Noise Spectral Density vs Frequency Figure 6-22
THD+N Ratio vs Frequency Figure 6-23
THD+N vs Output Amplitude Figure 6-24
Quiescent Current vs Supply Voltage Figure 6-25
Quiescent Current vs Temperature Figure 6-26
Open Loop Voltage Gain vs Temperature Figure 6-27
Open Loop Output Impedance vs Frequency Figure 6-28
Output Swing vs Supply Voltage Figure 6-29, Figure 6-30, Figure 6-31, Figure 6-32
Small Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 6-33, Figure 6-34
Phase Margin vs Capacitive Load Figure 6-35
No Phase Reversal Figure 6-36
Positive Overload Recovery Figure 6-37
Negative Overload Recovery Figure 6-38
Small-Signal Step Response (100 mV) Figure 6-39, Figure 6-40
Large-Signal Step Response Figure 6-41, Figure 6-42, Figure 6-43
Short-Circuit Current vs Temperature Figure 6-44
Maximum Output Voltage vs Frequency Figure 6-45
Channel Separation vs Frequency Figure 6-46
EMIRR vs Frequency Figure 6-47

OPA990, OPA2990, OPA4990
6.8 Typical Characteristics

at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
25% 25%
20% 20%
Population (%)
Population (%)
15% 15%
10%
10%
5%
5%
0
0
150
300
450
600
750
900
1050
1200
-1200
-1050
-900
-750
-600
-450
-300
-150
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
2.2
2.4
D001
Offset Voltage (PV) Offset Voltage Drift (PV/qC) D002
Distribution from 15526 amplifiers, TA = 25°C Distribution from 190 amplifiers
Figure 6-1. Offset Voltage Production Distribution Figure 6-2. Offset Voltage Drift Distribution
1000 800
800 600
600
400
Offset Voltage (µV)
400
200 200
0 0
-200 -200
-400
-400
-600
-800 -600
-1000 -800
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) D003
VCM = V+ VCM = V–
Each color represents one sample device. Each color represents one sample device.
Figure 6-3. Offset Voltage vs Temperature Figure 6-4. Offset Voltage vs Temperature
800 800
600 600
400 400
200 200
0 0
-200 -200
-400 -400
-600 -600
-800 -800
-20 -16 -12 -8 -4 0 4 8 12 16 20 16 16.5 17 17.5 18 18.5 19 19.5 20
Common Mode Voltage (V) D005
TA = 25°C TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)

OPA990, OPA2990, OPA4990
6.8 Typical Characteristics (continued)

1000 800
800 600
600 400

400 200
200 0
0 -200
-200 -400
-400 -600
-600 -800
-800 -1000
-1000 -1200
-20 -16 -12 -8 -4 0 4 8 12 16 20 -20 -16 -12 -8 -4 0 4 8 12 16 20
TA = 125°C TA = –40°C
Figure 6-7. Offset Voltage vs Common-Mode Voltage Figure 6-8. Offset Voltage vs Common-Mode Voltage
750 100 150
Gain
600 Phase
80 125
450
300 60 100
Gain (dB)
Phase (q)
150
40 75
0
-150
20 50
-300
-450 0 25
-600
-20 0
-750 100 1k 10k 100k 1M
0 4 8 12 16 20 24 28 32 36 40 44 Frequency (Hz) C002
Supply Voltage (V) D008
CL = 20 pF
VCM = V–
Each color represents one sample device. Figure 6-10. Open-Loop Gain and Phase vs Frequency
Figure 6-9. Offset Voltage vs Power Supply

70 3
G=1 IB
60 2.5
G = -1 IB+
Input Bias and Offset Current (pA)
50 G = 10 2 IOS
G = 100
Closed-Loop Gain (dB)
1.5
40 G = 1000
1
30
0.5
20
0
10
-0.5
0 -1
-10 -1.5
-20 -2
-30 -2.5
100 1k 10k 100k 1M -20 -16 -12 -8 -4 0 4 8 12 16 20
Frequency (Hz) Common Mode Voltage (V) D010
C001
Figure 6-11. Closed-Loop Gain vs Frequency Figure 6-12. Input Bias Current vs Common-Mode Voltage

OPA990, OPA2990, OPA4990

320 V+
IB
280 V+ 1V
IB+
Input Bias and Offset Current (pA)
IOS V+ 2V
240
V+ 3V
Output Voltage (V)

200
V+ 4V
160
V+ 5V
120 V+ 6V
80 V+ 7V
-40°C
40 V+ 8V 25°C
V+ 9V 85°C
0 125°C
V+ 10 V
-40 0 10 20 30 40 50 60 70 80 90 100
-40 -20 0 20 40 60 80 100 120 140 Output Current (mA) D012
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
Figure 6-13. Input Bias Current vs Temperature
V + 10 V 5
-40°C
V +9V 25°C 4.5 -40qC
V +8V 85°C
4
125°C
V +7V
Output Voltage (V)
3.5
Output Voltage (V)
25qC
V +6V 3 125qC
V +5V 2.5
V +4V 85qC
2
V +3V
1.5
V +2V
1
V +1V
0.5
V
0 10 20 30 40 50 60 70 80 90 100 0
Output Current (mA) 0 10 20 30 40 50 60 70 80 90 100
D012
Output Current (mA) D013
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
VS = 5 V
Figure 6-16. Output Voltage Swing vs Output Current (Sourcing)

5 110
PSRR+
4.5 100
PSRR-
4 90 CMRR
PSRR and CMRR (dB)
3.5 80
Output Voltage (V)
70
3
85qC
60
2.5
125qC 50
2
40
1.5
30
1 -40qC 20
25qC
0.5 10
0 0
0 10 20 30 40 50 60 70 80 90 100 100 1k 10k 100k 1M 10M
Output Current (mA) D013 Frequency (Hz) C003
VS = 5 V Figure 6-18. CMRR and PSRR vs Frequency
Figure 6-17. Output Voltage Swing vs Output Current (Sinking)

OPA990, OPA2990, OPA4990

124 145
144
Common-Mode Rejection Ratio (dB)
120
Power Supply Rejection Ratio (dB)

116 143
VS = 40 V
VS = 4 V 142
112
141
108
140
104
139
100
138
96 137
92 136
88 135
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
f = 0 Hz f = 0 Hz
Figure 6-19. CMRR vs Temperature (dB) Figure 6-20. PSRR vs Temperature (dB)
Input Voltage Noise Spectral Density (nV/rHz) 120
110
100
90
Voltage (1uV/div)
80
70
60
50
40
30
20
10
0
Time (1s/Div) 10 100 1k 10k 100k
C015 Frequency (Hz) C017
Figure 6-21. 0.1-Hz to 10-Hz Noise Figure 6-22. Input Voltage Noise Spectral Density vs Frequency
-40 -30
RL = 10 k:
-50 RL = 2 k: -40
RL = 600 :
RL = 128 :
-60 -50
THD+N (dB)
THD+N (dB)
-70 -60
-80 -70
-90 -80
RL = 10 k:
RL = 2 k:
-100 -90 RL = 549 :
RL = 128 :
-110 -100
100 1k 10k 0.001 0.01 0.1 1 10 20
Frequency (Hz) C012
Amplitude (VRMS) C023
BW = 80 kHz, VOUT = 1 VRMS BW = 80 kHz, f = 1 kHz
Figure 6-23. THD+N Ratio vs Frequency Figure 6-24. THD+N vs Output Amplitude

OPA990, OPA2990, OPA4990

130 127.5
125 125
120 122.5
Quiescent current (µA)

Quiescent current (µA)
120
115
117.5
110
115
105
112.5
100
110
95 107.5
90 105
85 102.5
0 4 8 12 16 20 24 28 32 36 40 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) Temperature (°C) D022
D021
VCM = V– Figure 6-26. Quiescent Current vs Temperature
Figure 6-25. Quiescent Current vs Supply Voltage

146 780
144 720
Open Loop Output Impedance (:)
Open Loop Voltage Gain (dB)
142 660
140 600
138 540
136 480
VS = 40 V
134 VS = 4 V 420
132 360
130 300
128 240
126 180
124 120
-40 -20 0 20 40 60 80 100 120 140 100 1k 10k 100k 1M 10M
Frequency (Hz) C013
Figure 6-27. Open-Loop Voltage Gain vs Temperature (dB) Figure 6-28. Open-Loop Output Impedance vs Frequency
Delta Between Supply and Output Voltage (mV)
200 0
180 -20
160 -40
-60
140
-80
120
-100
100
-120
80
-140
60 -160
40 -180
20 -200
0 -220
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
Supply Voltage (V) Supply Voltage (V) D026
D026
RL = 2 kΩ RL = 2 kΩ
Figure 6-29. Output Swing vs Supply Voltage, Positive Swing Figure 6-30. Output Swing vs Supply Voltage, Negative Swing

OPA990, OPA2990, OPA4990


40 0
36 -5
32 -10
28
-15
24
-20
20
-25
16
-30
12
-35
8
-40
4
-45
0
0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40
RL = 10 kΩ
RL = 10 kΩ
Figure 6-32. Output Swing vs Supply Voltage, Negative Swing

Figure 6-31. Output Swing vs Supply Voltage, Positive Swing
33 55
30 50
27 45
24 40
Overshoot (%)
Overshoot (%)
21 35
18 30
15 25
12 20
RISO = 0 :, Positive Overshoot RISO = 0 :, Positive Overshoot
9 RISO = 0 :, Negative Overshoot 15 RISO = 0 :, Negative Overshoot
6 RISO = 50 :, Positive Overshoot 10 RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot RISO = 50 :, Negative Overshoot
3 5
0 40 80 120 160 200 240 280 320 360 0 40 80 120 160 200 240 280 320 360
Cap Load (pF) C007
Cap Load (pF) C008
G = –1, 10-mV output step G = 1, 10-mV output step
Figure 6-33. Small-Signal Overshoot vs Capacitive Load Figure 6-34. Small-Signal Overshoot vs Capacitive Load
64
Input
60 Output
56
52
Amplitude (2V/div)
Phase Margin (q)
48
44
40
36
32
28
24
20
0 100 200 300 400 500 600 700 800 900 1000 Time (20µs/Div)
Cap Load (pF) C009 C016
Figure 6-35. Phase Margin vs Capacitive Load VIN = ±20 V; VS = VOUT = ±17 V
Figure 6-36. No Phase Reversal

OPA990, OPA2990, OPA4990

Voltage (5V/div)
Voltage (5V/div)
Input Input
Output Output
Time (500ns/div) Time (500ns/div)

C018 C018
G = –10 G = –10
Figure 6-37. Positive Overload Recovery Figure 6-38. Negative Overload Recovery
Input
Output
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Time (2Ps/div) Time (1µs/div)

C010 C011
CL = 20 pF, G = 1, 20-mV step response CL = 20 pF, G = –1, 20-mV step response
Figure 6-39. Small-Signal Step Response Figure 6-40. Small-Signal Step Response
Input
Output
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Time (1µs/div) Time (1µs/div)

C005 C005
CL = 20 pF, G = 1 CL = 20 pF, G = 1
Figure 6-41. Large-Signal Step Response (Falling) Figure 6-42. Large-Signal Step Response (Rising)

OPA990, OPA2990, OPA4990

100
Large Signal Step Response (2V/div)
80
60
Short-Circuit Current (mA)

Input
Output 40
20
Sourcing
0 Sinking
-20
-40
-60
-80
-100
Time (2µs/div) -40 -20 0 20 40 60 80 100 120 140
C021
CL = 20 pF, G = –1 Figure 6-44. Short-Circuit Current vs Temperature
Figure 6-43. Large-Signal Step Response

20 -60
VS = 15 V
VS = 2.7 V -70
Maximum Output Swing (V)
Channel Seperation (dB)
15
-80
-90
10
-100
-110
5
-120
-130
0
100 1k 10k 100k 1M 10M
1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz) C020
C014
Figure 6-46. Channel Separation vs Frequency

Figure 6-45. Maximum Output Voltage vs Frequency
100
90
80
EMIRR (dB)
70
60
50
40
30
1M 10M 100M 1G
Frequency (Hz) C004
Figure 6-47. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

OPA990, OPA2990, OPA4990
7 Detailed Description
7.1 Overview
The OPAx990 family (OPA990, OPA2990, and OPA4990) is a family of high voltage (40-V) general purpose
operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±300 µV, typ), and low offset drift (±0.6 µV/°C, typ).
Unique features such as differential and common-mode input voltage range to the supply rail, high short-circuit
current (±80 mA), high slew rate (4.5 V/µs), and shutdown make the OPAx990 an extremely flexible, robust, and
high-performance operational amplifier for high-voltage industrial applications.
7.2 Functional Block Diagram

OPA990, OPA2990, OPA4990
7.3 Feature Description

7.3.1 Input Protection Circuitry
The OPAx990 uses a unique input architecture to eliminate the requirement for input protection diodes but still
provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection
schemes that are activated by fast transient step responses and introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling
time.
V+ V+
VIN+ VIN+
VOUT VOUT
40 V OPAx990 ~0.7 V
VIN VIN
V V
OPAx990 Provides Full 40-V Conventional Input Protection
Differential Input Range Limits Differential Input Range
Figure 7-1. OPAx990 Input Protection Does Not Limit Differential Input Capability
Ron_mux 1
Vn = 10 V RFILT 10 V Sn 1 2
D
10 V ~±9.3 V
CFILT CS
CD
2 VIN±
Vn+1 = ±10 V RFILT ±10 V Sn+1 Ron_mux
~0.7 V
CFILT CS Idiode_transient VOUT
VIN+
±10 V
Input Low-Pass Filter Simplified Mux Model Buffer Amplifier
Figure 7-2. Back-to-Back Diodes Create Settling Issues
The OPAx990 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications using a patented input protection architecture that does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The OPA990 tolerates a maximum differential swing (voltage between inverting and non-inverting
pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in applications with fast-
ramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision
Operational Amplifiers for more information.
7.3.2 EMI Rejection
The OPAx990 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx990 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-3 shows the results of this testing on the OPAx990. Table 7-1 shows the EMIRR IN+ values for the OPAx990 at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

OPA990, OPA2990, OPA4990
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
100
90
80
EMIRR (dB)
70
60
50
40
30
1M 10M 100M 1G
Frequency (Hz) C004
Figure 7-3. EMIRR Testing
Table 7-1. OPA990 EMIRR IN+ For Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
400 MHz 59.5 dB
applications
Global system for mobile communications (GSM) applications, radio communication, navigation,
900 MHz 68.9 dB
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB
802.11b, 802.11g, 802.11n, Bluetooth®,
mobile personal communications, industrial, scientific and
2.4 GHz 78.0 dB
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
5 GHz 87.6 dB
operation, C-band (4 GHz to 8 GHz)

OPA990, OPA2990, OPA4990
7.3.3 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx990 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx990 has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and turning
off the op amp output drive for temperatures above 170°C. Figure 7-4 shows an application example for the
OPA990 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations indicate
that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual device,
however, turns off the output drive to recover towards a safe junction temperature. Figure 7-4 shows how the
circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3
V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If
the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
VOUT
3V
30 V TA = 65°C
PD = 0.81W
JA = 138.7°C/W 0V
TJ = 138.7°C/W × 0.81W + 65°C
TJ = 177.3°C (expected)
OPA990
Temperature 170ºC
IOUT = 30 mA +
RL 3V
+ VIN 100 Ÿ ±
± 3V
Figure 7-4. Thermal Protection
7.3.4 Capacitive Load and Stability

The OPAx990 features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
55 33
50 30
45 27
40 24
Overshoot (%)
Overshoot (%)
35 21
30 18
25 15
20 12
RISO = 0 :, Positive Overshoot RISO = 0 :, Positive Overshoot
15 RISO = 0 :, Negative Overshoot 9 RISO = 0 :, Negative Overshoot
10 RISO = 50 :, Positive Overshoot 6 RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot RISO = 50 :, Negative Overshoot
5 3
0 40 80 120 160 200 240 280 320 360 0 40 80 120 160 200 240 280 320 360
Cap Load (pF) C008
Cap Load (pF) C007
Figure 7-5. Small-Signal Overshoot vs Capacitive Figure 7-6. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = 1) Load (10-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the

OPA990, OPA2990, OPA4990
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the OPAx990 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
+ Cload
Vin -Vs
±
Figure 7-7. Extending Capacitive Load Drive With the OPA990

OPA990, OPA2990, OPA4990
7.3.5 Common-Mode Voltage Range

The OPAx990 is a 40-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 7-8. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region,
typically (V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with
process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance
may be degraded compared to operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
IN-
PMOS
PMOS
NMOS
IN+
NMOS
V-
Figure 7-8. Rail-to-Rail Input Stage
7.3.6 Phase Reversal Protection

The OPAx990 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx990 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-9. For more information on phase reversal, see Op
Amps With Complementary-Pair Input Stages application note.
Input
Output
Amplitude (2V/div)
Time (20µs/Div)
C016
Figure 7-9. No Phase Reversal

OPA990, OPA2990, OPA4990
7.3.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-10 shows an illustration of the ESD circuits contained in the OPAx990 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+
±
+VS
VDD
OPAx990
R1 100 Ÿ
IN±
±
RS IN+ 100 Ÿ
+
Power-Supply RL
ID ESD Cell
+
VIN
±
VSS
+
±
±VS
TVS
Figure 7-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

OPA990, OPA2990, OPA4990
7.3.8 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx990 is approximately 600 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00002% 0.00312% 0.13185% 2.145% 13.59% 34.13% 34.13% 13.59% 2.145% 0.13185% 0.00312% 0.00002%
1 1 1 1 1 1 1 1 1 1 1 1
-61 -51 -41 -31 -21 -1 +1 +21 +31 +41 +51 +61
Figure 7-11. Ideal Gaussian Distribution
Figure 7-11 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or
sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ–σ to µ+σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for OPAx990,
the typical input voltage offset is 300 µV, so 68.2% of all OPAx990 devices are expected to have an offset from –

OPA990, OPA2990, OPA4990
300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the OPAx990 family has a maximum offset voltage of 1.5
mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI
assures that any unit with larger offset than 1.5 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6σ
value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option
as a wide guardband to design a system around. In this case, the OPAx990 family does not have a maximum or
minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.6 µV/°C in the Electrical
Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When
designing for worst-case system conditions, this value can be used to estimate the worst possible offset across
temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.10 Packages With an Exposed Thermal Pad
The OPAx990 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature
an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.3.11 Shutdown
The OPAx990S devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V. The
shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The typical
enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a high-
impedance state. This architecture allows the OPAx990S family to operate as a gated amplifier, multiplexer, or
programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the OPAx990S without a load, the resulting turnoff time significantly
increases.
7.4 Device Functional Modes
The OPAx990 has a single functional mode and is operational when the power-supply voltage is greater than or
equal to 2.7 V (±1.35 V). The maximum power supply voltage for the OPAx990 is 40 V (±20 V).

OPA990, OPA2990, OPA4990
The OPAx990S devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Shutdown section for more information.

OPA990, OPA2990, OPA4990
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The OPAx990 family offers excellent DC precision and AC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz
bandwidth and high output drive. These features make the OPAx990 a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 High Voltage Buffered Multiplexer
The OPAx990S shutdown devices can be configured to create a high voltage, buffered multiplexer. Outputs can
be connected together on a common bus and the shutdown pins can be used to select the desired channel to
pass through. Since the amplifier circuitry has been designed such that disable transitions occur significantly
faster than enable transitions, the amplifier naturally exhibits a "break before make" switch topology. Amplifier
outputs enter a high impedance state when placed in shutdown, so there is no risk of bus contention when
connecting multiple channel outputs together. Additionally, because outputs are isolated from inputs, there is no
concern about the impedance at the input of each channel interacting undesirably with the impedance at the
output, like an amplifier gain stage or ADC driver circuit. Also, because this topology uses amplifiers instead of
MOSFET switches, other common issues with multiplexers such as charge injection or signal error due to RON
effects are eliminated.
Figure 8-1 shows an example topology for a basic 2:1 multiplexer. When SEL is low, channel 1 is selected and
active; when SEL is high, channel 2 is selected and active. For more information on how to use the OPAx990S
shutdown function, see the shutdown section in the Electrical Characteristics table.
±
Channel 1
Channel 1
+
Input
SEL Output
Channel 2
Input
+
Channel 2
Figure 8-1. High Voltage Buffered Multiplexer
8.2.2 Slew Rate Limit for Input Protection

In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and
down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx990 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems. Figure 8-2 shows the OPA990 in a slew-rate limit design.

OPA990, OPA2990, OPA4990
Op Amp Gain Stage Slew Rate Limiter

C1 R1
470 nF 1.69 kŸ
VEE
VEE
R2
1.6 MŸ
OPAx990
VIN
+
V+ OPAx990 VOUT
V+
VCC RL
VCC 10 kŸ
Figure 8-2. Slew Rate Limiter Uses One Op Amp

OPA990, OPA2990, OPA4990
9 Power Supply Recommendations

The OPAx990 is specified for operation from 2.7 V to 40 V (±1.35 V to ±20 V); many specifications apply from –
40°C to 125°C or with specific supply voltages and test conditions. Parameters that can exhibit significant
variance with regard to operating voltage or temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum
Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN +
RG VOUT
RF
Figure 10-1. Schematic Representation

OPA990, OPA2990, OPA4990
Place components close
Run the input traces to device and to each VS+
as far away from other to reduce parasitic
the supply lines errors
as possible RF
NC NC
Use a low-ESR,
RG
ceramic bypass
GND ±IN V+ capacitor
VIN +IN OUTPUT
V± NC GND
VS± GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration

INPUT
V+
GND GND
OUT
V-
GND
Figure 10-3. Example Layout for SC70 (DCK) Package

OPA990, OPA2990, OPA4990
OUTPUT A
GND GND GND
V+
INPUT A
OUTPUT B
INPUT B
V-
GND GND GND
Figure 10-4. Example Layout for VSSOP-8 (DGK) Package

OUT A
GND GND GND

V+
- +
OUT B
+ -
+IN A
GND GND
+IN B
V-
GND
Figure 10-5. Example Layout for WSON-8 (DSG) Package

OPA990, OPA2990, OPA4990
11 Device and Documentation Support

11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support

11.2.1 Related Documentation
Texas Instruments, Op Amps With Complementary-Pair Input Stages application note
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
OPA990 Click here Click here Click here Click here Click here
11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.

OPA990, OPA2990, OPA4990
11.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 16-Apr-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
OPA2990IDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O90F
OPA2990IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OP2990
OPA2990IDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O29G
OPA2990IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O2990P
OPA2990SIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OP29
OPA2990SIRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 H9F
OPA2990TIDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O90F
OPA4990IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4990D
OPA4990IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 OPA49PW
OPA4990IRUCR ACTIVE QFN RUC 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 FMF
OPA990IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 O90V
OPA990IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1FL
OPA990SIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O90S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 16-Apr-2021
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2990IDDFR SOT- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
OPA2990IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2990IDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
OPA2990IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
OPA2990SIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2990SIRUGR X2QFN RUG 10 3000 178.0 8.4 1.75 2.25 0.56 4.0 8.0 Q1
OPA2990TIDDFR SOT- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q2
23-THIN
OPA4990IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4990IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
OPA4990IRUCR QFN RUC 14 3000 180.0 9.5 2.16 2.16 0.5 4.0 8.0 Q2
OPA990IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA990IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
OPA990SIDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2021
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2990IDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
OPA2990IDR SOIC D 8 2500 853.0 449.0 35.0
OPA2990IDSGR WSON DSG 8 3000 210.0 185.0 35.0
OPA2990IPWR TSSOP PW 8 2000 853.0 449.0 35.0
OPA2990SIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0
OPA2990SIRUGR X2QFN RUG 10 3000 205.0 200.0 33.0
OPA2990TIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
OPA4990IDR SOIC D 14 2500 853.0 449.0 35.0
OPA4990IPWR TSSOP PW 14 2000 366.0 364.0 50.0
OPA4990IRUCR QFN RUC 14 3000 205.0 200.0 30.0
OPA990IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
OPA990IDCKR SC70 DCK 5 3000 190.0 190.0 30.0
OPA990SIDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A SCALE 4.000
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/E 09/2019
NOTES:
per ASME Y14.5M.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)

www.ti.com
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)

SCALE:15X
4214839/E 09/2019
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
C
5.05
TYP SEATING PLANE
4.75
A PIN 1 ID 0.1 C
AREA
8X 0.5
10
1
3.1
2.9 2X
NOTE 3 2
5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4
0.23
TYP
SEE DETAIL A 0.13
0.25
GAGE PLANE
0.7 0.15
0 -8 0.05
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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DGS0010A VSSOP - 1.1 mm max height
10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10
SYMM
8X (0.5) 5 6
(4.4)

SCALE:10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

DEFINED DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)

www.ti.com
DGS0010A VSSOP - 1.1 mm max height
10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10
SYMM
8X (0.5)
5 6
(4.4)

SCALE:10X
4221984/A 05/2015
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)

www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
www.ti.com
GENERIC PACKAGE VIEW
DSG 8 WSON - 0.8 mm max height
2 x 2, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1 B
A
1.9
PIN 1 INDEX AREA

2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE

TYPICAL
0.8 MAX C
SEATING PLANE
0.05
0.08 C
0.00
EXPOSED
THERMAL PAD 0.9 0.1 (0.2) TYP
4 5
6X 0.5
2X
9
1.5 1.6 0.1
8
1
0.32
8X
PIN 1 ID 0.4 0.18
8X
0.2 0.1 C A B
0.05 C
4218900/D 04/2020
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
DSG0008A WSON - 0.8 mm max height
(0.9) ( 0.2) VIA

8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM 9
(1.6)
6X (0.5)
5
4
(R0.05) TYP SYMM
(1.9)

SCALE:20X
0.07 MAX 0.07 MIN

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
DSG0008A WSON - 0.8 mm max height
8X (0.5) SYMM METAL

1
8
8X (0.25)
(0.45)
SYMM
9
6X (0.5) (0.7)
5
4
(R0.05) TYP (0.9)
(1.9)

EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
per ASME Y14.5M.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
PW0008A TSSOP - 1.2 mm max height
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)

SCALE:10X

METAL OPENING
OPENING SOLDER MASK
0.05 MAX 0.05 MIN


DEFINED DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)

www.ti.com
PW0008A TSSOP - 1.2 mm max height
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)

SCALE:10X
4221848/A 02/2015
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
RUC0014A X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
2.1 A
B 1.9
PIN 1 INDEX AREA 2.1

1.9
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 0.4 (0.15) TYP

6 7
8X 0.4
5
8
SYMM
1.6
12
1
14 13 14X 0.25
0.15
PIN 1 ID SYMM
(45oX0.1) 14X 0.5 0.1 C A B
0.3
0.05 C
4220584/A 05/2019
NOTES:
per ASME Y14.5M.
www.ti.com
SYMM
14X (0.6)
14X (0.2)
8X (0.4) SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)

EXPOSED METAL SHOWN
SCALE: 23X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND SOLDER MASK
METAL
OPENING
EXPOSED METAL SOLDER MASK EXPOSED METAL METAL UNDER

OPENING SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220584/A 05/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
SYMM
14X (0.6)
14X (0.2)
8X (0.4) SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)

BASED ON 0.100mm THICK STENCIL
SCALE: 23X
4220584/A 05/2019
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DDF0008A SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95 SEATING PLANE
TYP
2.65
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
2.95
2.85 2X
NOTE 3 1.95
4
5
0.4
8X
0.2
1.65 0.1 C A B
B 1.1 MAX
1.55
0.20
TYP
0.08
SEE DETAIL A
0.25
GAGE PLANE
0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
per ASME Y14.5M.
www.ti.com
DDF0008A SOT-23 - 1.1 mm max height
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP (2.6)

SCALE:15X

METAL OPENING
OPENING SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)

www.ti.com
DDF0008A SOT-23 - 1.1 mm max height
8X (1.05) SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)

SCALE:15X
4222047/B 11/2015
NOTES: (continued)
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Opax990 40-V Rail-To-Rail Input/Output, Low Offset Voltage, Low Power Op Amp

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Opax990 40-V Rail-To-Rail Input/Output, Low Offset Voltage, Low Power Op Amp

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OPA990, OPA2990, OPA4990

(1) For all available packages, see the orderable addendum at

REF3140 RC Filter OPA375 RC Filter

Current Sensing VINM

OPAx990 in a High-Voltage, Multiplexed, Data-Acquisition System

Changes from Revision E (December 2019) to Revision F (May 2020) Page

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Product Folder Links: OPA990 OPA2990 OPA4990

Changes from Revision D (July 2019) to Revision E (December 2019) Page

Changes from Revision C (May 2019) to Revision D (July 2019) Page

Changes from Revision B (April 2019) to Revision C (May 2019) Page

Changes from Revision A (March 2019) to Revision B (April 2019) Page

Changes from Revision * (February 2019) to Revision A (March 2019) Page

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

5 Pin Configuration and Functions

IN+ 3 4 IN± IN± 3 4 OUT

Not to scale Not to scale

Table 5-1. Pin Functions: OPA990

Table 5-2. Pin Functions: OPA990S

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Product Folder Links: OPA990 OPA2990 OPA4990

Table 5-3. Pin Functions: OPA2990

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5

Figure 5-4. OPA2990S DGS Package 10-Pin VSSOP IN2+ 4 6 OUT2

Table 5-4. Pin Functions: OPA2990S

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Product Folder Links: OPA990 OPA2990 OPA4990

OUT2 7 8 OUT3 IN2± 4 9 IN3±

Figure 5-6. OPA4990 D and PW Packages 14-Pin

A. Connect thermal pad to V–. See Packages with an Exposed

Table 5-5. Pin Functions: OPA4990

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7

Table 5-5. Pin Functions: OPA4990 (continued)

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Product Folder Links: OPA990 OPA2990 OPA4990

Table 5-6. Pin Functions: OPA4990S

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9

6.2 ESD Ratings

6.3 Recommended Operating Conditions

(1) Cannot exceed V+.

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6.4 Thermal Information for Single Channel

6.5 Thermal Information for Dual Channel

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11

6.6 Thermal Information for Quad Channel

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Product Folder Links: OPA990 OPA2990 OPA4990

6.7 Electrical Characteristics

Input voltage noise f = 1 kHz 30

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13

6.7 Electrical Characteristics (continued)

VS = 40 V, VCM = VS / 2, 120 145

VS = 2.7 V, VCM = VS / 2, 101 118 dB

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Product Folder Links: OPA990 OPA2990 OPA4990

6.7 Electrical Characteristics (continued)

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Table 6-1. Table of Graphs