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    Module 2 - Part6

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    Ahmad Raza
    The module is the basic building block in Verilog. Modules can be interconnected to describe digital systems and contain ports for interconnection. There are three models for writing module bodies - data flow, structural, and behavioral. The structural model describes logic using gates and wires. Keywords like and, or, not declare gates. The behavioral model uses initial and always blocks, with initial executing once and always executing continuously.

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    © All Rights Reserved
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    Module 2 - Part6

    Uploaded by

    Ahmad Raza
    43 views5 pages
    The module is the basic building block in Verilog. Modules can be interconnected to describe digital systems and contain ports for interconnection. There are three models for writing module bodies - data flow, structural, and behavioral. The structural model describes logic using gates and wires. Keywords like and, or, not declare gates. The behavioral model uses initial and always blocks, with initial executing once and always executing continuously.

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    Module 2_Part6

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    The module is the basic building block in Verilog. Modules can be interconnected to describe digital systems and contain ports for interconnection. There are three models for writing module bodies - data flow, structural, and behavioral. The structural model describes logic using gates and wires. Keywords like and, or, not declare gates. The behavioral model uses initial and always blocks, with initial executing once and always executing continuously.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    43 views5 pages

    Module 2 - Part6

    Uploaded by

    Ahmad Raza
    The module is the basic building block in Verilog. Modules can be interconnected to describe digital systems and contain ports for interconnection. There are three models for writing module bodies - data flow, structural, and behavioral. The structural model describes logic using gates and wires. Keywords like and, or, not declare gates. The behavioral model uses initial and always blocks, with initial executing once and always executing continuously.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    Digital Electronics

    MODULE 2
    Part 6 Introduction to HDL

    2.8 Introduction to HDL

    • HDL is computer Language used to describe hardware


    Advantages of HDL:
    • Describes large complex hardware in a convenient manner, in a smaller space.
    • Use Software tool to detect functional errors, if any errors, correct the errors, this is process is
    called Simulation.
    • Get hardware implementation details, this is called synthesis
    HDLs
    1. Verilog HDL
    2. VHDL (very high speed integrated circuit HDL)
    Verilog HDL:
    • Verilog HDL is more popular
    • Ii was introduced in 1980, as a simulation tool by Gateway Design Automation.
    Describing Input/ Output:
    • Any digital circuit, there are set of inputs and set of outputs.
    • Inputs and outputs are called as ports.
    Structure of Verilog HDL:

    Module: it is a keyword used to describe module name and input output port list
    Input : keyword used to declare the input ports
    Output : keyword used to declare output ports
    Endmodule: keyword to end the module, semicolon is not used for endmodule
    //  single line comments
    /* */  multi-line comments
    Writing Module Body:
    • Module body describes the logic of the circuit
    • There are three different models to write the module body
    1. Structural Model
    2. Data flow Model
    3. Behavioral Model
    Keywords used to declare gates:
    And, or, not, nand, nor, xor, xnor
    Syntax for 2 input OR gate: or(output, input1, input2)
    Syntax for Not gate: not(output, input)

    Prepared By: BHASKAR S VBE, M.Tech, CSI, LMISTE ,IETE


    Digital Electronics

    • The module is the basic building block in Verilog


    – Modules can be interconnected to describe the structure of your digital system
    – Modules start with keyword module and end with keyword endmodule
    – Modules have ports for interconnection with other modules

    Module NAME <port


    list>
    •
    •
    •
    endmodule
     Keywords used to declare gates:
    and
    or
    not
    nand
    nor
    xor
    xnor

    Operators ~ bit-wise NOT


    {} concatenation & bit-wise AND
    + - * / arithmetic | bit-wise OR
    % modulus ^ bit-wise XOR
    > >= < <=relational ^~ ~^ bit-wise XNOR
    ! logical NOT & reduction AND
    && logical AND | reduction OR
    || logical OR ~& reduction NAND
    == logical equality ~| reduction NOR
    != logical inequality ^ reduction XOR
    ?: conditional ~^ ^~ reduction XNOR
    << shift left
    >> shift right

    Prepared By: BHASKAR S VBE, M.Tech, CSI, LMISTE ,IETE


    Digital Electronics

    Writing Module Body:

    Module body describes the logic of the circuit


    There are three different models to write the module body
    1. Data flow Model
    2. Structural Model
    3. Behavioral Model

    1. Data flow Model

    2. Structural Model

    3. Behavioral Model

    Prepared By: BHASKAR S VBE, M.Tech, CSI, LMISTE ,IETE


    Digital Electronics

    Behavior: Initial and Always


    Initial blocks execute once
    at t = 0
    Always blocks execute continuously
    at t = 0 and repeatedly thereafter

    Behavior: Procedural assignments

    Programs:

    Write Verilog structural code for the figure shown below


    figure_a
    module fig_a(A,B,C,D,Y);
    input A, B, C, D;
    output Y;
    wire and_op1, and_op2; // internal connections
    and g1(and_op1, A, B); // g1 is upper AND gate
    and g2 (and_op2, C, D); // g2 is lower AND gate
    or g3(Y, and_op1, and_op2); // g3 is OR gate
    endmodule
    Write Verilog structural code for the following circuit

    Prepared By: BHASKAR S VBE, M.Tech, CSI, LMISTE ,IETE


    Digital Electronics

    module testckt(a,b,c,x,y);
    input a,b,c;
    output x,y;
    wire or_op1, or_op2; // internal connections
    or g1 (or_op1, a,b); // g1 is upper OR gate
    or g2 (or_op2, b,c); // g2 is lower OR gate
    nor g3(x, c, or_op1); // g3 is NOR gate
    nand g4 (y, or_op1, or_op2); // g4 is NAND gate
    endmodule

    Prepared By: BHASKAR S VBE, M.Tech, CSI, LMISTE ,IETE

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