VLSI Presentation1
VLSI Presentation1
VLSI Presentation1
BASED ON APPLICATION
BASED ON FABRICATION TECHNIQUES
BASED ON TECHNOLOGY
BASED ON DEVICE COUNT
BASED ON APPLICATION
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• •
• •
endmodule endmodule
Operators
• Logical operators map into primitive
logic gates addr = ~data << 2
• Arithmetic operators map into
adders, subtractors, …
– Unsigned 2s complement data3 addr5
– Model carry: target is one-bit data2 addr4
wider that source
– Watch out for *, %, and / data1 addr3
• Relational operators generate data0 addr2
comparators
addr1
• Shifts by constant amount are just
wire connections
– No logic invoved addr0
• Variable shift amounts a whole
different story --- shifter
• Conditional expression generates
logic or MUX
9/20/07 EECS 150, Fa07, Lec 08-timing-synth 46
Operators
Arithmetic Operators +, -, *, /, %
Relational Operators <, <=, >, >=
Equality Operators ==, !=, ===, !==
Logical Operators !, &&, ||
Bit-Wise Operators ~, &, |, ^, ~^
Unary Reduction &, ~&, |, ~|, ^, ~^
Shift Operators >>, <<
Conditional Operators ?:
Concatenations {}
Operators ~ bit-wise NOT
{} concatenation
+ - * / & bit-wise AND
arithmetic | bit-wise OR
% modulus ^ bit-wise XOR
^~ ~^ bit-wise XNOR
> >= < <=
& reduction AND
relational
| reduction OR
! logical NOT ~& reduction NAND
&& logical AND ~| reduction NOR
|| logical OR ^ reduction XOR
== logical equality ~^ ^~ reduction XNOR
!= logical inequality << shift left
?: conditional >> shift right
Brief Comparison Between
VHDL and Verilog
Introduction
There are now two industries standard hardware description languages,
1. Capability
Hardware structure can be modeled equally effectively in both VHDL and
Verilog.
When modelling abstract hardware, the capability of VHDL can sometimes
only be achived in Verilog when using the PLI.
Verilog.
Is still rooted its native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the
original nature of the language.
As a result, care must be taken with both the compilation order of multiple files.
Simulation result can change by simply changing the order of compilation.
3.Data types
VHDL.
A multitude of Language or user defined data types can be used.
This may mean dedicated conversion functions are needed to convert objects
from one type to another.
The choice of which data types to use should be considered wisely, especially
enumerated (abstract) data types.
This will make models easier to write, clearer to read and avoid
unnecessary conversion function that can clutter the code.
Function and procedures used within a model must be defined in the module.
VHDL may seem less intuitive(easy to use and understand) at first for two
primary reasons.
First, it is very strongly typed; a feature that makes it robust and
powerful for the advanced user after a longer learning phase.
Second, there are many ways to model the same circuit. Specially
those with large hierarchical structures.
6.High level construction
VHDL. There are more constructs and features for high-level modelling in VHDL
than there is in Verilog. Abstract data types can be used along with the following
statements:
Package statements for model reuse.
Configure statement for replication structure
Generate statements for generic models that can be individually
characterized, for example, bit width
All these language statements are useful in synthesizable models.
Verilog.
Except for being able to parameterise models by overloading parameter constants,
there is no equivalent to the high-level VHDL modelling statements in Verilog.
7.Language Extension
The use of extension will make a model non standard and most likely not portable
across other design tools. However they are necessary in order to achieve the
desired results.
9.Structural replication
VHDL.
The generate statement replicates a number of instances of the same design-unit
or some sub part of a design, and connects it appropriately.
Verilog.
There is no equivalent to the generate statement in Verilog
Chapter 3. Digital System Design
• Many engineers who want to learn this
language, very often ask this question, how
much time will it take to learn Verilog?
Well my answer to them is
Simulation Synthesis
Bottom-up
or
Top-down methodology.
Bottom-Up Design
– The traditional method of electronic design is bottom-up.
Each design is performed at the gate-level using the
standard gates (refer to the Digital Section for more
details). With the increasing complexity of new designs
this approach is nearly impossible to maintain. New
systems consist of ASIC or microprocessors with a
complexity of thousands of transistors. These traditional
bottom-up designs have to give way to new structural,
hierarchical design methods. Without these new practices it
would be impossible to handle the new complexity.
Top-Down Design
– The desired design-style of all designers is the top-
down one. A real top-down design allows early
testing, easy change of different technologies, a
structured system design and offers many other
advantages. But it is very difficult to follow a pure
top-down design. Due to this fact most designs
are a mix of both methods, implementing some
key elements of both design styles.
Verilog level of Abstraction
• Verilog supported levels of abstraction
– Behavioral (algorithmic) level
• Describe the algorithm used
• Very similar to C programming
– Dataflow level
• Describe how data flows between registers and is processed
– Gate level
• Interconnect logic gates
– Switch level
• Interconnect transistors (MOS transistors)
• Register-Transfer Level (RTL)
– Generally known as a combination of behavioral+dataflow that is
synthesizable by EDA tools
endmodule
• Behavioral
– Program describes input/output behavior of circuit
– Many structural implementations could have same behavior
– E.g., different implementations of one Boolean function
endmodule // mux2
in1 w1
s0 out
select
in0 w0
Sensitivity list
• Vectors of bits
– A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]
– Treated as an unsigned integer value
• e.g. , A < 0 ??
– Concatenating bits/vectors into a vector
• e.g., sign extend
• B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
• B[7:0] = {3{A[3]}, A[3:0]};
– Style: Use a[7:0] = b[7:0] + c;
Not: a = b + c; // need to look at declaration
• reg
– Variable that saves a value as part of a behavioral description
– Usually corresponds to a wire in the circuit
– Is NOT necessarily a register in the circuit
• usage:
– Don’t confuse reg assignments with the combinational continuous assign
statement! (more soon)
– Reg should only be used with always blocks (sequential logic, to be
presented …)