Kick Start

Verilog Basics
and
HDL modelling
Introduction
-Very Large Scale Integration (VLSI) is a Technique
where many circuit components and the wiring that
connects them are manufactured simultaneously into a
compact, reliable and inexpensive chip.
-VLSI circuits are everywhere ... your computer, your
car, your brand new state-of-the-art digital camera, the
cell-phones, etc.
VLSI Design Flow
Basic Verilog Concepts Gate level
modeling
Introduction to
Verilog
● Standardized as IEEE 1364.
●
Hardware description language (HDL) used to
model electronic systems
●
Commonly used in the design and verification
of digital circuits
WHY?
● Why use an HDL
-> Describe complex Designs
-> Design Explorations and Simulation
● -> An input to SynthesisTools

Verilog Vs VHDL
●
-> Verilog is simpler to use and is similar to C
-> Mostly used in the Industry while VHDL is mostly used
in Educational and Research institutions
Modeling in Verilog
● A Module is the basic building block in Verilog
●
Modules can be interconnected to form a Digital
System
●
It is like a function in C
Top: Module - 1

Module - 2 Module - 3

Module - 4
Module Syntax
MUST add the
module <Module Name> <(<port list>)>;
semicolon
.
.
. Write Module Name Here Like:
. Shift_Register, Encoder_8_3,
. etc List of all input and output Pins
that are needed to be connected
. Like: a, b, c, clk, rst, y, op, etc
.
IMPORTANT: Do NOT
endmodule
... add Semicolon Here
Port Declaration
● There are three types of ports:

input Input port

output Output port
inout Bi-directional port
Port Syntax
module And_gate (A, B, Y);
input A, B;
output Y;
.
.
.
.
.
.
...
endmodule
Data
Types
●Nets
-> Physical connection between Devices
-> Reflect logic value of the driving device
-> Cannot store logic value
-> eg: wire, tri, wand, wor etc.....only 'wire' net is used
●

Registers
-> Used when data storage is required
-> Retains previous state value till changed
-> Does not necessarily imply register or flip-flop or latch, can also
imply a wire
-> Denoted by 'reg'
Integer, Real and
Time Data types
Integer:
● It is a general purpose register used for manipulating quantities.
●
Default width is the host-machine word size, which will be atleast
●

●
32-bits Can be used to store signed values
● It is not bit addressable
It can be synthesised
Real: Time:
●
●
Real number constants can Time register datatype is used to
be declared in this data type store simulation time.
●
●
Values can be specified in either Size of time register will be >= 64- bits
● decimal or scientific notation ● System function $time can be
● Cannot have range invoked to get current simulation
●
declaration It is not time It is not synthesisable
synthesisable
Variable Declaration
● Declaring a wire
wire <[<bit range>]> <net_name>;
Default width = 1
● Declaring a Register
reg <[<bit range>]> <reg_name>;
Default width = 1
● Declaring Memory
reg [<bit range>] <reg_name> [<start_addr>:<end_addr>];
Examples
reg r0; // 1 – bit register r0

wire w1, w2; // 1 – bit wires w1 & w2

wire [7:0] a, b; // 8 – bit wires a & b

reg [31:0] counter; // 32 – bit register counter

reg [7:0] RAM_1024_8 [0:1023]; // 1kB memory element RAM

integer a = 50; // 32 – bit integer declaration

real rval = 3.14; // assigning value to real register

real r1 = 2e6; // assigning 2x10^6 to r1 register

time t1 = $time; // getting simulation time

Levels of Abstraction
● Switching / Transistor Level (Not used)
● Gate Level
● Dataflow Level
● Behavioural Level
Gate Level
● It is a low level of Abstraction
● Circuit is described in terms of primitive gates
● Verilog supports basic logic gates as predefined
primitives
●
Gates can be instantiated like instantiating a
module
●

There are 2 classes of gates: and/or gates and

Buf/not gates
Some Primitive Gates
● And ● Or ● Xor
● Nand ● Nor ● Xnor

● Not
● Buf
Gate level Instantiation
● Syntax:
<Gate> <*delay> <Instance_name>(<o/p variable>,<input
variables>);

* Optional, delay will not be synthesised, used only for simulation

purpose
● Eg:
and #10 // 2-input And gate with propagation delay 10, o/p
a1(y,a,b); // pin = y, i/p pins = a, b; Gate Instance = a1
not n1(b,a); // Not gate with o/p pin = b, i/p pin = a; Gate
// instance = n1
 DATA FLOW
AND
BEHAVIORAL MODELING
Number Representation
Verilog HDL allows integer numbers to be specified as
Syntax: <size>'<radix><value>;

Where,
Size: bit length of value (1,2,3,4-bit, 8, 32,...etc)
Radix: value represented in which format:
Example:
● Bit > b
1'b1 // 1
● Hexadecimal -> h
8'hE4 // 228 or 1110_0100
● Octal -> o 4'd5 // 5 or 0101
● Decimal -> d
Value: the value which needs to be assigned
Verilog Operators
●
Arithmatic Operators

●
Relational Operators

●
Equality Operators

●
Logical Operators

●
Bit-wise Operators

●
Reduction Operators

●
Shift Operators

●
Concatination Operators

●
Replication Operators

●
Conditional Operators
Arithmatic Operators
● Binary Operators: +, - , *, /, %

● Unary Operators: +, -

● Modulus operator takes the sign of the first operand

●
If any operand value is 'x', then the entire value of the output
is 'x'
Relational Operator
Operation Description
a<b a less than b
a>b a greater than b
a <= b a less than or equal to b
a >= b a greater than or equal to b

●
The result is a scalar value (example a < b)
●
0 if the relation is false (a is bigger then b)
●

●
1 if the relation is true ( a is smaller then b)
x if any of the operands has unknown x bits (if a or b contains X)
Equality Operator
Operation Description
a === b a equal to b, including x and z state
a !== b a not equal to b, including x and z state
a == b a equal to b, result may be unknown
a != b a not equal to b, result may be unknown

●
Operands are compared bit by bit, with zero filling if the two operands do
not have the same length
●

●
Result is 0 (false) or 1 (true)
●
For the == and != operators, the result is x, if either operand contains an x or a
z For the === and !== operators, bits with x and z are included in the
comparison and must match for the result to be true
Note : The result is always 0 or 1 for row 1 and 2
Logical Operator
Operator Description
! Negation
&& Logical And
|| Logical Or

●
Expressions connected by && and || are evaluated from left to
right
●

●
Evaluation stops as soon as the result is known
The
 result is a scalar value:
 0 if the relation is false


1 if the relation is true
x if any of the operands has x (unknown) bits
Bit-wise Operator
Operator Description
~ Negation
& AND
| OR
^ Exclusive OR
~^ or ^~ Exclusive NOR

● Computations include unknown bits, in the following

way:

~x = x

0&x = 0



1&x = x&x = x
 1|x = 1
 0|x = x|x = x

0^x = 1^x = x^x = x
0^~x = 1^~x = x^~x = x
●
When operands are of unequal bit length, the shorter operand is zero-filled in
the most significant bit positions.
Reduction Operator
Operator Description
& and
~& nand
| or
~| nor
^ xor
~^ or ^~ xnor

● Reduction operators are unary.

●
They perform a bit-wise operation on a single operand to produce a
●
single bit result.
Reduction unary NAND and NOR operators operate as AND and OR
● respectively, but with their outputs negated.
Unknown bits are treated as described before.
Shift Operator
Operator Description
<< Shift left
>> Shift right

●
The left operand is shifted by the number of bit positions given by
the right operand.
●
The vacated bit positions are filled with zeroes.
ConcatenationOperator

● Concatenations areexpressed using the brace

characters
{ and

}, with commas separating the expressions within.
Example: + {a, b[3:0], c, 4'b1001} // if a and c
are8-bit numbers, the results has 24 bits
●
Unsized constant numbers arenot allowed in
concatenations.
Replication Operator
●
Replication operator is used to replicate a group of bits n times.
Say you have a 4 bit variable and you want to replicate it 4 times
to get a 16 bit variable: then we can use the replication operator.

Operation Description
{n{m}} Replicate value m, n times

● Repetition multipliers (must be constants) can be used:

 {3{a}} // this is equivalent to {a, a, a}

● Nested concatenations and replication operator are possible:

 {b, {3{c, d}}} // this is equivalent to {b, c, d, c, d, c, d}
Conditional Operator

● The conditional operator has the following C-like format:

<cond_expression> ? <true_expression> : <false_expression>;
●
The true_expr or the false_expr is evaluated and used as a
result depending on what cond_expr evaluates to (true or false).
Operand Precedence

Operator Symbols
Unary, Multiply, Divide, Modulus !, ~, *, /, %
Add, Subtract, Shift +, - , <<, >>
Relation, Equality <,>,<=,>=,==,!=,===,!==
Reduction &, ~&, ^, ^~, |, ~|
Logic &&, ||
Conditional ?:
Dataflow Level Modelling
●
At this level, the module is defined by defining the
data flow.
●
The designer is aware how the data flows between
the hardware registers and the data is processed in
the design.
Continuous Assignment
●
A continuous assignment replaces the gates in the
description of the circuit and describes the circuit in a higher
level of abstraction.

● A continuous assign statement starts with the keyword

“assign”

Syntax: assign <variable name> = <expression>;

Example

module A_1(sum,c_out,a,b); // Half adder declaration

input a,b; // input ports
output sum,c_out; // output ports
assign sum = a ^ b; // 2-input Xor gate
assign c_out = a & b; // 2-input and gate
endmodule
Example - 2
2x1 Mux

module Mux_2_1(out,s,a,b); // Mux declaration

input s,a,b; // input ports
output out; // output ports
// s=0 -> select a, s=1 -> select b
assign out = s ? b : a;
endmodule
BEHAVIOURAL
MODELING
Structured Procedures
●
There are two structured procedural assignments in
verilog: initial and always.
●
All behavioural statements can only appear inside any
of these procedural blocks.
●

All procedural statements are started at time 0 and run

●
parallel in Verilog
However all behavioural statements inside the blocks
● are executed sequentially.
Each block represents a separate activity flow
Initial Block
●
Initial block starts at exactly time 0
●
Executes exactly once during a simulation
●
Each block finishes execution independently,
irrespective of other blocks.
● This block is not synthesizable
Always Block
● The always block initiates at time 0
●
Statementsin the always block, execute in
a continuous loop fashion
●
Used to model a block of activity which is
repeated continuously in a digital circuit.
●

Synthesizability of this block is dependant on the

statements present within this block.
Syntax
Initial block: Always block:
initial begin always @(<event_list>) begin
. .
. .
. .
.. .
.... ....
end end
Event list: Denotes the variables which determine when and how the
register values used in the procedural block change.

Eg. for sequential circuits, event list will consist of clock pin and
reset pin.
Procedural Assignments
●
It is IMPORTANT to note that all the variables present in the left side of
the '=' symbol in the procedural blocks must be declared as either a
reg, integer, real or time.
● They should NOT be a wire.

●
However those variables found on the right side of the '=' simbol can
be any datatype.

:output
Input:
Proceduaral Block register only
net/register
 Blocking and Non blocking
Statements
Blocking statements: Non-Blocking statements:
Non-Blockingstatements allow
Blocking statements are executed in the
execution of the the
order they are specified in the order they
are specified in the sequential block. statements follow in the that
sequential block.
Only after the blocking assignment has
finished executing will it allow the next
instrictin in the block to execute.
Syntax:
Syntax:
initial begin
Inital begin
.
.
. // non-blocking
.
a <= 4'b0010; // statement
a = 4'b0010; // blocking statement
x <= a + x;
x = a + x;
...
...
end
end
Blocking Vs Non-Blocking
Blocking Non-blocking
<variable> = <statement> <variable> <= <statement>
Similar to C code The inputs are stored once
the procedure is triggered
The next assignment waits
until the present one is Statements are executed in
finished parallel

Used for combinational Used for flip-flops, latches

logic and registers

Avoid mixing both assignments in one

procedure
Example
module
blockingVSnba1; Blocking (procedural) assignment: the whole statement
integer i, j, k, l; must execute before control is released, as in
initial traditional programming languages.
begin
#1 i = 3;
#1 i = i + 1;
j = i +1; Non-blocking (procedural) assignment: all the RHSs for the
#1 $display( "i = %d, j = %d", i, j ); current time instant are evaluated (and stored
transparently
#1 i = 3; in temporaries) first and, subsequently, the LHSs are updated
#1 i <= i + 1; at the end of the time instant.
j <= i + 1;
#1 $display( "i = %d, j = %d", i, j );
$finish;
end
endmodule
System
Tasks
Standard routine operations provided by
●

●
Verilog All start with $
●
Some commonly used system tasks are listed
below:
$display, $monitor, $time, $stop, $finish,
$random, $time
$display
● $display: displays values of variables, strings,
expressions.
● Syntax: $display(p1, p2, p3, …, pn);
●
p1,…, pn can be quoted string, variable, or
●
expression Adds a new-line after displaying pn by
●
default
Format
●
specifiers:

%d, %b, %h, %o: display variable respectively in decimal, binary,

● hex, octal
●
%c, %s: display character, string
%e, %f, %g: display real variable in scientific, decimal, or whichever
● smaller notation
●
%v: display strength
●
%t: display in current time format
%m: display hierarchical name of this module
Example
reg [4:0] port_id;
$display(“ID of the port is %b”, port_id);
Output: ID of the port is 00101

reg [3:0] bus;

$display(“Bus value is %b”, bus);
Output: Bus value is 10xx

$display(“Hierarchical name of this module is %m”);

Output: Hierarchical name of this module is top.p1

$display(“A \n multi-line string with a %% sign.”);

Output: A
multi-line string with a % sign.
System Tasks Continued
● $monitor: monitors a signal when its value changes
● $stop: stops simulation
● $finish: terminates simulation
●
$random: assigns random value to variable it is
equated to
●
$time: displays current simulation time
Compiler Directives
General syntax:
`<keyword>
`define: similar to #define in C, used to define macros
`<macro_name> to use the macro defined by
`define
Examples:
`define WORD_SIZE 32
`define S $stop

`define WORD_REG reg [31:0]

`WORD_REG a_32_bit_reg;
Simple Behavioural Model
Modules are of three types: behavioral,
Sensitivity trigger: when any of a, b or c changes.
data-flow, gate-level. Behavioral
Replace this statement with “initial”. Output?!
modules contain code in procedural
blocks.
module aOrNotbOrc(d, a, b,
c); output d; Statements in a procedural block cannot
input a, b, c; be re-ordered without affecting the
reg d, p; program as these statements are
executed sequentially, exactly like in a
conventional programming
always @(a or b or c)
language such as C.
begin
p = a | ~b; Ports are of three types: input, output, inout.
d = p | c; Each must be declared. Each port also has a
data type: either reg or wire (net). Default is
end
wire. Inputs and inouts are always wire.
endmodule Output ports that hold their value are reg,
otherwise wire.
One port register, one internal register.
More later…

Wires are part of the more general class of nets.

However, the only nets we shall design with are
wires.
CompilerDirectives
General syntax:
`<keyword>
`define: similar to #define in C, used to define macros
`<macro_name> to use the macro defined by
`define
Examples:
`define WORD_SIZE 32
`define S $stop

`define WORD_REG reg [31:0]

`WORD_REG a_32_bit_reg;
Top level Test Bench
module stimulus; Verilog Good Design Principle There is one
integer i, j, k; top- level module, typically called system or
reg a, b, c; stimulus, which is uninstantiated and has no ports.
aOrNotbOrc X(d, a, b, c); This module contains instantiations of
lower-level (inner) sub-modules. Typical picture
initial below.
Instantiation
begin . Top-level
for ( i=0; i<=1; i=i+1 ) module
for ( j=0; j<=1; j=j+1 ) Inner
for ( k=0; k<=1; k=k+1 ) sub-modul
begin es
a = i;
b = j;
c = k;
#1 $display("a = %d b = %d, c = %d, d = %d", a, b, c, d)
end
$finish;
end
endmodule
Port Rules Diagram Outside
connectors to
EXTERNAL
internal ports, i.e.,
MODULE wir variables
of internal
e
Example: corresponding
module to
wir inou
ports in instantiation
module external e t
reg a;
wire b; Internal
ports
internal in(a, b); //instantiation
outpu
endmodule
… t
reg or wir
INTERNAL reg or wir
wire e
module internal(x, y) MODULE wire e
input x;
output y;
wire x;
reg y;
… General rule (with few exceptions) Ports in all modules except for
endmodule the stimulus module should be wire. Stimulus module has registers
to set data for internal modules and wire ports only to read data
from internal modules.
If Statement
Syntax

if (expression)
begin Example:
...statements...
end if (alu_func == 2'b00)
aluout = a + b;
else if (expression)
begin else if (alu_func == 2'b01)
...statements... aluout = a – b;
end else if (alu_func == 2'b10)
...more else if blocks aluout = a & b;
else // alu_func = 2'b11
else aluout = a | b;
begin
...statements...
end
Case Statement
Syntax

case (expression)
case_choice1:
begin
...statements... Example:
end case (sel)
case_choice2: 0: out = in[0];
begin 1: out = in[1];
...statements... 2: out = in[2];
end
3: out = in[3];
...more case choices blocks...
Default: out = 0;
default: endcase
begin
...statements...
End
endcase
For Statement
Syntax:
for(<initial_assignment>,<condition>,<step_assignment>
) begin
<statements>;
...
end
Note: This loop is partially
synthesisable,
Example: Depending on the
staements present inside
the loop
for (i = 2'b0; i <= 2'b11; i = i + 2'b01)
#10 y = y + 8'h01;
While Statement

Syntax: Example:
while (<expression>) while (i < 3) begin
begin #10 Y = Y + 1;
<statements>; i = i + 1;
...
end
end

Note: This loop is not

synthesisable, Can only be
used in test bench.
Repeat and Forever Loop

Syntax:
repeat (<number of times>) Example:
begin repeat (4) #10 Y = Y + 1;
...
end Can be either an
integer or a variable
T = 20 time units
clk

Syntax:
Example:
forever
forever #10 clk = ~clk;
<statement>;

Note: These loopd are not

synthesisable, Can only be
used in test bench.
Function and
Tasks
●
Functions and tasks are subprograms consists of behavioral
statements and defined within a module
●
Useful for replacing repetitive code
●
Function

– Always execute in zero time

– Must have atleast one input argument
– Always return a single value
– Must call another function but not a task
● – Produces combinational logic
Task
– May execute in non-zero simulation time
– May have zero or more input, output or inout arguments
– May call functions or other tasks
– Produces combinational or registered logic
Function Example
// function definition - Multiplier // function invocation - MAC
function [15:0] mult; module mult_acc (
input [7:0] ina, inb;
input [7:0] a, b;
reg [15:0] r; input clk, clr;

integer i; output reg [15:0] mac_out

);
begin wire [15:0] mult_out, adder_out;
if (a[0] == 1)
r = b; assign adder_out = mult_out + out;
else
always @(posedge clk or posedge clr) begin
r = 0;
for (i=1; i<7; i=i+1) begin if (clr)

if (a[i] == 1) mac_out <= 16'h0000;

else
r = r + b << i; mac_out <= adder_out;
end
End
mult = r;
end //function invocation
assign mult_out = mult(ina, inb);
endfunction
endmodule
Task Example
module task_example;

// task definition - Adder

task add;
input a, b; // 2-input argument ports
output c; // 1-output argument port
begin
c=a+b;
end

endtask
initial begin
reg p; // task invocation, values are
add (1, 0, p); // passed in the order they appear
$display (“p = %b”, p);
end
endmodule
Design Under Test (DUT)
module example1(A,B,C,D,cond);

input [3:0] B,C,D;

input [1:0] cond;
reg [3:0] A;
output [3:0] A;

case (cond)
00: A = B + C + D;
01: A = B - C + D;
default: A = B + C - D;
endcase

endmodule
Recommended Books
● Digital Logic Design
-M. Morris Mano and Michael D. Ciletti “Digital
Design with an introduction to Verilog HDL”
-Randy Katz, Gaetano Borriello, “Contemporary Logic
Design”
●

Verilog HDL
-Samir Palnitkar. “Verilog HDL”
●
Text book
- Zainalabedin Navabi, “Verilog Digital System Design”
Reference
● http://en.wikipedia.org/wiki/Verilog
Kunle Olukotun, Stanford EE183, http://www.stanford.edu/class/ee183/handouts_win2003/lect2.pdf
●

http://www.asic-world.com/verilog/
●

●
Samir Palnitkar, “Verilog HDL, A guide to digital design and synthesis”, Prentice Hall Professional,
2nd Edition
● Steve Poret, RCS, deimos.eos.uoguelph.ca/.../ENG6530-StevePoret-PaperReview2008.ppt
●
staff.fit.ac.cy/com.tk/ACOE361/Design_Flow.ppt

● http://www.xilinx.com/fpga/asic.htm

Mr. Dilip Risbud, Mr. Sameer D. Sahasrabuddhe, Ms. Shailaja Kulkarni, “VLSI : An article about
VLSI field and How to make career in this field”,
http://www.kokanastha.com/career_guide/introduction_VLSI.html
●

http://www.csee.umbc.edu/~tinoosh/cmpe650/slides/FPGAs-1.pdf
●

Dr. Esam Al-Qaralleh, “Introduction to Verilog Hardware Description Language”, Princess Sumaya
University for Technology
●

Thanasis Oikonomou, “Verilog HDL Basics,” Computer science department, University of Crete,
Greece, October 1998.