M28C64

PARALLEL 64K (8K x 8) EEPROM

WITH SOFTWARE DATA PROTECTION

FAST ACCESS TIME: 90ns

SINGLE 5V ± 10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE: 28
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max 1

ENHANCED END OF WRITE DETECTION: PDIP28 (P) PLCC32 (K)

– Ready/Busy Open Drain Output
(only on the M28C64)
– Data Polling
– Toggle Bit 28

PAGE LOAD TIMER STATUS BIT

1
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY: SO28 (MS) TSOP28 (N)
300 mils 8 x13.4mm
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION Figure 1. Logic Diagram

DESCRIPTION
The M28C64 is an 8K x 8 low power Parallel VCC
EEPROM fabricatedwith SGS-THOMSON proprie-
tary single polysilicon CMOS technology. The de-
vice offers fast access time with low power
dissipation and requires a 5V power supply. 13 8
A0-A12 DQ0-DQ7

Table 1. Signal Names

W M28C64
A0 - A12 Address Input
E
DQ0 - DQ7 Data Input / Output RB *
W Write Enable G
E Chip Enable
G Output Enable
RB Ready / Busy VSS
AI01350B
VCC Supply Voltage

VSS Ground
Note: * RB function is only available on the M28C64.

June 1996 1/19

M28C64

Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections

VCC
A12
RB 1 28 VCC

DU

NC
RB
A7

W
A12 2 27 W
A7 3 26 NC 1 32
A6 4 25 A8 A6 A8
A5 A9
A5 5 24 A9
A4 6 23 A11 A4 A11
A3 7 22 G A3 NC
M28C64 A2 9 M28C64 25 G
A2 8 21 A10
A1 A10
A1 9 20 E
A0 10 19 DQ7 A0 E
DQ0 11 18 DQ6 NC DQ7
DQ0 DQ6
DQ1 12 17 DQ5
17
DQ2 13 16 DQ4

DU
DQ1
DQ2

DQ3
DQ4
DQ5
VSS
VSS 14 15 DQ3
AI01351C
AI01352D

Warning: NC = Not Connected. Warning: NC = Not Connected, DU = Don’t Use.

Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections

RB 1 28 VCC G 22 21 A10
A12 2 27 W A11 E
A7 3 26 NC A9 DQ7
A6 4 25 A8 A8 DQ6
A5 5 24 A9 NC DQ5
A4 6 23 A11 W DQ4
A3 7 22 G VCC 28 15 DQ3
M28C64 M28C64
A2 8 21 A10 RB 1 14 VSS
A1 9 20 E A12 DQ2
A0 10 19 DQ7 A7 DQ1
DQ0 11 18 DQ6 A6 DQ0
DQ1 12 17 DQ5 A5 A0
DQ2 13 16 DQ4 A4 A1
VSS 14 15 DQ3 A3 7 8 A2
AI01353C
AI01354C

Warning: NC = Not Connected. Warning: NC = Not Connected.

2/19
 M28C64

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
TA Ambient Operating Temperature – 40 to 125 °C
TSTG Storage Temperature Range – 65 to 150 °C
VCC Supply Voltage – 0.3 to 6.5 V
VIO Input/Output Voltage – 0.3 to VCC +0.6 V
VI Input Voltage – 0.3 to 6.5 V
(2)
VESD Electrostatic Discharge Voltage (Human Body model) 4000 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

Figure 3. Block Diagram

RB E G W

VPP GEN RESET CONTROL LOGIC

ADDRESS
A6-A12
LATCH
(Page Address)
X DECODE

64K ARRAY

ADDRESS
A0-A5
LATCH

Y DECODE SENSE AND DATA LATCH

I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01355

3/19
M28C64

Table 3. Operating Modes (1)

Mode E G W DQ0 - DQ7

Standby 1 X X Hi-Z

Output Disable X 1 X Hi-Z

Write Disable X X 1 Hi-Z

Read 0 0 1 Data Out

Write 0 1 0 Data In

Chip Erase 0 V 0 Hi-Z

Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH; V = 12 ± 5%.

DESCRIPTION (cont’d) OPERATION

In order to prevent data corruption and inadvertent
The M28C64 outputs the Ready/Busy write status, writeoperations an internal VCC comparatorinhibits
the M28C64-aaaX (aaa = access time) has no Write operation if VCC is below VWI (see Table 6).
Ready/Busy status and the relevant RB pin is Not Access to the memory in write mode is allowed after
Connected (NC). The circuit has been designed to a power-up as specified in Table 6.
offer a flexible microcontroller interface featuring
both hardware and software handshaking with Read
Ready/Busy, Data Polling and Toggle Bit. The The M28C64 is accessed like a static RAM. When
M28C64 supports 64 byte page write operation. A E and G are low with W high, the data addressed
Software Data Protection (SDP) is also possible is presented on the I/O pins. The I/O pins are high
using the standard JEDEC algorithm. impedance when either G or E is high.
Write
PIN DESCRIPTION Write operations are initiated when both W and E
Addresses (A0-A12). The address inputs select are low and G is high.The M28C64 supports both
an 8-bit memory location during a read or write E and W controlled write cycles. The Address is
operation. latched by the falling edge of E or W which ever
Chip Enable (E). The chip enable input must be occurs last and the Data on the rising edge of E or
low to enable all read/write operations. When Chip W which ever occurs first. Once initiated the write
Enable is high, power consumption is reduced. operation is internally timed until completion.
Output Enable (G). The Output Enable input con- Page Write
trols the data output buffers and is used to initiate Page write allows up to 64 bytes to be consecu-
read operations. tively latched into the memory prior to initiating a
Data In/ Out (DQ0 - DQ7). Data is written to or read programming cycle. All bytes must be located in a
from the M28C64 through the I/O pins. single page address, that is A6-A12 must be the
same for all bytes. The page write can be initiated
Write Enable (W). The Write Enable input controls during any byte write operation.
the writing of data to the M28C64.
Following the first byte write instruction the host
Ready/Busy (RB). Ready/Busy is an open drain may send another address and data with a mini-
output that can be used to detect the end of the mum data transfer rate of 1/tWHWH (see Figure 13).
internal write cycle (this function applies only to the If a transitionof E or W is not detected within tWHWH,
M28C64). the internal programming cycle will start.

4/19
 M28C64

Chip Erase 100µs after the previous byte. Up to 64 bytes may

The contents of the entire memory may be erased be input. The Data output (DQ5) indicates the
to FFh by use of the Chip Erase command by status of the internal Page Load Timer. DQ5 may
setting Chip Enable (E) Low and Output Enable be read by asserting Output Enable Low (tPLTS).
(G) to VCC +7.0V. The chip is cleared when a 10ms DQ5 Low indicates the timer is running, High
low pulse is applied to the Write Enable pin. indicates time-out after which the write cycle will
start and no new data may be input.
Microcontroller Control Interface
The M28C64 provides two write operation status Ready/Busypin (available only on the M28C64).
bits and one status pin that can be used to minimize The RB pin provides a signal at its open drain
the system write cycle. These signals are available output which is low during the erase/write cycle, but
on the I/O port bits DQ7 or DQ6 of the memory which is released at the completion of the program-
during programming cycle only, or as the RB signal ming cycle.
on a separate pin. Software Data Protection
The M28C64 offers a software controlled write
Figure 4. Status Bit Assignment protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 memory from inadvertent write cycles that may
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
occur due to uncontrolled bus conditions.
The M28C64 is shipped as standard in the ”unpro-
DP=Data Polling
TB =Toggle Bit tected” state meaning that the memory contents
PLTS=Page Load Timer Status can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
Data Polling bit (DQ7). During the internal write operation where no further write commands have
cycle, any attempt to read the last byte written will any effect on the memory contents. The device
produce on DQ7 the complementary value of the remains in this mode until a valid Software Data
previously latched bit. Once the write cycle is fin- Protection (SDP) disable sequence is received
ished the true logic value appears on DQ7 in the whereby the device reverts to its ”unprotected”
read cycle. state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
Toggle bit (DQ6). The M28C64 offers another way quences.
for determining when the internal write cycle is
To enable the Software Data Protection (SDP) the
completed. During the internal Erase/Write cycle,
device requires the user to write (with a Page Write)
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
three specific data bytes to three specific memory
first read value is ”0”) on subsequent attempts to
locations as per Figure 5. Similarly to disable the
read the memory. When the internal cycle is com-
Software Data Protection the user has to write
pleted the toggling will stop and the device will be
specific data bytes into six different locations as per
accessible for a new Read or Write operation.
Figure 6 (with a Page Write). This complex series
Page Load Timer Status bit (DQ5). In the Page ensures that the user will never enable or disable
Write mode data may be latched by E or W up to the Software Data Protection accidentally.

5/19
M28C64

Figure 5. Software Data Protection Enable Algorithm and Memory Write

WRITE AAh in WRITE AAh in

Address 1555h Address 1555h

Page WRITE 55h in Page WRITE 55h in

Write Address 0AAAh Write Address 0AAAh
Instruction Instruction
(Note 1) (Note 1)
WRITE A0h in WRITE A0h in
Address 1555h Address 1555h
WRITE
is enabled
SDP is set
Write Page
(1 up to 64 bytes)

SDP ENABLE ALGORITHM WRITE IN MEMORY

WHEN SDP IS SET

AI01356B

Note: 1. MSB Address bits (A6 to A12) differ during these specific Page Write operations.

Figure 6. Software Data Protection Disable Algorithm

WRITE AAh in
Address 1555h

WRITE 55h in
Address 0AAAh

WRITE 80h in
Page Address 1555h
Write
Instruction
WRITE AAh in
Address 1555h

WRITE 55h in
Address 0AAAh

WRITE 20h in
Address 1555h

Unprotected State
AI01357

6/19
 M28C64

AC MEASUREMENT CONDITIONS Figure 8. AC Testing Equivalent Load Circuit

Input Rise and Fall Times ≤ 20ns
1.3V
Input Pulse Voltages 0.4V to 2.4V
Input and Output Timing Ref. Voltages 0.8V to 2.0V
1N914
Note that Output Hi-Z is defined as the point where data
is no longer driven.
3.3kΩ

Figure 7. AC Testing Input Output Waveforms DEVICE

UNDER OUT
TEST
2.4V CL = 30pF
2.0V

0.8V
0.4V

AI00826
CL includes JIG capacitance
AI01129

Table 4. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: 1. Sampled only, not 100% tested.

Table 5. Read Mode DC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC 10 µA
ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA

(1) Supply Current (TTL inputs) E = VIL, G = VIL , f = 5 MHz 30 mA

ICC
Supply Current (CMOS inputs) E = VIL, G = VIL , f = 5 MHz 25 mA
(1)
ICC1 Supply Current (Standby) TTL E = VIH 1 mA
ICC2 (1)
Supply Current (Standby) CMOS E > VCC –0.3V 100 µA
VIL Input Low Voltage – 0.3 0.8 V
VIH Input High Voltage 2 VCC +0.5 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = –400 µA 2.4 V
Note: 1. All I/O’s open circuit.

Table 6. Power Up Timing (1) (TA = 0 to 70°C or –40 to 85°C)

Symbol Parameter Min Max Unit
tPUR Time Delay to Read Operation 1 µs

tPUW Time Delay to Write Operation (once VCC ≥ 4.5V) 10 ms

VWI Write Inhibit Threshold 3.0 4.2 V
Note: 1. Sampled only, not 100% tested.

7/19
M28C64

Table 7. Read Mode AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
M28C64
Test
Symbol Alt Parameter Unit
Condition -90 -120 -150
min max min max min max
Address Valid to E = VIL,
tAVQV tACC 90 120 150 ns
Output Valid G = VIL
Chip Enable Low to
tELQV tCE G = VIL 90 120 150 ns
Output Valid

Output Enable Low

tGLQV tOE E = VIL 40 45 50 ns
to Output Valid
Chip Enable High
tEHQZ (1) tDF G = VIL 0 40 0 45 0 50 ns
to Output Hi-Z

(1) Output Enable High

tGHQZ tDF E = VIL 0 40 0 45 0 50 ns
to Output Hi-Z
Address Transition E = VIL,
tAXQX tOH 0 0 0 ns
to Output Transition G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.

Figure 9. Read Mode AC Waveforms

A0-A12 VALID

tAVQV tAXQX

tGLQV tEHQZ

tELQV tGHQZ
Hi-Z
DQ0-DQ7 DATA OUT

AI00749B

Note: Write Enable (W) = High

8/19
 M28C64

Table 8. Write Mode AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Alt Parameter Test Condition Min Max Unit

tAVWL tAS Address Valid to Write Enable Low E = VIL, G = VIH 0 ns

tAVEL tAS Address Valid to Chip Enable Low G = VIH , W = VIL 0 ns

tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns

Output Enable High to Write Enable

tGHWL tOES E = VIL 0 ns
Low

tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns

tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns

tWLAX tAH Write Enable Low to Address Transition 50 ns

tELAX tAH Chip Enable Low to Address Transition 50 ns

tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs

tELDV tDV Chip Enable Low to Input Valid G = VIH , W = VIL 1 µs

tELEH tWP Chip Enable Low to Chip Enable High 50 ns

tWHEH tCEH Write Enable High to Chip Enable High 0 ns

Write Enable High to Output Enable

tWHGL tOEH 0 ns
Low

tEHGL tOEH Chip Enable High to Output Enable Low 0 ns

tEHWH tWEH Chip Enable High to Write Enable High 0 ns

tWHDX tDH Write Enable High to Input Transition 0 ns

tEHDX tDH Chip Enable High to Input Transition 0 ns

tWHWL tWPH Write Enable High to Write Enable Low 50 ns

tWLWH1 tWP Write Enable Low to Write Enable High 50 ns

tWHWH tBLC Byte Load Repeat Cycle Time 0.15 100 µs

tWHRH tWC Write Cycle Time 3 ms

tWHRL tDB Write Enable High to Ready/Busy Low Note 1 150 ns

tEHRL tDB Chip Enable High to Ready/Busy Low Note 1 150 ns

tDVWH tDS Data Valid before Write Enable High 50 ns

tDVEH tDS Data Valid before Chip Enable High 50 ns

Note: 1. With a 3.3 kΩ external pull-up resistor.

9/19
M28C64

Figure 10. Write Mode AC Waveforms - Write Enable Controlled

A0-A12 VALID

tAVWL tWLAX

tELWL tWHEH

tGHWL tWLWH1 tWHGL

tWLDV tWHWL

DQ0-DQ7 DATA IN

tDVWH tWHDX

RB

tWHRL

AI01126

Figure 11. Write Mode AC Waveforms - Chip Enable Controlled

A0-A12 VALID

tAVEL tELAX

tGHEL tELEH

tWLEL tEHGL

tELDV tEHWH

DQ0-DQ7 DATA IN

tDVEH tEHDX

RB

tEHRL

AI00751

10/19
 M28C64

Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled

A0-A12 Addr 0 Addr 1 Addr 2 Addr n

tPLTS

tWHWL tWHRH

tWLWH tWHWH tWHWH

DQ0-DQ7 Byte 0 Byte 1 Byte 2 Byte n

DQ5 Byte n

tWHRL

RB

AI00752C

Figure 13. Software Protected Write Cycle Waveforms

tWLWH tWHWL tWHWH

tAVEL tWLAX

A0-A5 Byte Address

tWHDX

A6-A12 1555h 0AAAh 1555h Page Address

tDVWH

DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63

AI01358

Note: A6 through A12 must specify the same page address during each high to low transition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.

11/19
M28C64

Figure 14. Data Polling Waveform Sequence

A0-A12 Address of the last byte of the Page Write instruction

DQ7

DQ7 DQ7 DQ7 DQ7 DQ7

LAST WRITE INTERNAL WRITE SEQUENCE READY

AI00753C

Figure 15. Toggle Bit Waveform Sequence

A0-A12

DQ6 (1)

LAST WRITE TOGGLE READY

INTERNAL WRITE SEQUENCE

AI00754D

Note: 1. First Toggle bit is forced to ’0’

12/19
 M28C64

Figure 16. Chip Erase AC Waveforms

tWHEH

tGLWH

tELWL tWLWH2 tWHRH

AI01484B

Table 9. Chip Erase AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit

tELWL Chip Enable Low to Write Enable Low G = VCC + 7V 1 µs

tWHEH Write Enable High to Chip Enable High G = VCC + 7V 0 ns

tWLWH2 Write Enable Low to Write Enable High G = VCC + 7V 10 ms

tGLWH Output Enable Low to Write Enable High G = VCC + 7V 1 µs

tWHRH Write Enable High to Write Enable Low G = VCC + 7V 3 ms

13/19
M28C64

ORDERING INFORMATION SCHEME

Example: M28C64 -90 X K 1

Speed Write Monitoring Package Temperature Range

-90 90ns blank RB function P PDIP28 1 0 to 70 °C
active
-120 120ns K PLCC32 6 –40 to 85 °C
X No RB function
-150 150ns MS SO28 300 mils
N TSOP28
8 x 13.4mm

Parts are shipped with the memory content set at all ”1’s” (FFh).
For a list of available options (Speed, Package, Temperature Range, etc... ) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.

14/19
 M28C64

PDIP28 - 28 pin Plastic DIP, 600 mils width

mm inches
Symb
Typ Min Max Typ Min Max
A 3.94 5.08 0.155 0.200
A1 0.38 1.78 0.015 0.070
A2 3.56 4.06 0.140 0.160
B 0.38 0.56 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.30 0.008 0.012
D 34.70 37.34 1.366 1.470
E 14.80 16.26 0.583 0.640
E1 12.50 13.97 0.492 0.550
e1 2.54 – – 0.100 – –
eA 15.20 17.78 0.598 0.700
L 3.05 3.82 0.120 0.150
S 1.02 2.29 0.040 0.090
α 0° 15° 0° 15°
N 28 28
PDIP28

A2 A

A1 L
B1 B e1 α C
eA
D
S
N

E1 E

1
PDIP

Drawing is not to scale

15/19
M28C64

PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

mm inches
Symb
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595

E1 13.89 14.10 0.547 0.555

E2 12.45 13.46 0.490 0.530

e 1.27 – – 0.050 – –

N 32 32
Nd 7 7

Ne 9 9
CP 0.10 0.004
PLCC32

D
D1 A1

1 N
B1

e
Ne E1 E D2/E2
B

Nd A

PLCC CP

Drawing is not to scale

16/19
 M28C64

SO28 - 28 lead Plastic Small Outline, 300 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 2.46 2.64 0.097 0.104
A1 0.13 0.29 0.005 0.011
A2 2.29 2.39 0.090 0.094
B 0.35 0.48 0.014 0.019
C 0.23 0.32 0.009 0.013
D 17.81 18.06 0.701 0.711
E 7.42 7.59 0.292 0.299

e 1.27 – – 0.050 – –
H 10.16 10.41 0.400 0.410

L 0.61 1.02 0.024 0.040

α 0° 8° 0° 8°

N 28 28
CP 0.10 0.004
SO28

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Drawing is not to scale

17/19
M28C64

TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm

mm inches
Symb
Typ Min Max Typ Min Max
A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469

E 7.90 8.10 0.311 0.319

e 0.55 – – 0.022 – –

L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°

N 28 28
CP 0.10 0.004
TSOP28

A2

22 21
e

28
1 E

B
7 8

D1 A
D CP

DIE

TSOP-c A1 α L

Drawing is not to scale

18/19
 M28C64

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

 1996 SGS-THOMSON Microelectronics - All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

19/19