452 IEEE TRANiACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO.

4, APRIL 1984

Carlo method,” J. Appl. Phys., vol. 41, no. 9, pp.3843-3845’, ical analysis of stability criteriaof GaAs FET’s,”ZEEE Trans. Elec-
1970. iron Devices, vol. ED-23, pp. 1283-1290, 1976.
[17] K. Yamaguchi, T. Toyabe,and H. Kadera,“Two-dimension:ll [I91 W. Shockley, “A unipolar ‘field-effect’ transistor,”Proc. IRE, vol.
analysis of vertical junction gate FET’s,” Proc. 7th ConJ Sold 40, pp. 1365-1376, 1952.
State Devices 1975, Suppl. to Japan. J. Appl. Phys., vol. 15, PI). [20] D. P. Kennedy and R. R. O’Brien, “Computer aided two-dimen-
163-168,1976. analysis
sionalfield-effect
junction
of the transistors,”ZBM J. Res.
[ 1 8 ] K. Yamaguchi, S . Asai, and H. Kodera,“Two-dimensionalnumet-Dev., vol. 14,pp.95-116,1970.

Generalized Scaling Theory and Its Application

to a MicrometerMOSFETDesign

Abstract-In this paper we present a generalized scaling theory which Arbitrary electric field.
allows for an independent scaling of the FET physical dimensions a11d
Surface field at threshold.
applied voltages, while stillmaintainingconstanttheshape of t ~ e
electric-fieldpattern.Thustwo-dimensionaleffectsarekeptunder Electron current density.
control even though the intensity of the field is allowed t o increar,e. Channel length.
The resulting design flexibility allows the design of FET’s with quartlx- Debye length.
micrometer channel length to be made, for either room temperature or Acceptor concentration.
liquid-nitrogentemperature. The physicallimitations of the scallirig Substrate acceptor concentration.
theoryaretheninvestigatedindetail,leadingtotheconclusiontkat
the limiting FET performances are not reached at the0.25-pm chanllel
Donor concentration.
length,Furtherimprovementsarepossibleinthefuture,provided Electron density per unit area.
certain technology breakthroughs areachieved. Mobile charge density per unit area.
Projected range.
NOMENCLATURE Drain parasitic resistance.
Boltzmann constant. Source parasitic resistance.
Current ideality factor. Sheet resistance.
Electron concentration. Spreading resistance.
Subthreshold current ideality factor. Absolute temperature.
Hole concentration. Bulk-source voltage.
Electron charge. Drain-source voltage.
Inversion-layer thickness. Gate-source voltage.
Carrier saturation velocity. Low logic level.
Depletion width. Threshold voltage.
Junction depth. Channel width.
Device area. Silicon dielectric constant.
Depletion capacitance. Drain-induced barrier lowering coefficient.
Inversion-layer capacitance, - a Q,/a &. Potentials scaling factor.
Gate-channel capacitance, - aQn/aVGs. Linear dimensions scaling factor.
Oxide capacitance. Electron mobility within the channel.
Electron diffusivity. Electron mobility at thefield Eo.
Electric field. Effective electron mobility within the channel.
Average normal field within the channel. Resistivity in the source region.
Critical field for velocity saturation. Standard deviation.
Electric potential.
Manuscript received January 19, 1983;revised May 10, 1983. Surface potential.
The authors are with the IBM Thomas J. Watson ResearchCenter,
Yorktown Heights, NY 10598. G. Baccarani is on leave from the llni- Surface potential at threshold.
versity of Bologna, Bologna, Italy. Low logic level variation.

0018-9383/84/040C~-0452$01.OO 0 1984 IEEE

BACCARANI e t al.: SCALING
THEORY AND ITS APPLICATION TO MOSFET DESIGN 453

I.INTRODUCTION limitations which affectthe behavior of very small devices,

and develop improved models to account for such effects in

I N THE LAST decade theminiaturization limits of MOS the evaluation of the device performance. Amongthese, we
devices have been the subject of several investigations [ 11 - shall consider:
[6]. In1972 Hoeneisen and Mead [ l ] identifiedthe drain- 1) The effect of the finite inversion-layer thickness (or lim-
source punchthroughandthe gate-oxide breakdown as the ited inversion-layercapacitance)which results in a transcon-
most important limiting factors. The subsequent development ductance degradation. Although this effect was already incor-
of the channel implant as a tool to adjust the thresholdvoltage porated in the early model by Pao and Sah [ 1 I ] ,it is only more
addedfurther flexibility tothe device design, allowing for recently that its importance has been pointed out in connection
bettertradeoffs betweendrain-inducedbarrierlowering and with reduced oxide thickness [ 121 ;
substrate sensitivity. 2) The mobility degradation effect due to the influence of
In the same year the scaling theory was first presented [7] , increasing normal fields [ 131 - [ 151 . Such an effect is responsi-
identifying concise design criteria for small dimension FET's. ble for degraded output characteristics in the triode region;
According to such a theory, if the device physical dimensions 3) Thesaturation of thedrift velocityoccurring at large
andappliedpotentials arescaledby acommonfactor I/K, parallel fields [ 161 - [ 181 ;
( K > 1) and the impurity concentration is increased by K , the 4) The effect of the source-drain contactand spreading
shape of the electric-field patternwithinthe scaled device resistances,which negatively influences the device character-
remains constant. Therefore, two-dimensional effects such as istics both in the triode region and in saturation [ 191 , [20] .
drain-source punchthrough and thresholdsensitivity to channel Sucha degradation is of course more severe as the channel
length and drain voltage remain under control. Such a theory width and lengthare reduced according to the: scaling rules.
was confirmed by the successful fabrication of 1-,um channel Conclusionsaredrawn in Section VIII, where we estimate
devices exhibiting the expected, properly-scaled characteristics theFETperformance achievable atthequarter-micrometer
with respect to those of a typical 5-pm FET technology [8] . level and discuss the feasibility of further device scaling.
Although the scaling theory has been widely used in the past
as a guide to MOSFET miniaturization down to the 1-pmlevel, 11. GENERALIZEDSCALINGTHEORY
its limited flexibility does not allow one to properly design a For any given device geometry and set of boundary condi-
quarter-micron channel FET by its straightforward application,tions, the field configuration within a MOSFET results from
the limiting factors being: thesolution of Poisson's andcurrentcontinuityequations,
1) Thetemperature variation of threshold voltage (e- 1 i.e.,
mV/"C) which leads to a large threshold fluctuation if an ex-
tended operating temperature range must be guaranteed. This -aZ$ = - - (a2$
t - - t -a2$ p-ntND-NA)
limiting sensitivity basically results from the temperature de- a x z ay2 azz
pendence of the Fermi level in the substrate and of the band
bending required to reach the onset of strong inversion;
2) The nonscalability of thejunctionbuilt-inpotential, where
which leads to a larger depletion width relative to the device J n = -qp,,n grad $ + 40, grad n. (3)
physical dimensions, and makes the short-channel effect more
severe. In subthreshold conditions the electron concentration neglig-
Both of the above properties call for the threshold andsupply ibly contributes to the space charge on the RHS of (1). There-
voltages to be reduced less thanconventional scaling would fore, (1) and ( 2 ) can be decoupled, and we can refer to (1)
indicate. only. Let us consider the variable transformation
In view of the above considerations, it would be desirable to
generalize the scaling theory, and identify the design criteria
that, while allowing the local field to increase, still conserve the
shape of the electric field and potential distributions within
the scaled device. So doing, the FET physical dimensions and
the applied potentials can be scaled by independent factors, by which (1) becomes
thus considerably improving the design flexibility while, at the
same time, keeping two-dimensional effects under control.
In the next section we present such a generalization, identify
the new rules to be followed for a proper scaling, and investi- and, simplifying
gate its consequences interms of achievable device perfor-
mance. In Section 111,we indicate the avenues of attack of a
quarter-micrometerchannelFET design, for both room and
liquid-nitrogentemperatureoperations.
In so doing, we Equation ( 5 ) is formally identical to (I), and can be interpreted
account for reasonable manufacturing tolerances and assume, as Poisson's equationfora scaled device. If theboundary
as a reference, a typical 1-pm process [9], [IO]. conditions (i.e., potentials at source, drain, and gate electrodes)
In Sections IV-VI1 we discuss the most important physical are proportionally reduced by K , solutions of (1) and ( 5 ) only
454 IEEE TRP.NSACTIONS ON ELECTRON
ED-31,
DEVICES,
VOL. NO. 4, APRIL 1984

differ bya scale factor,andthe shape of theelectric-f.eld TABLE I

pattern is the same in the two devices. The intensity of the GENERALIZED SCALING FACTORS ASSOCIATED WITH THE MOST
field,however, varies by X / K and does thereforeincreas:if IMPORTANT PHYSICAL QUANTITIES
Physical Parameter Expression Scaling factor
h>K.
Equation (4) represents the generalized scaling rules to be 77'K 300'K

applied when the voltages cannot be reduced in direct propor-

Lin. Dimensions w. L. to,, x, 1 /A
tion to the device physical dimensions. Since the field pattern
Potentials 00,os, 0,
is conserved within the scaled device, punchthrough and dr;lin- l/K

Impurity Conc.
induced barrier lowering are expected to remain essentially tm- NA, ND h 2/K

modified, in spite of the increase in the electric field strenEth.

Electric Fieid E A/K
It is straightforward to verify that, when h = K , (4) tend t o !he
Capacitances A Cox,A C, 1/X
conventional scaling rules [7], [8].
Current (uns. vel.) (W/L)pCox(Vos-VT) VDs
The implicit assumption underlying (4) is that, by suita Ay X/K2

scaling applied voltages and doping profiles, electron and Inole Current (sat. vel.) ks w cox (Vas- VT)V,,, I/K

concentrations increase by thefactor X 2 / ~ . As n and p Bre Power ID VDD X/k3 l/n2

exponential functions of 4, such an assumption is not justified Power Density I D VDD1A X3/2 X2/r2

except for holesin theneutral region. Within the deple.t:on Gate Delay C o VDD 1ID ./h2 1/A
region, however, ( n ,p ) << NA , so that the space-charge density Power-Delay Pr. ID vDD td l/hK2
is not affected by electron and hole concentrations and scales Line Resistance p l / A X
by the proper factor. Current Density ID / A X 3 / 2 X2/r
The Debye length L D = ( E , ~ T / ~ ~ N Awhich ) " ~represetlts
,
Time Constant R, C, I
the width of the intermediate layer between neutral and spat:e-
charge regions, scales by K'"/?L Thus only for constantvoltzge
scaling ( K = 1) is the Debye lengthreducedproportionally slightly varies vs h / but ~ is regarded as a constant throughout
with the lineardimensions.However, so long as L D is much the table. Therefore, the predicted scaling factors at 77 K for
smaller than the depletion width, the effect of a nonscaling drain current and gate delay are rather pessimistic for h > K ,
transition width has anegligible influence on the overall p o k n - while thoseassociated with power andcurrent densitiesare
tial andfield distribution. perhaps slightly optimistic.
When the FET operates in strong inversion (1) and (2) c m - The mostimportantlimitations resulting fromthe choice
not be decoupled anymore because the electron concentrati In h > K are represented by the increasesinpowerdensityby
effectively contributestothe space charge, and, due to the h 3 / ~ 3and , in current density within the interconnection lines
nonlinearity of the transport equation, we cannot expect n 1.0 by h 3 / ~ 2For
, a given chip size, the former effect leads to an
scale, as required, by the factorX 2 / ~within the channel. Never- increased power dissipation and enhanced heat-removal prob-
theless, so long as the inversion layer is thin enough to negli- lems. The latter is of special concern due to electromigration
gibly contributetothe surface potential,thetotalelectron and long-term reliability. Also, the increased oxide field must
density per unit area Ni still varies, as expected, by h / ~Tlt~us
. be contained within acceptable limits, because the mean time
the scaling principle still applies, even in strong inversion, in to failure is an exponential function of the oxide field itself
the limit of a vanishingly small channel thickness which pins [221 .
the surface potential at the onset value of strong inversion. The scaling laws for the constant-voltage scaling case may be
Thechannelthickness tinv is, within a classical model, i n - found by setting K = 1. In order to conserve the shape of the
versely proportional to the surfacefield and therefore scales electric-field pattern within the scaled device, thebulk im-
by ~ / h Thus
. only for constant voltage scaling does tinv scale purity concentration must increase by h 2 . In a recent paper
with the device physical dimensions. In general, tinv increases [ 191 , Chatterjee et al. suggested a criterion forMOSFET mini-
by the factor K relative to the oxide thickness, giving rise tc a aturization at constant supply voltage implying an increase of
transconductance degradation effect to be discussed in Section the bulk impurity concentration by X and a reduction of the
IV . oxide thickness by l l h 1 t 2 , Such a criterion, however, does not
Table I reports the scaling factors associated with the most conserve the shape of the electric-field pattern, allows for
important physical quantities, in the general case of h f. K. relatively moreextendeddepletion regions and reduces the
For n-channel logic circuits, gatedelay and power consunl3- gate control over the channel, making the short-channel effect
tion are primarily determined by the depletion-load chargillg more severe, and ultimately leading t o a source-drain punch-
current which, in turn, equals the enhancement device currel~t through. Within the cohstant voltage scaling scheme, the gate
atthe circuit logic threshold. In thiscondition,the dril't delay and power-delay product improve by X2 and X, respec-
velocity is generally not saturated at room andhigher tempera- tively, while the power/circuit increases by the latter factor.
tures, while theoppositeholdstrueat 77 K. Hence, tv,o The power density, however, increases by X3 and so does the
scaling factors are reported for a number of parameters i n c h 1- current density within the interconnection lines. Besides, the
ing current, gate delay, and power consumption.Thefactor field increase by X at still large applied voltages is of consider-
k , in the expression of the current for saturated drift velociry able concern due to increased impact ionization and related
is a slowly increasing function of theratio (l',s/LE,), L ' , breakdown phenomena. Hot-electron injection into the oxide
being the critical field for velocity saturation [21]. Thus I : , [23] represents an additional limitation associated with a pure
BACCARANI e t al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 455

TABLE I1 TABLE I11

PROPOSED ROOM-TEMPERATURE QUARTER-MICROMETER DEVICE PROPOSED LIQUID-NITROGEN QUARI-ER-MICROMET-ER DEViCE
DESIGN(QMDT) COMPARED WITH A 1-prn DESIGN
(LATV) ALONG DESIGN(QMDT) COMPARED WITH A 1 - w n DESIGN (LAW
W I T H ASSOCIATED SCALING PARAMETERS ALONG
W l l - H ASSOCIATED
S C A L I K G PARAMElERS

Physical Parameter LAW QMDT Sealing Factor Physical Parameter LATV QMDT Seallog Fpctor

Channel length (pm) 1.3 0.25 5.2 Channel length (pm) 1.3 0.25 5.2

Oxide thickness (nm) 25 5 5.0 Oxide thickness (nm) 25 5 5.0

Junction depth (pm) 0.35 0.07-0.14 5.0-2.5 Junction depth (pm) 0.35 0.07-0.14 5.0-2.5

Supply voltage (V) 2.5 1.O 2.5 Supply voltage (V) 2.5 0.6 4.2

Threshold voltage (V) 2.4 0.6 0.25 Threshold voltage (V) 0.6 0.15 4.0

Band bending (VI 1.8 0.8 2.25 Band bending (V) 1.8 0.5 3.6

Impurity Conc. 3xlOl’ 3 ~ 1 0 ’ ~ 0.1 Impurity

(cm-3)Conc. 3x10’’ 2 ~ 1 0 ’ ~ 0.15

constant-voltage scaling, which makes it impossible to properly effects, and assuming the temperature range 0-75”C, leads to
design submicrometer FET’s while maintainingthe(to day) the choice of VT = 250 mV at the largest operating tempera-
standard 5-V supply. ture (Le., 75°C). From circuit requirement considerations, the
supply voltage is then set at VDD= 4VT = 1 V, and therefore
III. 1/4 MICROMETER
MOSFET DESIGN K turns out tobe 2.5. This small power supply voltage is chosen
to reduce power ata given performance level aswell as to
In this section we discuss the design tradeoffs for a quarter- minimize the adverse effects of velocity saturation, mobility
micrometer channel FET, assuming a manufacturing tolerance degradation, and other high field effects. In order to reduce
of kO.1 pm. Both room temperature and liquid-nitrogen oper- theband bending as far as possible by the same factor, the
ationsareconsidered, leading to different device designs. In backgate bias (- 1 V for the LATV process) is reduced to zero;
doing so, we make use of the generalized scaling theory and this leads to apotentialdrop across the depletion region of
assume, as a reference, a typical 1-micrometer process called 0.8 V, as compared to 1.8 V for the LATV design. The corre-
LATV [ 9 ] , [ l o ] ,developed at IBM in the mid-seventies. sponding scaling factor is 2.25, fairly close to the desired value
Table I1 compares the most important physical parameters of K = 2.5. Finally, the impurity concentration is chosen ac-
forthe LATV andtheproposedquartermicrometer device cording to the generalized scaling rules, using the appropriate
technology (QMDT) and lists the corresponding scaling factors. factor A’/K = 10.
Assuming X = 5 , therequiredoxide thickness andjunction The relative advantages of liquid-nitrogen € E T operation in
depth turn out to be 5 nm and 0.07 pm, respectively. While terms of speed, reliability andheat removal problems have
it certainly represents a challenging task to properly grow and been widely discussed by Gaensslen et al. [26] . Table I11 re-
controla5-nmoxide,suchan objectivedoes not seem far ports the proposed physical parameters for the liquid-nitrogen
beyond today’scapabilities, in view of the large experience temperature design. In this case two factors allow us t o sub-
gained in 20 years of studiesandexperimental activities on stantially reduce the threshold voltage: 1) the stability of the
thesubject. Similarly, a0.07-pmdeepjunction can be ob- operatingtemperature,and 2) the possibility of positively
tained as lightly-doped
a source-drain extension, using a biasing the back contact, which makes the threshold voltage
suitable spacer technology [24]. The most serious limitations more insensitive tochannel-length variations.The optimum
of such an approach would be the large sheet resistance of the choice of the substrate bias must be as large as possible, but
source/drainextensions (R, 100 n/O) the implication of still low enough as to avoid any appreciable forward-bias cur-
which is discussed in detail in Section VI. A viable alternative rent. Experimental results show that such a current is a slowly
could be that of using a somewhat deeper source-drain region increasing function of the applied voltage, so long as the latter
having a smaller sheet resistance. Even though such a choice is maintained below 0.9 V.A reasonable compromisethat
represents a deviation with respect to the scaling theory, two- accounts for the various constraints is the choice of VT = 0.15
dimensional simulations using FIELDAY[25]showthat no V and VDD= 0.6 V, with the backgate contact tied up toVDD.
punchthrough effect occurs with junction depths up to 0.14 So doing, the need of an additional supply source is avoided.
pm, even at the lowest dimensional size o f L = 0.15 pm, while The resulting potential drop across the depletion region turns
the threshold sensitivity to channel length and drain voltage is out to be 0.5 V, with a corresponding scaling factor of 3.6, so
only slightly affected by the increased junction depth. that all the potentials are scaled by approximately avalue of 4.
In the design of a quarter-micrometer FET, the choice of the Inmost small dimensions MOSFET designs, one or more
threshold voltage is a crucial one, for it basically determines boron channel implants are performed which enhance the con-
the supply voltage to beused.If the design is intended for centration of acceptors in the channel region near the surface.
logic applications, the criterion one should refer to is the noise The implants have a twofold function: their primary use is to
margin that can be afforded, accounting for threshold sensitiv- adjust the threshold voltage to the desired value; however they
ityto effective channellengthand drainvoltage, operating also help reduce the depletion width under the gate and at the
temperature range, and process tolerances. An estimate of the junction curvature, thus suppressing punchthrough effects.
lowest possible threshold voltage, accountingforthe above In order to properly design the channel impurity profile, an
456 IEEE TR.ILNSACTIONS
ELECTRON
DEVICES,
VOL.
ON E D - ~ I NO.
, 4, APRIL 1984

algorithm has been developed by which the implant paramcters

are determined for any desired depletion width xd within a r,, = 5 nm
permissible range. The implanted profile can be either peg ked R,=2.o N, 3 . ~ 1 0 'cme3
~
V, = 0.3 V
attheinterface or within thesemiconductor.Inthe 12 tter
case, the following equations must be fulfilled

1:6a)
D
I
2o
0 '
50
I I
6080
1

70
, I

90
I

100 I10
I

DEPLETION WIOTH (nm)

Fig. 1. Projected range of the channel implant against depletion width
for the present room temperature FET design. The resulting thresh-
old voltage is 0.3 V for a long-channel device and 0.25 for a quarter-
micrometer FET. The dotted lines intersect the solid line at a deple-
tion width extending beyond the peakof the implant by the indicated
number of standard deviations.

where E , i andrepresentthe surfacefield andthesurfxe 4.0 1 I I I I I

potential, respectively, at the onset of strong inversion; N(l is
3.5 - T,, = 5 nm
the peak, R , the projected range, and u the standard deviat Ion N, = 3.~10" cm.$
of the assumed Gaussian impurity profile superimposed 0 : a 3.0 - Rp 2.a V, = 0.3 V
constant background doping N B , and NA(x) is the result.ing T v, 0.0Y
doping profile. In (6) the former terms represent the contriw- v
Y
1=75C
tion to the surface field (or potential) due to the space charge 2.0
D
Y
within the depletion region, while the latter is the contributjon
due to the space charge within the quasi-neutral region [27] .
ziE 1.5
1.0
The choice of thethreshold voltage andsubstrate bias
uniquely determines E , i and q5s, i , after the oxide thickn.l:ss 0.5 -

and the background doping have been chosen. Consequenl ly 0.0 1I 1 I I

(6) containsfour variables,namely N o , R,, a, and xd. 'Ne 50 60 70 80 90 100 110

DEPLETION WIDIH (nm)
assume that a fixed ratio exists between projected range and
standard deviation, as suggested by experience, and treat ':d Fig. 2. Implanted dose of the channel implant against depletion width
for the present room-temperatureFET design.
as an independent variable. The self-consistent solution of ('6)
for any value of xd then determines R , , u, and N o . Figs, 1 a zd
2 showtheprojected range andimplanted dose against .the
depletion width, whichprovide a threshold voltage 0.3 V at
75°C for a long-channel device. Such a value corresponds to
about 0.25 V for a nominal channel length of 0.25 pm. The
dotted lines in Fig. 1 intersect the solid curve at points rep:e-
senting a well-defined ratio between (xd - R,) and the stall&
ard deviation u. Of course, the choice of a smaller depleticn
width leads to amorepronouncedsubstrate sensitivity of
threshold voltage.
For several implant conditions, 2-D simulations using FIEL-
DAY [25] were performed, and the threshold dependence on
channel length and drain voltage was investigated. Fig. 3 shows 0 50 100 150 200
theparameter 7 = - ( d V , / d V ~ s ) against the long-channel DEPLETION WIDTH (om)
depletion width, and the 2-D simulation results are compared Fig. 3. Drain-inducedbarrierloweringcoefficientagainstdepletion
with the theory by Ratnakumar et al. [28] . A junction dep.:h width. The solid line represents the theory by Ratnakumar etal. [ 211,
of 0.1 pm was assumed in the calculation. The agreement i.s while the discrete points are the resultof numerical simulations.
remarkably good for eachconsideredchannel length, and jt
appears that, from the standpoint of short-channel effect, it of L = 0.15 pm. The choice of V , = 0.25 V already accounts
is generally desirable to reduce the depletion width to thelouv- for this worst-case threshold dependence upon drain potential.
est practical value. From Fig. 3 it appears that the factor 17 The choice of the depletion width must therefore be made
can be as low as 30 mV/V in the nominal case of L = 0.25 p ~ : : trading ~ off substrate sensitivity of the threshold voltage and
but it raises to about 80 mV/V at the lowest dimensional &;e short-channel effect.
BACCARANI e t al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 457

Similar considerationsapply to the choice of the channel

implant for the liquid-nitrogen device design. The substantially
reduced band bending and supply voltage allow a better con-
trol of thethreshold voltage which, therefore, can be set at
0.15 V in this design.
IV. EFFECTOF FINITEINVERSION-LAYER CAPACITANCE
In MOSFET modeling it is generally assumed that the mobile
channel charge increases linearly with gate voltage for biases
above threshold. This is indeed the case so long as the oxide
thickness is much larger than the inversion-layer width, and for
0.0
relatively large applied voltages. Using ideal constant-field 0.0 0.5 1.0 1.5 2.0 2.5 3,O
scaling, the inversion-layerthicknessremainsessentially con- GATEVOLTAGE(V)
stant while theoxidethickness is reducedaccording t o the Fig. 4. Normalized theoreticalandexperimental gate-channel capaci-
scaling factor. Consequently, the oxide capacitance increases tance against gate voltage for an FET having an oxide thickness of
relative tothe inversion-layer capacitance, Cj= -(aQ,/&$,) 10.3 run.
leading to a sub-linearchannel-chargevariation and to a de-
graded transconductance.Theeffect of the inversion-layer
capacitance was already incorporated in the early model by
Pao and Sah [ 111 , assuming a uniform impurity concentration. 4 I
Modern FET's, however, invariably require a channel implant
which considerably alters the surface field. Consequently, their
integral expression cannot be expected t o provide quantitatively
3 I
good results.
To calculate the inversion-layer capacitance, we take advan-
tage of the fact that theinversion-layer width is generally much
thinner than the scale of length over which the doping density
appreciably varies, and solve Poisson's equationwithinthe
inversion layer, assuming as a doping the surface value Ns [30] . 0.0 0.5 1.0 1.5 2.0 2.5 3.0
At theposition where n = Ns we impose the value of the GATEVOLTAGE (V)
electric field resulting from the solution of Poisson's equation Fig. 5 . Theoretical and experimental channel charge against gate volt-
within the depletion region,where the carrier density is ne- age for an FEThaving an oxide thicknessof 10.3 nm.
glected. So doing, the value of the inversion-layer capacitance
and channel charge can easily be determined, within a classical
model, by accounting for the propersurface field,
It is well known that the motion of electrons normal to the
interface is quantized within the inversion layer [3 11 , and that
the conduction bandis split in several sub-bands, eachof which
representsatwo-dimensionalcontinuum associated witha
well-defined energy level. Accountingforthesequantum
effects requires thesimultaneoussolution of Poisson's and
Schroedinger's equations; besides, at room andhigher tempera-
tures several sub-bands are occupied, which makesthe com-
putational problem extremely heavy. Although less appealing
from the conceptual point of view, the classical model turns 0.0 0.2 0.4 0.6 0.8 1.0
out to quantitatively interpret the effect under investigation, GATEVOLTAGE (V)
as shownin Figs. 4 and 5 . Theformerrepresentsthe gate- Fig. 6. Theoreticalchannel chargeagainst gate voltage for anFET
channelcapacitance CGC= - ( a Q , / a V ~ s ) measured at room having an oxide thickness of 5 n m .
temperatureswiththe quasi-static C-V technique[32]ona
structure having a 10-nm thick oxide; the latter represents the of accuracy due to the uncertainty on the exact position of
channel charge Q,, obtainedbyintegration of the channel the Fermi level within the degenerately-doped poly-gate. The
capacitance. As can be seen, the agreement is excellent over doping profile within the semiconductor was separately deter-
the whole range of applied voltages, indicating that the classi- mined with an independent measurement, and wasnot adjusted
cal model can adequately interpret the above behavior at room to fit thecapacitance and charge data.
and higher temperatures. It should be observed that the above Fig. 6 shows calculatedresults using the same modelfor
fittings contain two adjustable parameters: the oxidethickness, inversion-layer charge versus gate v.oltage at 75°C for an FET
which sets the asymptotic behavior of the channel capacitance, having a5-nm gateoxide andachannelimplantsuchthat
and the flat-bandvoltage, which is known with a limiteddegree V , = 0.3 V. Atthe largest gatevoltage, thetotal channel
458 IEEE TRAPISACTIONS ON ELECTRON DEVICES,
VOL. ED-31, NO. 4, APRIL 1984

charge turns out to be 15 percent less than expected by r e -

glecting theeffectofthe inversion-layercapacitance. ?'-le
quantitative extent of this charge decrease is therefore far i a s
important than predicted by El-Mansy [20] who, within the 103 -
900 -
constant-voltage scaling scheme, assumed a constant inversic:n- 800 -
700 -
layer thickness of 10 nm regardless of the surface field, a Id 600 -
reached the conclusion that a 50-percent degradation occlirs 500 -
with an oxide thickness of 5 nm. 400 ~ ,
V. MOBILITY DEGRADATIONEFFECT. 300 ~

T,, = O
I nm, V,, 0.0 V
The electron channel mobility is known t o be a decreasing T,, I nm, VIS
O 1 0.5 V

function of the normal field [ 131- [15] . In order to experi- 104 105 106
mentally determine such a functional dependence, a combilr~a-
AVERAGE FIELD (V/cm)
tion of channel capacitance and drain current measuremerits
Fig. 7. Experimentalelectronmobility against average field atroom
were digitally performed at room temperature on large arc:a, temperature.
thin oxide FET's, using the technique described in [ 151 , :3y
integration of the inversion-layer capacitance,the chanllel
charge was determined for each value of the gate voltage, and
the experimental curve was fitted with the model described in
the previous section, using flat-band voltage and oxide capaci-
tance as adjustable parameters.Theturn-on characteristic
measured with a constant drain voltage, VDS= 100 mV, was
then used todeterminethechannelmobility.It was found
that the drain voltage was by no means small enough to keep
the inversion layer uniform throughout the channel, except at
the largest gate voltages. If not properly accounted for, 1he
channel nonuniformityproducesafictitiousmobility maxi- 4
0
/I I 1
mum in the vicinity of threshold,and severely reduces..he 0.0 0.2 0.4 0.6 0.8 1.0
achievable accuracy, even in strong inversion. When the n'm- GATE VOLTAGE(V)
uniformity of thechannel was accountedforby using :he
Fig. 8. Predicted turn-on characteristic for the quarter-micrometer FET.
generalized Pao-Sah integralexpression, suchamaximIm
disappeared, and the carrier mobility turned out to monotc'ni-
cally decrease as thenormal fieldincreases. As already Ib- a remarkably linear characteristic results in the over-threshold
served bySabnis and Clemens [14],the various mobility condition. If one tries to extract the carrier mobility from the
curves, when plotted against the average normal field exp:ri- slope of the curve at the inflection point by simply dividing
enced by the carriers within the inversion layer, merged h t o by theoxidecapacitance, an effective mobility p,ff = 318
one universal curve as shownin Fig. 7 . Here we report the cm2/V . s is found, while theactualmobility value at that
mobility data extracted from 4 samples, having oxide thick- point is about pn = 380 cm2/V s. Thisnearly-linear turn-on
nesses of 10 and 26 nm, and different channel implants. Over characteristic allows an easy estimate of the achievable device
the range of average fields 2 X lo4-6 X lo5 V/cm, the elect 'on performance, as we shall see in Section VIII.
mobility can be described by the empirical expression
VI.SATURATIONOF THE DRIFTVELOCITY
p n = p 0 ( ~ 0 / ~ , ) 1 1=33.25 . 1o4~;;I3 17)
The gate delay in n-MOS circuits is basically determined by
where po is the carrier mobility at the arbitrary field E o . A the depletion-load charging current which, in turn, equals the
possible choice of the above parameters is po = 700 cm2/W s, enhancement device current at the circuit logic threshold. In
and Eo = lo5 V/cm. our room-temperature FET design, the electron drift velocity
Mobility is reduced in small dimensionFET's relative to is not saturated at the circuit logic threshold (assumed equal
larger devices due t o an increase in the average normal f d d to VDD/2)while it happens to be so at VDs= Vcs = 1 V. For
in the inversion layer. This may be broughtabout by yon- the liquid-nitrogen operating FET, instead, saturation of the
proportional voltage scaling (X > K). Even when proporticlnal drift velocity occurs even at the logic threshold, so that dif-
scaling (X = K) is applied, E, will increase due to the r on- ferent projections are to be made when investigating the effect
scalability of thework-function difference
between the of scaling.
degenerately-doped poly-gate and the inversion layer. If the device current is limited by the saturation of the drift
Using (6) within the generalized Pao-Sah formula, the t l m - velocity ratherthan channel pinchoff, we may refer to the
on characteristic shown in Fig. 8 is found for a squareIiET expression [ 21]
with a 5-nm oxide and an n+ poly-gate, at 75°C. For sw:h a
device, the decreasing mobility is compensatedfor by the
increase in the inversion-layer capacitance in such a way :hat where k, is a slowly-varying function of the ratio ( V G S - V T ) /
BACCARANI et al.: SCALING THEORY AND ITS APPLICATION
MOSFET
TO DESIGN 459

LE,, E , being the criticalfield for velocity saturation. By few-hundreds C? pm is tolerable at the 1/4 micrometer chan-
neglecting the weak dependence of k, and uMt upon X/K, the nel level.
device currentturnsoutto vary as 1 / ~andthe gate delay The source resistance results from the combined effect of a
scales by l / h , independentof K . This is indeedthe case at contact resistance [33], a geometrical resistance related to the
liquid-nitrogen temperature, where increasing the
electric shape factor of the sourceregion, and a spreadingresistance
field by a nonproportional voltage scaling does not produce due to the crowding of the current-flow lines in the vicinity of
any appreciable speed advantage and only increases the power/ the channel [34]. The contact resistance has been investigated
circuit. At roomtemperature,instead,a considerablespeed by Scott et aZ. [30] using a transmission-line equivalent circuit
gain can be obtained for n-MOS circuits bychoosing K < h , model for a variety of geometries. It should be stressed, how-
until saturation of the driftvelocity occurs at logic threshold. ever, thatthecontact resistance is a technological problem
rather than a fundamental one, and that improvements can be
VII.EFFECT OF THE SOURCE-DRAIN expected in the future as the study of contact metallurgy pro-
PARASITICRESISTANCES. gresses. So far, a resistance of 15 C? on a square micrometer
contact, using A1-Ti has been reported [32] . Such a value is
The increasing importance of the parasiticsource-drain re-
very encouraging, for it is one order of magnitude below the
sistances as theFET physicaldimensions are progressively
estimated limits forperformance degradation given above.
shrunk, was pointed out by Chatterjee et aZ. [I91 and by El-
The geometrical and spreadingresistances are certainlyofa
Mansy [20] , who investigated the resulting reduction in gain
more fundamental nature than the contact resistance, since the
factoratthe largest operating voltage. For n-MOS circuits,
conductivity of heavily-doped silicon is a material property,
however, it is the current at the logic threshold that mostly
and a major breakthrough in this area cannot be expected in
matters, for the gate delay is dominated by the rise time which,
the near future. The geometrical resistance can be kept to a
in turn, depends upon the depletion-load current. The effect
minimum value by using self-aligned silicided junctions with
of the parasiticresistance is two-fold:first,it reduces the
short and relatively conductive .source/drain extensions.
enhancement-devicecurrentatthe logic threshold,thus re-
The spreading resistance effect was investigated by a simpli-
quiring a smaller depletion-load charging current; next itraises
fiedtwo-wire model [36], using a Schwartz-Christoffel con-
the low logic level, thus impairing the noise-immunity margins.
formal transformation.In reasonably general conditionsthe
As far as the former effect is concerned, the current at VGS=
following result was found
VDS = VDD/2, assuming VT = V D D / 4 , turns out to be
2 R X'
Rspr= - In (0.75xj/tin,)
71w
where R , represents the sheet resistance of the source region,
where n, = 1 + CC /,, C, is the depletion capacitance, and
and xi the junction depth. Equation (12) must be added to
R , is the source resistance. In order to limit the current deg- the geometrical resistance. This resistance wa.s evaluated for the
radation to less than 5 percent in our design, the technology
two limiting cases of xi = 0.14 where R , = 50 f2 and 0.07 pm
must provide a source resistance such that WRs < 228 SZ * pm.
where R , = 500 SZ. The resistivity for these two cases was de-
The voltage drop AVL on the source drain resistances ( R s t
termined by process simulation and experience for a given hot
RD) at the lowlogic level is
processing cycle. In these structures the srnaller ratio xi/tinv
AVL = (Rs + R D )IDLT ( 10) relative to the latter case is more than counterbalanced by the
larger resistivity, so that the total spreadingresistance turns
and turns out to be 10 mV, assuming R s = R D and WRs =
out to be approximately 90 f2-wor four times larger than in
228 i2 . pm, as before. Such a value is certainly compatible
theformer case. Fromthe above considerations,it appears
withthe available noise margins;it is quite clear,however,
thatthelightly-doped source-drain extensionsmust be care-
that a resistance value of the order of 1 ki2 . pm would signif-
fully designed, trading offparasiticsourceresistance and
icantly impair both noise margins and gate delay.
short-channel effect.
Atliquid-nitrogentemperature,thecurrent is limitedby
velocity saturation; itsvalue at the logic threshold is
VIII. DISCUSSIONAND CONCLUSIONS.
By taking into account all the physical limitations discussed
4
so far, it appears that scaling down to a micrometer channel
and a 5-percent reduction occurs for -
WRs = 145 C? pm, as- length still leads to a considerable speed advantage, compared
suming k , = 0.4, and usat = lo7 cm/s. to larger device geometries. The achievable gate delay versus
Due to the higher current at the logic threshold, the liquid- power is reported in Fig. 9 andcomparedwith LATV [9]
nitrogen design is thus more severely affected by the parasitic results, assuming for both cases a fan out of 3 and properly
source resistance, and poses more demanding requirements on scaled capacitance loads. As it appears from the figure, a gate
its upper limit. The low logic level VL varies according to (1 o), delay of 300 ps is possible at a power/circ:uit of 25 pW/gate.
and again the increased current leads to a more pronounced Increasing the power/gate to 60 pW would lead to a gate delay
variation of V L . From the above considerations, however, it of 200 ps. These projectionscontradict previous resultsby
can be generally stated that a parasitic source resistance of a El-Mansy [20]andby Shichijo [37] who predicted an opti-
460 IEEE TRtlNSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 4, APRIL 1984

10-5 1 @-' 10-3

1o-'Q

1Q i
p,;;
.' .....,
, , , ,

10.'
,
..
, ,
......*............. ..............._
,,,,I
10-3
POWERjClRCUlT (W) POWER/CIRCUIT (W)

Fig. 9. Gate delay against power/circuit at 7 5 ° C for the LATV tech- Fig. 10. Gatedelay against power/circuitatliquid-nitrogentempera-
nology and the proposed QMDT. The calculation assumes a f.0. = 3 ture for the LATV technology and the proposed QMDT. The calcula-
and properly scaled load capacitance. tion assumes a f.0. = 3 and properly scaled load capacitances.

mum device performanceat 1- and0.5-pmchannellength, [39] using X-ray lithographic techniques and maintaining the
respectively. The reason forthe abovediscrepancies is tllat vertical profiles typical of the I-pm technology. These devices
different assumptions were made by these authors, leading to have demonstrated an excellent speed performance, reaching a
entirely different results. El-Mansy considersaconstant-vcllt- gate delay of 30 ps in an unloaded ring oscillator. The ques-
age scaling down to the quarter micrometer channel leng :h, tion is therefore in order: is the effort of reducing all the verti-
and assumes a constant inversion-layerthickness of 10 nm, cal dimensions (including oxide thickness) worthwhile, if the
regardless of the value of the normal field. As shown in S w same performance can be obtainedwithsomewhat more re-
tion IV, however, suchan assumption is not justified andleads laxed conditions? In our opinion, the basic limitation of these
to a pessimistic estimate of the inversion-layer capacitance devices is the large threshold sensitivity to drain voltage [40],
effect. Shichijo, instead, considers several kindof scaling which makes the achievable voltage gain fairly small, i.e., 2-3
schemes, and investigates the impact on thegain factor and t.le only, with a negative effect on noise immunity margins. Such
saturation current of the various limitations discussed so filr. an effect can be alleviated by increasing the substrate doping,
In doing so, however, he assumes asheetresistance varyi::tg but then a more severe threshold sensitivity on backgate bias
inversely with the 5th power of junction depth and lets tlle would result. Also, the relatively small gate capacitance (and
junction depth proportionally scale like all other physical tLi- transconductance) makes them more susceptible to the influ-
mensions. Therefore, the parasitic
source-drain
resistantx ence of interconnect capacitances, unless unreasonably large
turns out to be the primary cause of performance degradatio 11. aspect ratios or higher voltages are used, with an accordingly
Two orders of objections can be raised about the above pr3- increased power dissipation. In our proposed design, instead,
cedure: first, if the sheetresistance of an implanted layer is the proper scaling of the horizontal and vertical device dimen-
effectively increasing with the 5th power of l / x i , it is totally sions allows us to keepconstantthedrain-induced barrier
unreasonable to let xi proportionally scale withthe devic:e lowering factor 9, so that the available voltage gain remains
physical dimensions. On the other hand, it is well known that constant,andnonoise-immunity margin degradation is ex-
the influence of junction depth on drain-induced barrier lower- pected. Besides, so long as theinterconnect capacitances
ing is weak [38], and punchthrough can be prevented by #a scale by the proper factor, no increased susceptibility to their
suitable channel implant. Consequently, a better tradeoff calls influence is expected. From the standpoint of device manu-
for a nonproportional scaling of the junction depth, to thead- facturability,theproposed design does not requiremajor
vantage of the parasiticsource-drainresistance. Next, a shal- modifications of the MOS technology as it is today, but rather
lower junction can be obtained in several ways: reducing the irtl- an evolutiontowardthinner gateoxides andproportionally
planation dose for a given processing cycle is the simplest, but a reduced fabrication tolerances.
viable alternative is to reduce the annealing temperature and the Although the primary goal of this paper was that of demon-
implant energy. If such a strategy is pursued, a weaker shect strating the feasibility of a quarter-micrometer n-channel FET
resistance variation against junction depth can be obtained. for logic applications, most of the above considerations apply
Fig. 10 shows a similar comparison at liquid-nitrogen terr - to p-channel devices as well. Due to the smaller hole mobility,
perature. The smaller voltage used in this design considerabti and to the larger sheet resistance of p+ shallow junctions, how-
reduces the power dissipation so that, for a given power/circuil ever, quantitatively different results are obtained in this case,
the performance improvement over that of the LATV technol- leading to somewhat modified design tradeoffs. Also consid-
ogy is even more pronounced. A gate delay of 100 ps can bl: erations related to the effect of the parasitic source resistance
achieved at a power/circuit of 50 pW. on the gate delay of CMOS circuits should be revised to account
Recently,0.3-pmchannel FET's have been manufacturetl for the specific switching mechanisms of CMOS gates. In spite
BACCARANI e t al.: SCALING THEORY AND ITS APPLICATION TO MOSFET DESIGN 46 1

of themore severe limitationsofp-channel FET’s, however, characteristicsforhigh-perf,ormance logic applications,” IEEE J.

theinherentlylow powerdissipation of CMOS circuits makes Solid-St. Circuits, vol. SC-14, pp. 247-255,Apr.1979.
[ 111 H. C. Pao and C. T. Sah, “Effects of diffusion current on charac-
them attractive candidates forVLSI applications. teristics of metal-oxide(insulator)semiconductortransistors,”
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supply of 1 v wouldbecertainlybeneficial from the perfor- [ 121 Y . Hayashi,“Staticcharacteristics of extremelythingateoxide
MOS transistors,” Electron. Lett., vol. 11, pp. 618-620, 1975.
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even take advantage Of overshoot effects [371 ’ but May 1968.
[ 141 A. G. Sabnis and J. T. Clemens, “Characterization of the electron
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material having a dielectric constant at least twice as large as [ 151 s. C. Sun and J. D. Plummer, “Electron mobility in inversion and
accumulation layerson thermally oxidized silicon surfaces,” IEEE
silicon dioxide’s, so that its thickness need notbe scaled down Trans. Electron Devices, vol. ED-27, pp. 1497-1508, Aug. 1980.
to limits incompatible with reproducibility and reliability, and 161 F. F. Fang and A. B. Fowler, “Hot electron effects and saturation
and the tunneling of electrons across the insulator can be kept velocitiesin silicon inversion layers,” J: Appl. Phys., vol. 41, pp.
1825-1831, Mar. 1970.
to an insignificant level. Also, an improved gate material with 171 R. W. Coen. and R. S. Muller, “Velocity o$ surface carriers in in-
a high conductivity and a more suitable work-function [29] version layers in silicon,” Solid-state Electron., vol. 23, pp. 35-
for the required thresholdvoltage would be desirable. Alterna- 40, 1980.
181 J. A. Cooperand D. F.Nelson,“Measurement of the high-field
tively, new device structures with more contained short-chan- drift velocity of electrons in inversion layers in silicon,” IEEE
ne1 effect should be devised, so that scaling the channel length Electron Device Lett., vol. EDL-2, July 1981.
would be compatible with the vertical profiles typical of larger 191 P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin,
“The impact of scaling laws on the choice of n-channel or p-chan-
devices. In any case, it is anticipated that power density and ne1 for MOS VLSI,” IEEEElectronDevice Lett., vol. EDL-1,
relatedheat removal problems, along with increased current . DU. 220-223. Oct. 1980.
density within the interconnect wires, will be the major prob- 1201 Y: A . El-Mansy, “Limits to scaling MOS Devices,” in 1981 Symp.
on VLSI Tech. Dig. Tech.Papers, pp.16-17,Sept.1981; also
lems t o be carefully considered, and will ultimately establish “MOS device and technology constraints in VLSI,” IEEE Trans.
whether the goal of a 0.1-pm FET is worth the effort. Electron Devices, vol. ED-29, pp..567-573, Apr. 1982.
[21] B. Hoefflinger, H. Sibbert,andG.Zimmer, “Model andPerfor-
mance of hot-electron MOS transistors for VLSI,” IEEE Trans.
ACKNOWLEDGMENT Electron Devices, vol. ED-26, pp. 513-520, Apr. 1979.
The authors are grateful to C. J. Han and R. P. Havreluk for [22] C. M. Osburn and E. Basspus, “Improved dielectric reliability of
SiOzfilmswithpolycrystallinesiliconelectrodes,” J: Electro-
their help in the electrical characterization. The personnel of chem. Soc., vol. 122, pp. 89-92, Jan. 1972.
the Silicon Fabricationgroupatthe T. J. Watson Research [23]T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Osburn, S. E.
Center is also acknowledged for fabrication of the hardware Shuster, and H. N. Yu, “1-pm MOSFET VLSI technology: Part
IV-Hot-electron design constraints,” IEEETrans.ElectronDe-
used in this paper. vices, vol. ED-26, pp. 346-353, Apr. 1979.
[24] C. M. Osburn, M.Y. Tsai, S. Roberts, C. J. Lucchese, and C. Y.
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Recombination Lifetime Using the Pulsed MOS

Capacitor
DIETER K. SCHRODER, SENIOR MEMBER, IEEE, JAMIS D. WHITFIELD, AND CHARLES J..VARKER, MEMBER, IEEE

Abstract-The pulsed MOS capacitor is routinely used t o measure h e to measure the generation lifetime rg since its introduction in
generationlifetime.A new technique is describedhereinwhich he 1966 [l] . Anumber of refinements have been added[2] -
samedevice is used to obtaintherecombinationlifetime.Themea- [ 5 ] , but the extracted information is still generally T ~ .The
surement technique is identical to the commonlyused pulsed C-t met1 od
except that the device is operated at an elevated temperature of ’; Q- technique is useful because an MOS capacitor is usually in-
100°C, where quasi-neutral current originating below the space-chaLrge cluded in wafer test patterns. The generation lifetime can be
region dominates over space-chargeregion currents. The new techniq de, used to characterize the generation rate of reverse biased space-
coupled with established techniques, makes possible the simultaneous charge regions for p-n junction diodes and capacitors and there-
determination of T~ and 7,. fore provides information on the charge storage properties of
DRAM’S and CCD’s. Ithastheadditional advantage thatit
samples a well-defined volume of the material, which is deter-
INTRODUCTION mined by the gate area and space-charge region (scr) width,

T HE CARRIER lifetime is an important parameter in the

operation of many semiconductor devices. For example,
the switching time of bipolar devices, the leakage current of F .=n
the latter being controlled by the applied voltage and there-
fore under the operator’s control.
Recombination processes are characterized by the recombi-
junction diodes and charge-coupled devices, andthe refresh nation lifetime r, which is generally differentfrom rg [6] .
time of dynamic RAM’S all depend on the lifetime. Becatse The generation lifetime, determined by thermal emission pro-
the lifetime depends directly on foreign impurities and crys :a1 cesses, is very sensitive to the energy level of the dominant
defects, it is also frequently used as a process control measu.e. impurity or defect, while recombination is relatively insensi-
Among themanylifetimemeasurementtechniques,the tive to it. r, is usually measured on diode structures using the
pulsed MOS capacitor has found wide acceptance as a method reverse recovery or open circuit voltage decay methods or on
bulkmaterials using opticalmethods like photoconductive
Manuscript received June 3, 1983; revised October31,1983. The decay or surface photovoltage. The volume sampled by recom-
Arizona State University portion of this work was partially supported bination lifetime measurementtechniques is notunderthe
by the National Science Foundation under Grant ECS-82-12336. experimenter’s control because one of the dimensions in this
D. K. Schroder is with Arizona State University, Tempe, AZ 85287
J. D. Whitfield and C. J. Varker arewithMotorola,Inc.,Product volume is the minority-carrierdiffusion length, and this is a
Development Laboratory, SRDL, Phoenix, AZ 85008. material property.

.OO 0 1984 IEEE

001 8-9383/84/0400~0462$01