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Patterned electrode vertical field effect transistor: Theory and experiment

Article  in  Journal of Applied Physics · September 2011

DOI: 10.1063/1.3622291 · Source: IEEE Xplore

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 JOURNAL OF APPLIED PHYSICS 110, 044501 (2011)

Patterned electrode vertical field effect transistor: Theory and experiment

Ariel J. Ben-Sasson and Nir Tesslera)
Sarah and Moshe Zisapel Nano-Electronic Center, Department of Electrical Engineering, Technion - Israel
Institute of Technology, Haifa 3200, Israel
(Received 5 May 2011; accepted 16 June 2011; published online 16 August 2011)
We present a theoretical and experimental investigation of the recently reported new architecture
of a patterned electrode vertical field effect transistor (PE-VFET). The investigation focuses on the
role of the embedded source electrode architecture in the device behavior. Current-voltage
characteristics was unraveled through the use of a self-consistent numerical simulation resulting in
guidelines for the PE-VFET architecture regarding the On/Off current ratio, output current density,
and apparent threshold voltage. Current modulation characteristics are obtained through the
formation of virtual contacts at the PE nano-features (i.e., perforations) under gate bias, which lead
to the formation of vertical channels under drain bias. As the vertical channel is formed the device
characteristics change from contact-limited to space-charge-limited. The analytical model strength
is shown with the parameter extraction procedure applied to a measured PE-VFET device
fabricated using block copolymer lithography and with the appropriate simulation results. V C 2011

American Institute of Physics. [doi:10.1063/1.3622291]

I. INTRODUCTION length, width, and dielectric capacitance constitute most of

the device structural parameters. The key element in the
Organic field effect transistors (OFETs) attract consider-
VFET architecture is the source electrode structure, sand-
able interest, being flexible, low cost, and amenable to large
wiched between the gate and gate dielectric layers, on one
area fabrication techniques. They are expected to integrate
side, and the active layer and drain electrode, on the other.
into the growing variety of organic electrical products such
In 2004, Yang and coworkers have demonstrated a high
as flexible displays, sensors, and disposable devices with
performance device realized with an ultra-thin Al electrode,
moderate computing demands (e.g., radio frequency identifi-
stacked upon a high roughness dielectric layer, serving as the
cation tags). However, the inherent low mobility of the non-
source electrode.8 The effect is explained in Ref. 8 as follows:
crystalline active material, 3 to 6 orders of magnitudes lower
charge accumulation on the source/active-layer interface
than that of crystalline materials, results in low performance
determined by the Debye shielding length sets the charge
in terms of current output, On/Off ratio and modulation fre-
injection performance. In addition to having non-uniform
quency, which hinder the practical realization of these
thickness and partially oxidized composition, the short Debye
devices.
shielding length requires the gate dielectric to be a super high
Vertical field effect transistor (VFET) architecture with
capacitor, above 1 lF/cm2, limiting the device frequency per-
the drain and source electrodes vertically stacked enables the
formance. This approach was recently combined with the
reduction of channel length without substantial increase in
enhanced electric eouble layer (EDL) gate dielectric.9 Porous
cost or complexity of fabrication, and may compensate for
SiO2 fabricated by plasma enhanced chemical vapor deposi-
the low mobility. These thin film transistors (TFTs) can be
tion under certain conditions results in capacitance greater
categorized into two groups. The first group can be referred
than 1 lF/cm2.10 For the sake of comparison, thermally
to as semi-vertical devices, characterized with vertical fabri-
grown 150 nm SiO2 layer has a capacitance of 20nF/cm2.
cation but lateral structural configuration, i.e., the channel
Such structures can outperform lateral organic TFTs in terms
length is determined by the layers’ thickness but the gate is
of low voltage and high current density but are also inher-
still spatially located between the source and the drain elec-
ently limited to low frequency as the EDL dielectric is an
trodes.1–6 The drain and source electrodes are either in the
ion-based capacitor.11 A different approach for pure VFETs
same layer5,6 where the space is defined by surface topogra-
does not consider the source Debye shielding length but
phy, or in separate layers in which case the thickness of ei-
instead the source spatial structure which includes perfora-
ther the dielectric layer2–4 or the active layer1 defines the
tions, resulting in a planar metal grid structure (patterned
channel length. The second group is of “pure” VFETs where
electrode).12,13 The patterned electrode geometrical structure
the gate, source, and drain electrodes are stacked vertically.
lessens the source electrode screening effect, hence, super ca-
The current-voltage characteristics of these devices cannot
pacitance is not required and the theoretical frequency limit
be described simply by the lateral devices physical picture,
is dramatically reduced. The patterned electrode can take
i.e., the gradual channel approximation,7 where channel
forms other than a metallic grid. Porous electrode spin coated
from a dilute solution of single wall carbon nano tubes14–16
a)
Author to whom correspondence should be addressed. Electronic mail: results in a conductive network that serves as a conductive
[email protected]. porous layer. Lately, we have presented a facile fabrication

0021-8979/2011/110(4)/044501/12/$30.00 110, 044501-1 C 2011 American Institute of Physics

V

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 044501-2 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

method which results in a metallic Patterned Electrode Verti-

cal OFET (PE-VOFET) with perforations determined in size
and shape,12 yielding a complex electrode structure. PE-
VOFET is realized through patterning of the source electrode,
using polystyrene poly(methyl-methacrylate) block-copoly-
mer (BCP) self-assembled layer.17 The source patterning pro-
cess, obtained by transferring the BCP pattern to the metal
electrode, offers accurate control of the source composition,
architecture and dimensions. The freedom to select any con-
ductive source materials allows the fabrication of either n-
type or p-type transistors with various active layer materials.
In addition, fabrication of architecture with different struc-
tural dimensions opens the route for comprehensive investi-
gation of the device operation and its optimization.
The current work aims to present a comprehensive view
of the PE-VFET performance, based on numerical analysis.
Experimental measurements are presented to support the
simulation results. In Sec. II we describe the device architec-
ture and the structure we use for the simulation analysis. The
physical model and the method of its implementation are
specified in Sec. III. Based on the numerical analysis,
Sec. IV sheds light on the physical processes affecting the
device operation and presents analytical description for the FIG. 1. (Color online) Description of device architecture. (a) Illustration of
vertical 3D device ideal structure with a cylindrical active cell. (b) Simula-
device operation at On and Off states which are supported by tion 2D cross section of the device active cell with the layers notations.
experimental data. Section V attempts to clarify the influence
of the different structural parameters on device performance Fig. 1(a). The active cell is spatially comprised of a single
and provides structural optimization guidelines. perforation surrounded by the metallic source layer and
extends vertically to include all the layers.
II. DEVICE DESCRIPTION
III. MODEL DESCRIPTION
Similar to a lateral FET, the vertical type also includes a
dielectric layer sandwiched between the gate electrode and A. Physical picture
the active layer. However, in the VFET the active layer is Having the explicit description of the device geometrical
sandwiched also between the source and the drain electrodes. structure, we now provide the physical picture within which
The device structure comprises of five layers stacked one we describe the device operation. The model takes into
upon the other: The bottom gate which could be highly account drift and diffusion of charge carriers and the effect
doped silicon wafer, the dielectric layer (as thermally grown of space charge on the electric field in the device. Unique
oxide layer), the source electrode (SE) with the grid shaped properties of organic semiconductors are not accounted for
metallic structure, the semi conductive (active) layer, and the in the present model; among these are the generalized Ein-
drain as the top electrode. The device ideal structure pre- stein relation19 and the field dependent mobility.20 The basic
sented in Fig. 1(a) shows a SE layer having a periodic struc- equations used for the simulation are described below. Equa-
ture with identical circular shaped perforations. This tion (1) is the 2D Poisson equation relating the potential
structure is somewhat justified by the fabrication method shape to the device geometrical structure, through the bound-
based on BCP self-assembly18 which determines the perfora- ary conditions, and to the charge density distribution
tions size and shape.  2 
In this paper, we will use the following definitions for @ wðx; zÞ @ 2 wðx; zÞ q
þ ¼ ½nðx; zÞ  pðx; zÞ; (1)
the structural parameters. The distance between the source @x2 @z2 eðx; zÞe0
and drain electrodes determined by the active layer thickness
defines the channel length, L. The vertical FET area, A, is where q, e, and e0 are the elementary charge, the vacuum per-
determined by the overlap between the gate, source, and mittivity and the relative permittivity, respectively. n and p
drain electrodes. D is defined as the perforation diameter, are the electron and hole density values. For the sake of con-
and the Fill Factor value, FF, is defined as the ratio between venience, the spatial notations are dropped in the following
the sum of the perforations area to A. hd and hs are the dielec- sets of equations. Charge conservation is applied through the
tric thickness and the SE thickness, respectively. Finally, the current continuity equations [Eq. (2)] for electrons and holes
contacts potential, ub0, is defined as the difference between 8
the electrodes work functions and the active layer LUMO/ >
> ! @n
<ðaÞ div J n  q ¼ qR;
HOMO levels. Figure 1(b) presents a 2D cross section uti- @t (2)
lized by the numerical simulation. The cross section provides >
> ! @p
:ðbÞ div J p þ q ¼ qR;
a side view of the device single active cell as indicated on @t

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 044501-3 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

where Jn, Jp, and R are the electrons current density, the holes Furthermore, the commonly used formula for the image
current density, and the recombination rate, respectively. Equa- potential21–23 was developed for the case of a charge next to
tion (3) are the drift diffusion equations for electrons and holes an infinite metal plane. This case is very different than the sce-
describing the relation between the current density and both the nario at the perforations (gap) where the metal surface extends
charge distribution and the potential shape vertically only few nm, a case in which the influence of the
( ! ! image potential is reduced in size.24 The boundary conditions
ðaÞ J n ¼ qnln E n þ qDn grad ðnÞ; at the sides (x ¼ 0 and x ¼ 160 nm in Fig. 1) are described by
! ! (3)
ðbÞ J p ¼ qplp E p  qDp grad ð pÞ; cyclic boundary conditions. The insulating interface between
the dielectric layer and the active layer, at the bottom of the
where ln, lp, Dn, and Dp are the mobility and diffusion coef- perforation, is assumed to be free of surface charges and with
ficients for electrons and holes, respectively. The ratio zero vertical current.
between the diffusion and mobility is taken to be given by
the classical Einstein relation Di/li ¼ kBT/q, where kB and T
C. Numerical method and parameters
are the Boltzmann constant and the temperature, respec-
tively. Using Eq. (3) and assuming steady state conditions The model assumes initial condition of charge neutrality
(@n/@t ¼ 0 and @p/@t ¼ 0) and zero generation/recombina- to implicitly obtain the potential shape [Eq. (1)]. The implicit
tion, Eq. (2) are reduced to solution of Eqs. (4a) and (4b) incorporates the Scharfetter-
8 Gummel method.25 The method calculates the current values
   
>
> @ @w @n @ @w @n in the middle of each mesh interval under the approximations
> ð
< @xaÞ nl n þ D n þ nl n þ D n ¼ 0;
@x @x @z @z @z that electric field, mobility, and diffusion coefficients are
    fixed in the entire interval. The electrons and holes currents
>
> @ @w @p @ @w @p
>ðbÞ
: nlp þ Dp þ plp þ Dp ¼ 0: at a mid-interval point along the x axis are
@x @x @x @z @z @z
8
(4) > qDn  x x

>
>ðaÞ J 1 ¼ Dh Bð ti Þniþ1;j  Bð ti Þni;j ;
>
< n;iþ ;j
B. Boundary conditions 2
qDp   (7)
Obtaining a unique solution using the set of differential >
>ð bÞ J ¼ B ð x
t Þp þ Bð  x
t Þp ;
>
> 1 i iþ1;j i i;j
: Dh
Eqs. (1) and (4) requires the carriers density and the potential p;iþ ;j
2
value to be specified at the boundaries. For the device struc-
ture used, the potential shape is solved for the entire device where i and j are the calculation point indices along the x and z
but the carriers density distributions are solved solely in the axis, respectively, Dh is the interval length, B is the Bernoulli
active layer, introducing boundary conditions spatially function B(t) ¼ t/(et1) and xti is given by xti ¼ (lnExiþ1/2,jDh)/
located interior to the device. These boundary conditions are Dn (where x denotes the measured field direction).
located at the interfaces between the active layer and the Convergence to the steady state solution is obtained using
source/drain electrodes and the dielectric layer, at the bottom iterative method.26 The iteration solves first the continuity equa-
of the perforation. The boundary conditions at the electrodes tion with damping factor to ensure numerical stability, then the
determine the potential value on their surface through the Poisson equation is solved, and finally the boundary conditions
applied bias (VG, VD, and VS ¼ 0) and the contact potential, are updated.27 The finite element method is realized using fixed
ub0, between each electrode and the active layer. We consid- mesh increments of 1 nm to both the x and z axis, similar to the
ered the electrodes to have infinitely short Debye length and molecular distance of crystalline fullerene, the material of
hence fixed work function value regardless of the applied choice for the active layer of the reference measured devices.28
electric field. The electrons/holes charge density in the inter- The shape and location of the different layers is presented in
face is assumed to be in equilibrium with the electrodes,21 Fig. 1(b). The typical dimensions used for the following investi-
  gation are hd ¼ 50 nm, hs ¼ 5 nm, L ¼ 100 nm, Xwidth ¼ 160
qub
n ¼ N0 exp  ; (5) nm, D ¼ 60 nm, FF ¼ D/Xwidth ¼ 37.5%, and ub0 ¼ 0.6 eV (the
kB T barrier between the source and the active layer LUMO level).
where N0 is the density of states in the active layer. ub is the Single carrier type is assumed and we solve only for electrons
energetic potential barrier determined by (will be justified in Sec. IVA).

ub ¼ ub0  Du ¼ ub0  DxE? ; (6) IV. OPERATION DESCRIPTION

where E? is the electric field perpendicular to the interface In this section, we use the numerical simulations to pro-
and Dx is the distance between the metal surface to the first duce the distribution of the various quantities (charge carrier
site at the active layer (taken to be the intermolecular spacing density, potential, and current) and to provide some insight and
of 1 nm, the mesh increment in the simulation). We note understanding of the operation of such vertical FET structure.
that the image potential influence here, obtained through the
solution of the 2D Poisson equation in the vicinity of the elec-
A. Potential surface
trodes BCs, is only partially considered. The solution, being
based on charge densities substantially, lessens the image As was briefly described in Ref. 12, the device operation
potential magnitude rendering the phenomena insignificant. relies on the gate potential inducing electric fields which pull

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 044501-4 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

the charges out of the SE and into the perforation area (i.e., The electric fields quiver plot shown in Fig. 3(b) demon-
gap) such that a virtual contact is created. To understand the strates the electric field magnitude and direction in the region
device operation in more detail, one has first to follow the close to the perforation edge. We distinguish between the
potential lines in such a device and their dependence on the side and upper interfaces of the SE with the active layer and
structural parameters. We first consider the device without refer to them as the source lateral facets and the source top
any injected charges present. In a non-patterned source con- facet, respectively. Modifying the gate potential, non-homo-
figuration, the potential shape would have been very simple, geneously varies the electric field applied to the SE surfaces.
comprising two flat surfaces, one between the gate and the Examining the electric field values close to the interface we
source, and the other between the source and the drain find that the maximum increase in the electric field is at the
(dashed line in Fig. 2). When the source electrode is com- bottom of the lateral facets and it lessens as one moves away
pletely removed only one flat surface exists between the gate from the dielectric surface. Furthermore, the electric field
and the drain (dotted line in Fig. 2). The perforated electrode over the source top facet is negligibly affected by the gate,
shape is a mix of both cases, resulting in a complex potential indicating that the gate’s main role is in varying the injection
surface. The solid line in Fig. 2 shows the potential spatially properties of the source lateral facets. More insight is gained
located at the perforation center and along the vertical axis. through analytical Laplace model developed based on the
The difference between the dotted and solid lines indicates numerical simulation results (see the Appendix). As is shown
the existence of lateral electric fields concentrated at the area in the Appendix, most of the charge injection (extraction
of the perforations. The arrow in Fig. 2 indicates the point at from the SE) at the On state takes place at the bottom of the
which the electric field, at the center of the gap, changes sign perforations’ lateral facets in close proximity to the dielectric
and starts to pull electrons toward the drain electrode. We surface.
term this point as “inversion point” and as we will show, its
position is affected by the source electrode thickness and it B. Charge carrier concentration
influences device performance. We elaborate on the inver-
Charge carrier concentrations are presented in Fig. 4.
sion point in Sec. IV B.
Simulation results are obtained for a device with the same
The shape of the potential surface with the same biasing
structural parameters as in Fig. 4 and for biasing conditions
conditions as in Fig. 2 solved by the numerical simulation is
of VG ¼ 5 V, VD ¼ 2 V, and VS ¼ 0 V. Figure 4 omits the gate
presented in Fig. 3(a). Figure 3(a) shows that for the vertical
electrode and gate dielectric layers as they do not participate
configuration the gate effect is restricted to the close proxim-
in charge carrier conduction. The charge extracted from the
ity of the source perforations and specifically it does not affect
the drain electrode injection properties. Therefore, injection
through the drain would contribute only to the device leakage
current and hence, its injection properties have to be mini-
mized through judicious choice of the electrode material. The
above leads to the conclusion that an optimized vertical device
is of single carrier type, as considered in the numerical model.

FIG. 2. (Color online) Schematic description of the potential distribution in FIG. 3. (Color online) (a) Potential surface shape in an active device with
a device empty of charges with VG ¼ 2 V, VS ¼ 0 V, VD ¼ 5 V. Dotted line structural parameters of D ¼ 60 nm, FF ¼ 37.5%, hd ¼ 50 nm, hs ¼ 6 nm,
represents a structure with the SE removed. Solid line represents a structure ub0 ¼ 0.6 eV, and L ¼ 100 nm, and biasing conditions: VG ¼ 2 V, VS ¼ 0 V,
with a gap size of 60 nm and SE thickness of 5 nm (vertical arrow denotes VD ¼ 5 V. The vertical white arrow denotes the point at which the electric
the point at which the electric fields start to pull electrons toward the drain). field, at the center of the gap, starts to pull electrons toward the drain. (b)
Dashed line represents the potential outside the perforated region. Electric field quiver plot focused on the area of the gap edge.

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 044501-5 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

lateral perforation facets by the lateral electric fields accu- On current would occur solely at the gap from the source lateral
mulates within the perforation at the dielectric interface, facets. As the charge that accumulates in the gap can flow only
forming the virtual contact which is the origin of the vertical in the vertical direction one would expect a vertical channel to
channel. Figure 4 shows that indeed the vertical channel is extend from the gap to the drain electrode (see Fig. 4). In this
located above the source perforation. The experienced reader scenario one can separate the device into two different func-
may note that the shape of the charge density resembles that tional regions. The region between the dielectric (in the gap)
found in space charge limited diode. We will revisit this ob- and the drain can be referred to as the On region (the channel)
servation later in the text. while the region above the SE top facet can be referred to as
the Off (or “leakage”) region.
1. The inversion point The device current density quiver plot, at active state (after
channel formation), is shown in Fig. 5. The arrows denoting the
The details of the shape of the vertical channel do not current are overlaid on top of the charge concentration contour
depend only on the fields within the perforation but also on (shown in Fig. 4) for better orientation. Direction of electrons
the vertical electric fields in the active layer and particularly flow is indicated with arrows, the length of which is logarithmi-
above the perforation area. Unlike the lateral electric fields, cally scaled with the current density (note that the vertical and
the vertical ones projected by the gate and drain electrodes horizontal axes are not to scale). The carriers’ path is initially in
are opposite in direction. This effect led to the convex horizontal direction from the gap edges to the gap center. Its
shaped potential line along the device vertical axis (Fig. 2, density is at its maximum in close proximity to the dielectric
solid line), indicating that the vertical electric fields direction interface and reduces fast as the distance from the dielectric
switches along this line. The spatial location of this turning layer increases. The current then turns to the vertical direction,
point which we refer to as the inversion point is a function of driven initially by diffusion forces and kept at the center of the
the device structural parameters and the biasing conditions. perforation due to the lateral electric fields exerted by the perfo-
Determining the inversion point spatial location and its ration facets. As Fig. 5 shows, the current initially flows
potential cannot be done analytically with Laplace interpre- through a very short “tunnel” the length of which is determined
tation as the high charge accumulation significantly alters by the SE thickness. The effect of this “tunnel” will be dis-
the shape of the potential at the vertical channel area. The cussed later in the text.
vertical electric fields between the insulator surface, the ori-
gin of the accumulation, and the inversion point are in direc-
tion opposite to that applied by the drain. Therefore, the D. Channel width (W)
charge concentration at the inversion point is actually driving It is common to associate the channel width with the
the rest (upper part) of the vertical channel. The spatial dis- length of the injecting contacts. In the PE-VFET architec-
tance and the related potential difference between the dielec- ture, the channel width would thus be measured by summing
tric layer and the inversion point determine the charge the length of all the SE lateral facets. This value could be
density at that point with the potential difference acting as an assessed analytically assuming the perforation (gap) takes ei-
effective barrier. Namely, the properties of the inversion ther ideal circular or striped shape
point (location/potential) affect the resulting current density
8
where a shorter distance would imply higher current. > 2FF  A
<ðaÞ Winterfacestriped ¼ ;
D (8)
C. Current flow >
:ðbÞ W 4FF  A
interfacecircular ¼ :
D
As the influence of the gate over the source electrode top
facet is negligible the varying charge injection attributed to the Using the previously mentioned BCP fabrication method the
perforation diameter is roughly 60 nm and the FF is around

FIG. 4. (Color online) Charge concentration distribution, logarithmic scale, FIG. 5. (Color online) Current density quiver plot overlaid on top of the
for a device with structural parameters of D ¼ 60 nm, FF ¼ 37.5%, hd ¼ 50 charge concentration contour for a device with structural parameters similar
nm, hs ¼ 6 nm, ub0 ¼ 0.6 eV. and L ¼ 100 nm, and biasing conditions: to those in Fig. 4 and biasing conditions: VG ¼ 3 V, VS ¼ 0 V, VD ¼ 2 V.
VG ¼ 5 V, VS ¼ 0 V, VD ¼ 2 V. Arrow size is logarithmically scaled with the current density.

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 044501-6 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

30%. For a device in total area of 10 mm2, the channel width Output curves of measured devices at On and Off states
value is between 100 to 200 m according to Eqs. (8a) and (8b), are shown in Fig. 6(a) and Fig. 6(b) (circles), respectively.
respectively. For the sake of comparison, lateral devices fabri- Curve fitting at On state (SCL regime) based on Eq. (10) is
cated with lithographic resolution of 1 lm occupying the same shown in Fig. 6(a) (solid line). The curve fitting for contact
surface area have approximately 3 mm channel width, five limited regime (Off state) based on Eq. (9) is shown in Fig.
orders of magnitude smaller. The large channel width at the 6(b) (solid line). For this fit, shown in Eq. (12), we use the
vertical device indicates that these interfaces would not consti- image force barrier lowering described in Eq. (11).23
tute a bottleneck for the current-voltage behavior in the active rffiffiffiffiffiffiffiffiffiffiffi
state. qE?
ub ¼ ub0  Du ¼ ub0  ; (11)
4pe0 e
E. On and Off states   rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
q qVDS
General device behavior can be deduced using the fol- JOff ¼ qln N0 exp  ub0 
kT 4pe0 eLOff
lowing three observations: First, the On current originates
VDS
only from the perforations area. Second, the Off current orig-  ð1  FFÞ: (12)
inates solely from the rest of the SE (i.e., top surface). Third, LOff
the channel width is large and hence does not constitute a We use E? ¼ [VDS/LOff] assuming that in the regions outside
bottleneck for the current voltage behavior in active state. the perforation area, between the source and the drain, the
Following the above observations we consider two limiting electric field is constant due to low charge concentration at
cases for the current regimes. In the first limiting case, when CL regime.
the device is at Off state, charges are extracted to the active Fitting coefficients values extracted from the device char-
layer only due to applied drain-source voltage. In this config- acteristics shown in Fig. 6 are detailed in Table I, where the first
uration the similarity to a diode structure is obvious and we two coefficients are ascribed to the Off state measurement and
expect Contact Limited (CL) behavior which is described by the third coefficient is ascribed to the On state measurement.
Eq. (9), Device parameters (detailed in Table II) are then deter-
 qu mined as follows. Effective channel length is determined first
JOff ¼ qln N0 E? exp  b ð1  FFÞ; (9) through coefficient #2, mobility is determined through coef-
kT
ficient #3 and potential barrier is determined through coeffi-
E? is the perpendicular electric field applied to the SE top cient #1 (we assume the mobility at CL and SCL regimes is
facet, LOff is the Off Channel length (the distance between unchanged and L  LOff).
the SE top facet and the drain electrode), and the (1-FF) fac-
tor accounts for the Off current originating from only part of
the device area (SE top surface). The second limiting case
occurs when the device is at the On state and charges are
extracted from the source electrode by the gate and accumu-
late at the perforations. The large accumulation of charges at
the dielectric interface in the source perforations creates the
virtual contact and if the density is sufficiently high it will
act as an “infinite” charge reservoir as would be the case for
an ohmic contact. In that case, space charge limited current
(SCLC) regime is expected where the device behaves
according to Eq. (10)20,21,29 and the (FF) factor accounts for
the On current originating only from the perforations area.

9 V2
JOn ¼ e0 eln DS FF: (10)
8 L3
These two limiting cases are best observed when measuring
the device output characteristics, sweeping the drain poten-
tial while the gate is either closed (Off state ¼ gate source
bias is negative with respect to the drain source bias) or fully
open (|VGS|  |VDS|). To illustrate the strength of these
observations we show below a parameter extraction proce-
dure applied to a measured PE-VFET device. We note that
the Gate potential values at the experimental part (VG ¼ 40
V) are higher than those in the theoretical part (VG  10 V)
primarily due to geometrical differences. In this context, the FIG. 6. (Color online) Output characteristics for experimental measure-
most relevant feature is the dielectric thickness which is ments (circles) and simulation results (triangles). Fitting curves indicated
with solid lines. (a) Device at On state, VG ¼ 40 V. (b) Device at Off state,
equal to 100 nm in the experimental part and 50 nm in the VG ¼ 5V. Dashed line is the calculated curve based on Eq. (9) for a device
theoretical part (see Fig. 14). with no potential barrier lowering due to image potential.

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 044501-7 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

TABLE I. Experimental fitting parameters describing the CL and the SCL is performed with numerical tools and provides more accu-
regimes obtained based on Eqs. (10) and (12). rate understanding regarding device behavior as well as
structural optimization tools. Structural features are investi-
(#) Parameter Exp. fit
gated one by one focusing mainly on parameters unique to
CL (1) qlnN0(1-FF)/LOffX
1.99  106
the PE-VFET architecture. Device performance is analyzed
Exp[q ub0/(kT)] in the context of On/Off current ratio, output current, thresh-
(2) q/(kT)X(q/(4pee0LOff))0.5 1.306 old voltage and Subthreshold Swing (SS). We note that for
SCL (3) 9/8Xee0lnFF/L3 9.5  103 disordered organic transistor operating in accumulation re-
gime, the threshold voltage serves as a fitting parameter31,32
We note that Leff is found to be smaller than the nominal associated with the formation of the virtual contact.
evaporated layer thickness and we attribute it to the film surface
A. Source electrode thickness
morphology characterized with irregular stacking of crystal
grains formed when C60 film is grown on various surfaces even Figure 7(a) shows the transfer characteristics of simu-
at room temperature.30 We also note that the FF parameter is lated devices with source electrode thickness (hs) varying
evaluated prior to device fabrication based on Atomic Force between 2 to 50 nm. Other structural parameters are kept
Microscopy measurement by summing up the perforations area constant and are the same as those of the previous section.
at the SE. However, the effective FF value is smaller than the Specifically, the distance between the SE top surface and the
“physical” one due to the “tunnel” effect rendering only part of drain electrode is kept constant and hence the current density
the perforation area active. The difference between the effective at zero gate bias remains constant. As Fig. 7(a) shows,
and “physical” FF was demonstrated using the simulation (not increasing the source electrode thickness leads to perform-
shown here) and its size is a factor of structural parameters, i.e., ance degradation: SS value increases from 1.3 V/decade for
perforation height and diameter. In the above applied parameter 2 nm thick SE to 4.8 V/decade for 50 nm thick SE; threshold
extraction procedure, the error associated with the FF value voltage increases; On/Off ratio, measured at VG ¼ 10 V and
was not taken into consideration hence the mobility value VG ¼ 0 V, reduces by three orders of magnitudes along with
extracted based on coefficient #3 is underestimated. the On current output. Figure 7(b) shows the On/Off ratio as
Using the parameters detailed in Table II we performed a a function of hs and we note the functional form is close to
simulation run, the results of which are presented in Fig. 6 (tri- exponential. Deviation from the exponential dependence
angles). The output characteristics describing the On state [Fig. occurs for ultra-thin (hs < 5 nm) and relatively thick (hs > 40
6(a)] are similar to the measured device’s ones; however, at Off nm) SE. This behavior can be explained by examining the
state [Fig. 6(b)] the simulation predicts lower current density role of hs in determining the properties of the inversion point
than measured experimentally. This deviation mainly originates (location/potential) relative to those at the insulator interface
from the lack of the image potential barrier lowering not which is the On channel origin.
accounted for in the simulation. The dashed line in Fig. 6(b) is
a calculation of Eq. (9), using Eq. (6) for the barrier height,
based on the parameters described in Table II. This calculation
shows that indeed the deviation at the Off state between the
simulation and the measured data is largely due to the exclusion
of the image force barrier lowering at the top surface of the
source electrode.

V. ROLE OF STRUCTURAL PARAMETERS

The following section analyzes the coupling between
structural parameters and device performance. The analysis

TABLE II. Experimental parameters obtained for PE-VOFET with fuller-

ene (C60) active layer.

Parameter Value

ln[cm2/Vs] 1.7  103a

N0[cm3] 1.44  1021c
T[ K] 300
Leff[nm] 315a
ub0[eV] 0.57a
FF 0.45b
e 4c
FIG. 7. (Color online) (a) Transfer characteristics of devices with varying hs
a
Extracted from the fitting coefficients at Table I. values and fixed Off channel length (100 nm) with VD ¼ 3 V. (b) On/Off ra-
b
Atomic force microscopy measurement prior to device fabrication. tio vs SE thickness. (c) On/Off ratio vs potential barrier height at the inver-
c
Based on literature.28 sion point.

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 044501-8 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

The simulations show that as hs increases, the distance

between the inversion point and the dielectric interface also
increases. Actually, if we plot Fig. 7(b) as a function of the
distance between the inversion point and the dielectric inter-
face, instead of the SE thickness, the exponential relation is
even more pronounced (not shown here). This observation
led us to plot at Fig. 7(c) the On/Off ratio as a function of the
potential difference between the inversion point at the center
of the perforation and the dielectric interface (uBeff). The
almost perfect exponential fit indicates that the inversion
point displays an effective potential barrier to charge injec-
tion from the virtual contact into the upper part of the verti-
cal channel. This observation, along with the results shown
in Fig. 5, indicate that the charge flow between the dielectric
interface and the inversion point is, to a good approximation,
one dimensional.
We conclude that the device operational mechanism
includes two barriers. The first, between the SE and the
active layer (contacts barrier), is determined by the choice of FIG. 8. (Color online) Numerical and analytical Off current density compari-
materials and is either gate-controlled at the lateral facets or son for devices with varying FF or D values. Rectangles: non-biased gate. Tri-
angles: reversibly biased gate. Solid line: analytical curve according to Eq. (9).
drain-controlled at the top facet. The second, the inversion
point barrier, is located inside the active layer.
1. The unit cell length, Xwidth, is kept constant and D is var-
1. The inversion point and the tunnel effect ied (FF changes accordingly and in the 2D simulation it
means: FF ¼ D/Xwidth);
One of the implications of the inversion point is that at
2. The perforation size (D) is kept constant and the FF is
this point the diffusion-controlled current flowing toward the
varied (unit cell length changes accordingly);
drain becomes drift-controlled. As can be seen in Ref. 33,
3. The FF is kept constant and D is varied (unit cell length
Fig. 6(b), this situation is found in every space charge limited
changes accordingly).
device. The other effect illustrated in the same paper
[Fig. 6(a)] is that the charge density drops exponentially In set #1 (Figs. 8 and 9), D and FF are linearly proportional
between the contact and the point at which the electric field while the device unit cell size is constant (Xwidth ¼ 160 nm as in
changes sign. In a standard SCLC diode the position of the Fig. 1). The FF value varies between 0.1 and 0.9 together with
inversion point would depend largely on the charge density at the gap size (D) which varies accordingly, between 16 and
the contact interface, which in our case translates to the charge 144 nm. Figure 8 shows the current density for devices biased
density accumulated at the dielectric interface (the virtual con- at VDS ¼ 2 V and VGS ¼ 0 V (rectangles) or VGS ¼ 2 V (trian-
tact), and slightly also on the diode bias. In the current struc- gles) as a function of the FF (or D) value. As was discussed ear-
ture, however, the current starts its flow between two source lier, the current flowing from the source may originate either
facets (see Fig. 5) which are of constant potential (generally from the lateral facets of the perforations or from the top surface
zero). Such a “tunnel” with equipotential walls acts to prevent of the electrode. As the FF increases, the area of the top surface
the electric field at the vicinity of the walls from changing decreases and hence the increase in current for the case where
sign before the “tunnel” ends. Closer to the center of the gap VG ¼ 0 V (rectangles) has to be associated with the lateral fac-
(“tunnel”), the effect would be weaker but still the inversion ets. Close examination of the simulation outputs reveals that
point would move toward the drain as the thickness of the there is a more effective barrier lowering at the lateral facets for
source electrode increases. Since the charge density would larger D values. The lower curve for VG ¼2V (triangles)
decay exponentially toward the inversion point, the farther the decreases linearly, indicating that the reverse-biased gate elec-
inversion point, the lower the density that is supplied to the trode eliminates the current flow from the lateral facets, leaving
upper part of the channel that is governed by the drift current. only the top surface as the origin for charges. Therefore, in this
As mentioned above, the effect of the inversion point position device configuration, measurements of drain-source leakage
on the device performance (On current and On/Off ratio) is currents, as described in Eq. (9), are obtained only when the
very strong [Fig. 7(b)]. Namely, due to the “tunnel” effect it is gate is oppositely biased to the drain electrode (Fig. 8, solid
important that the source electrode is thin enough (<5 nm) for line). Under these conditions, when the injection from the lat-
the device to exhibit best performance. eral facets (into the gap) is completely suppressed, the Off cur-
rent originates solely from the SE top facet. The Off current
B. Perforation size and FF value decreases linearly with FF value (triangles) and is linearly
proportional to the top surface area.
In this section, we investigate the role of perforation Transfer characteristics of the same set are shown in
(gap) size, D, and the FF value by performing three simula- Fig. 9 and exhibit a strong dependence on FF and D values.
tion sets: Varying the gap size (D) and the FF results with On/Off ratio

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 044501-9 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

Figure 10 displays a slight increase in the Off current den-

sity with unit cell length which is observed at the onset of the
transfer characteristics, in agreement with Eqs. (9) and (13b).
Similarly a decrease in the On current density with unit cell
size is shown as the density of the active sites (FF) is reduced.
A complete agreement between the analytical Eq. (13c) and the
numerical On/Off performance is shown at the inset to Fig. 10
marked with line and dots, respectively. Note that SS value
remains similar for the entire set.
Set #3 is comprised of devices with constant FF value,
and D values varying proportionally with unit cell length.
Figure 11 presents the transfer characteristics where the onset
displays similar Off current density for all devices, validating
the constant FF value, according to Eq. (9). The On current,
on the other hand, increases approximately linearly with
increasing unit cell length (Fig. 11 inset). This increase is pro-
portional to the increase in D, despite the constant value of the
FF. This is again due to the “tunnel” effect and the associated
barrier discussed previously. For a constant SE thickness the
FIG. 9. (Color online) Transfer characteristics for devices with varying
FF(D) values. Inset: On/Off performance as a function of FF(D) value. “tunnel” effect would reduce as D increases (see discussion of
the inversion point in the context of Figs. 7 and 9).
increased by over three orders of magnitude with the On cur-
rent taken at VG ¼ 10 V and the Off current at VG ¼ 2 V. C. Injection barrier height
The SS varies between 3.2 V/decade for D ¼ 16 nm to 1.3 V/
As could be deduced from Sec. IV E, the device per-
decade for D ¼ 144 nm. The inset to Fig. 9 presents the On/
formance is dependent on the potential barrier height for
Off performance as a function of D (FF). Examining this
charge injection from the SE to the active layer (constituting
inset together with Fig. 7(b), the effect can be intuitively
the Schottky barrier). For the following calculations, we use
explained by referring to the perforation relative dimensions
a medium level type of fixed parameters and vary the barrier
or the “tunnel” effect. Thicker electrode and smaller gap size
between the source electrode and the active layer. The fixed
result in a more pronounced “tunnel” structure which
parameters are D ¼ 60, Xwidth ¼ 160, hs ¼ 6, and hD ¼ 50 nm.
reduces the device performance, and vice versa (see discus-
Figure 12 shows the transfer characteristics for several
sions in Secs. V A 1 and IV B 1).
injection barrier heights. As expected, the Off current (trans-
Set #2, shown in Fig. 10, is comprised of devices with
fer characteristics at negative gate bias) reduces exponen-
fixed D and varying unit cell length (Xwidth). Hence, FF val-
tially with the barrier height. In Sec. IV E, we stated that the
ues are inversely proportional to the latter. Based on the dis-
On current obtained for |VGS|  |VDS| is independent of this
cussions above, the current at On state originates mainly
injection barrier as the high gate bias would diminish this
from the perforation, which in this set is of constant size, and
barrier through the field induced barrier lowering. However,
the Off current originates from the top surface of the source
electrode. This implies that the relation between the currents
at the On or Off states of the devices in this set can be
described using purely geometrical factors,
8
> Xwidth 2
>
> ðaÞ JOn ðXwidth 1 Þ¼ JOn ðXwidth 2 Þ;
>
> X
>
< width 1  
Xwidth 2 Xwidth 1 D
ðbÞ IOff ðXwidth 1 Þ¼ IOff ðXwidth 2 Þ;
>
> Xwidth
 2 D  Xwidth 1
>
> Xwidth 2 D
>
>
:ðcÞ On=Off ðXwidth 1 Þ¼ On=Off ðXwidth 2 Þ;
Xwidth 1 D
(13)

where Xwidth_1 and Xwidth_2 are the unit cell length of two dif-
ferent devices. Equation (13a) shows that the current per unit
cell is fixed due to the constant perforation size and the cur-
rent density reduces as the size of the unit cell increases.
Equation (13b) shows that due to the increase in the area of
the SE top surface, the current density at the Off state will
FIG. 10. (Color online) Transfer characteristics for devices with varying
slightly increase. These two equations lead to the On/Off ra- unit cell size (Xwidth in Fig. 1(b) and constant D (38 nm). Inset: On/Off ratio
tio decreasing as a function of the unit cell length (D being vs FF, numerical (dots) and analytical (solid line) evaluations according to
fixed and FF decreasing), as indicated by Eq. (13c). [Eq. (13c)], in linear plot.

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 044501-10 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

FIG. 13. (Color online) Layered SE devices transfer characteristics with

fixed bottom layer potential barrier equal to 0.6 eV and varying potential
FIG. 11. (Color online) Transfer characteristics for varying unit cell size barrier at the top layer as indicated in the plot. Inset: On/Off performance
devices with fixed FF value. The inset shows linear dependence between comparison between the uniform (hollow circles) and non-uniform (full
perforation gap size and On/Off performance. circles) SE structures having the same barrier at their top facet.

Fig. 12 shows that as the barrier increases, the gate bias lations a potential barrier of 0.6 eV for the bottom layer and
required to diminish its effect becomes larger. Hence, for the varied the upper layer potential barrier between 0.6 and 1 eV
VG range used in Fig. 12, a full virtual contact is not obtained (see Fig. 13). As anticipated, the Off currents are reduced with
for the samples with potential barrier of 0.7 eV and above. increasing top facet potential barrier while the On currents
As a result, in the simulated range, the increase in the On/ and threshold values remain approximately fixed. The On/Off
Off performance (inset in Fig. 12) is accompanied by a performance comparison between the uniform (hollow circles)
reduction in the On current. and layered (full circles) SE structures is presented in the inset
To improve the properties of the source electrode one of Fig. 13 where the potential barrier at the bottom layer is
could make use of the fact that the origins of the On and Off fixed and equal to 0.6 eV and at the upper layer varies
channels are spatially separated. This can be manifested if a between 0.6 to 1.2 eV. Not only is better On/Off performance
higher potential barrier is exhibited at the SE top facet (the or- obtained for the layered structure, but also the On current
igin of the Off channel) and a lower potential barrier is pre- remains almost unchanged.
sented at the SE lateral facets (the origin of the On channel).
Knowing that the On current originated mainly from the bot- D. Dielectric thickness (hD)
tom of the lateral facet, in proximity to the dielectric interface,
Scaling down of the dielectric thickness (hD) has the
allows suggesting a practical solution where the SE would be
obvious attribute of lowering the gate voltage required to
composed of two layers (i.e., layered structure). The bottom
switch the transistor on. The other effect is of reshaping the
layer provides the lateral facets injection properties and the
field lines as the bias is applied across the insulator. In lateral
upper layer provides the top facet injection properties. The
FETs this reshaping through downscaling of the insulator
transfer characteristics of such devices are presented in
thickness is associated with the gradual channel approximation
Fig. 13. Since Fig. 12 shows that up to about 0.5–0.6 eV the
where optimal performance requires that L (channel length) is
maximum current is not highly affected, we used for the simu-

FIG. 12. (Color online) Transfer characteristics for devices with varying
SE-active layer potential barrier height. Inset: On/Off performance vs barrier
height. FIG. 14. (Color online) Transfer characteristics for devices with varying hD.

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 044501-11 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

at least 1.5 times the length of hD (i.e., hD:L ratio of 1:1.5) and, vertical direction and by the perforation lateral edges in the
in some cases, 5 times as much.34,35 The scaling in the case of lateral direction. Equation (A1) is the Laplace equation form
the vertical transistor configuration is rather associated with for a rectangular space with normalized variables,
the “tunnel” effect discussed earlier. If the “tunnel” effect is
the dominant one for this scaling of the dielectric thickness 1 1
u þ 2 u ¼ 0; (A1)
then the ratio to be kept is that of hD:D. Transfer characteristics D2 h
presented in Fig. 14 demonstrate the behavior of devices with
varying hD. Comparing the results of Fig. 9 with those pre- where D and h are the perforation diameter and the device
sented in Fig. 14, we find that the effect of increasing the per- total thickness, respectively. The boundary conditions (BC)
foration size (D) is similar to that of reducing the dielectric along the upper and lower interfaces are those of equipoten-
thickness (hD), showing that indeed for a well behaved device tial surface and refer to the drain and gate electrodes, respec-
the scaling to be considered is of hD:D and the ratio is to be tively. The lateral BCs are symmetrical but more complex,
larger than 1:3. separated into three different regions which represent the
potential at the dielectric layer, the source electrode and the
VI. SUMMARY active layer. Based on the numerical results a linearly vary-
ing potential value is assumed both between the gate and
The operation of the PE-VFET was analyzed in the physi- source electrodes and between the source and drain electro-
cal framework of semiconductor basic transport equations, des, as illustrated in Fig. 2 (dashed line). The potential sur-
realized with a 2D numerical simulation. We have discussed face is given by Eq. (A2) as an infinite series,
the non-symmetrical VFET structure regarding the source and
drain electrodes and the role of the SE architecture in the for- X  2
2 1
mation of the virtual contact and, in turn, in the formation of uðx; zÞ ¼ sinðnpzÞ  
the vertical channel. The device current behavior was shown n
D np
sinh np
to follow the SCL- and CL-regimes, with minor modifications h
   
[Eqs. (10) and (9)], at On and Off states, respectively. This VS  VG VD  VS
 ½sinðnphd Þ 
behavior was theoretically examined versus the 2D simulation hd 1  hd  hS
and experimentally verified. Under the assumption of zero   
D
Debye shielding length, the On channel is formed solely at the  sin½npðhd þ hs Þg sinh npx
h
SE perforations area and is spatially separated from the Off  
D
channel. A series of optimizations and design rules were þ sinh npð1  xÞ  ½ðVG  VD Þz  VG ; (A2)
derived from the simulation and experimental sets. An ideal h
device requires its SE to be ultra-thin with large perforations
(the “tunnel” effect) and with large FF value. The device where hs and hd are the source electrode and dielectric layer
switching performance relies on the SE Schottky barrier; how- thicknesses normalized by h.
ever, its output performance and threshold voltage are nega- The lateral electric fields [Eq. (A3)] are obtained by
tively influenced. The On and Off channel origins shown to be deriving the equation of the potential surface over the hori-
localized at the SE lateral facets and top facet, respectively, zontal axis (x). To simplify, the source electrode potential is
enable a design consisting of two layers shown to provide both grounded and the term for the active layer thickness, ha,
high switching performance, similar threshold voltage and replaces the term (1-hd-hs),
similar output performance. While this study centered on PE-
 
VFET architecture with well-defined patterns (based on BCP DX 2 1
fabrication methods) the results and especially the physical ux ðx; zÞ ¼  sinðnpzÞ  
h n D np
insights would be applicable also to less ordered fabrication sinh np
h
methods such as solution-based nanowire SEs.  
VG VD
 ½sinðnphd Þ þ sinðnpha Þ
ACKNOWLEDGMENTS hd ha
    
D D
This research was supported by the Israel Science Founda-  cosh npx  cosh npð1  xÞ : (A3)
tion (Grant No. 695/10) and the Russell Berrie Nanotechnology h h
Institute at the Technion – Israel Institute of Technology. Ariel
J. Ben-Sasson is grateful to the Azrieli Foundation for the We require to obtain the electric fields adjacent to the SE lat-
award of an Azrieli fellowship and to Mr. Manfred Gruber for eral facets in order to determine the local potential barrier
fruitful discussions on numerical analysis methods. lowering at the perforations [Eqs. (5) and (6)]. A simpler
expression than the one presented in Eq. (A3) is obtained in
Eq. (A4) when referring to a specific horizontal location x0,
APPENDIX: ANALYTICAL DESCRIPTION OF THE
where x0 is assumed to be in close proximity to the SE facets
POTENTIAL SHAPE
(x0!0 or x0!1). For analysis purposes x0 is considered to
The potential shape is obtained by solving the 2D ho- be one molecular layer away from the electrode, a distance
mogenous Poisson equation (Laplace problem) in a rectangu- approximated at 1 nm (the length of one mesh increment in
lar space bounded by the gate and the drain electrodes in the the numerical simulation).

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 044501-12 A. J. Ben-Sasson and N. Tessler J. Appl. Phys. 110, 044501 (2011)

0 ( D D
) 1
VG 1  2ep h x0 cos½pðz þ hd Þ þ e2 h px0
B ln þC
1D B C
D D
B hd 1  2ep h x0 cos½pðz  hd Þ þ e2 h px0 C
ux ðx0 ; zÞ ¼ B ( ) C: (A4)
2p h B VD 1  2e pDhx0
cos½pðz þ ha Þ þ e 2pDhx0 C
@ ln A
D D
ha 1  2ep h x0 cos½pðz  ha Þ þ e2p h x0

13
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