05 2016-3-6-pp.27-34
05 2016-3-6-pp.27-34
05 2016-3-6-pp.27-34
1Department of EEE, Meenakshi Academy of Higher Education and Research, (MAHER University), Chennai City, India
2Department of EEE, Arulmigu Meenakshi Amman College of Engineering, Vadamavandal, Kanchipuram, Tamil Nadu State, India
3GRT Institute of Engineering and Technology, Tirupathi Highway, Mahalakshmi Nagar, Puzhal, Chennai City, Tamil Nadu State,
India
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Yuvaraja et al/ International Journal of Advanced and Applied Sciences, 3(6) 2016, Pages: 27-34
The designed sector designates the arrangement 1. The converter output parameters are controlled by
of a simple microgrid, shown in Fig. 1. It entails a controlling the pulse given to the gate terminal and
collector bus, a voltage source converter, a bus Switching is done through pulse width intonation.
capacitor, CB, along with the load (Woyte et al., 2. The operating frequencies of the voltage source
2003). The capacitor Connected along with the load converter switches are able-bodied above the
ensures that the voltage pulsations at the terminuses fundamental frequency of the ac supply and the
of the voltage source converter do not seem across resonant frequency of the microgrid.
the load (Ropp et al., 1999). For minimalism, the load 3. The dc state of the converter is allied to a strong dc
is estimated to be unprejudiced, and it is bus with amply towering voltage.
characterize as a parallel amalgamation of resistance 4. The converter is regulated by a sky-scraping
R and inductance L, as is the standard in islanding bandwidth current controller.
detection narrative (Kotsopoulos et al., 2002). The 5. The complete system is considered to be in
line impedance sandwiched between the collector balanced condition.
bus and the load is less significant than the load By assuming these conventions, the fundamental
impedance and is abandoned. The converter is frequency of the Voltage Source converter model is
associated with the collector bus through an justified; and somewhere the converter exhibits as a
interface inductor, which is not revealed here (Smith middling current resource. Note that the high
et al., 2000). frequency converter current dynamics have been
It is assumed in this paper that: snubbed in order to focus solely on the dynamics and
control of the islanded microgrid.
than 1/RvCB and, KPKI/ReCB the scheme is well 2.3 Frequency Control Scheme
damped nevertheless of the load resistance. Devising
confirmed that the plant is well damped, a PI As both the voltage and frequency of the
compensator may be castoff to outcome the system microgrid are controlled, the system consummate of
voltage to track the voltage allusion V*Bd. The direct Fig. 2, which includes the voltage controller, is hand-
input is (Eq. 3): me-down for the derivation of ωB(s)/i1q(s). Fig. 2
𝐾
𝑢𝑣 (𝑠) = (𝐾𝑃𝑣 + 𝑖𝑣) (𝑣𝐵𝑑 ∗ (𝑠) − 𝑣𝐵𝑑 (𝑠)) (3) shows that transfer function ωB(s)/i1q(s) is given by
𝑠
(Eq. 6 and 7):
Where Kpv and Kiv are proportional and 𝜔𝐵 (𝑠) 𝑣𝐵𝑑 (𝑠) 1 𝑖𝐿𝑞 (𝑠)
fundamental gains equally. The blocked loop transfer = −𝐾𝑏 + ( ) (6)
𝑖1𝑞 (𝑠) 𝑖1𝑞 (𝑠) 𝐶𝐵 𝑣𝐵𝑑0 𝑖1𝑞 (𝑠)
function of the voltage control loop is (Eq. 4 and 5): Deriving transfer function and substituting them
𝑠 2 𝐾𝑃 𝐾𝐼
𝑣𝐵𝑑 (𝑠) (𝐾𝑝𝑣 𝑠+𝐾𝑖𝑣 )(
𝐶𝐵
−
𝐶𝐵
) in (5) results in:
= (4) 𝑘𝑏 𝐾𝑎 𝑠2
𝑣𝐵𝑑 ∗ (𝑠) 𝐷(𝑆)
𝜔𝐵 (𝑠) 𝐶𝐵
=− +
𝑖1𝑞 (𝑠) 𝐷(𝑠)
Where 𝑘 𝐾 𝑘 𝐾𝑎 𝐾𝑝𝑣 𝑘 𝐾𝑎 𝐾
1 𝐾𝑝𝑣 2 𝐷(𝑠)−𝑘𝐼 𝐾𝑎 𝑠2 +( 𝐼 𝑎 + 𝐼 )𝑠− 𝐼 𝐶 𝑖𝑣
𝐷(𝑆) = 𝑆 4 + ( + ) 𝑆3 + ( − 𝐾𝑃 𝐾𝐼 + 𝑅𝐶𝐵 𝐶𝐵 𝐵
(7)
𝑅𝑒 𝐶𝐵 𝐶𝐵 𝐿𝐶𝐵 𝐶𝐵 𝑣𝐵𝑑0 𝐷(𝑠)
𝐾𝑖𝑣 𝐾𝑃 𝐾𝐼 𝐾𝑃 𝐾𝐼 𝐾𝑝𝑣 𝐾𝑃 𝐾𝐼 𝐾𝑝𝑣
2
)𝑆 − ( + )𝑆 − (5) The denomination of ωB(s)/i1q(s) is one and the
𝐶𝐵 𝑅𝑒 𝐶𝐵 𝐶𝐵 𝐶𝐵
same to that of the closed loop transfer function of
The proportional and integral gains of
the (4), which is balanced and glowing damped. This
compensator are preferred as 0.078 and 95
entails in the isolation of the purpose of the
correspondingly plus the step response of the
frequency control loop has a stable plant and a PI
voltage control loop for two load configuration as
compensator may be castoff to normalize the system
generated by MATLAB/Simulink is shown below.
frequency to track ωB*.
Fig. 2: Linearized system model with the voltage control loop added
A frequency control loop is anticipated for the created. By instigating the fuzzy technology the
power system. The stand constraints and the voltage and frequency can be controlled in a single
linearization position are manipulated. The controller, the inaccuracy from voltage and
comparative and fundamental gain of the reparation frequency is given to the fuzzy controller and the
is chosen as 0.014 and 17 respectively and the step output gain is given to the plant from the controller.
responses of frequency control loop for two load Inputs to the fuzzy controller are voltage error and
configuration. frequency error. And the outputs from the fuzzy
controller are I1d and I1q which are the real and
2.4 Fuzzy Controller reactive power respectively in Fig 3 and 4.
Fuzzy systems are widely used in today 3. PI controller and FMRLC algorithm
engineering (Saber et al., 2014; Kadir, 2014;
Anderson 2015; Sangsefidi et al., 2015; Hofford A MG in islanded mode is used to verify the
2015; Markez and Pique, 2015). In control, based on performance of proposed FMRLC algorithm. The
conventional PI control method, the modernized structure of MG power system used for the
fuzzy control algorithm is cast-off to assess the simulation is shown in Fig. 5.
fuzzification and defuzzification progression in Fig. 5 system is composed of PV bus supplied by
MATLAB/Fuzzy toolbox. The variables and its two sources, wind turbine and asynchronous
associate membership function of fuzzy toolbox is generator and PQ bus with two loads, linear load and
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Yuvaraja et al/ International Journal of Advanced and Applied Sciences, 3(6) 2016, Pages: 27-34
induction motor. The PV and PQ buses are connected The asynchronous generator is used as a
via 100 m distribution line. The wind turbine synchronous condenser that controls the grid
represents a renewable source. voltage by its excitation system during load or/and
wind variation.
Fig. 5: Single line diagram of the power system used in the simulations
The induction motor is 200kW while the linear load side. The mathematical model of the SVC is
load consists of 120 kW active loads and 50 kVAR presented. The simplified SVC phasor model block of
capacitive loads connected continuously to the bus the FACTS library of MATLAB/SIMULINK is used for
and 20 kW active loads and 20 kVAR capacitive loads the simulation. The original model of SVC applies PI
connected after 2.5 seconds of the simulation. A 120 controller. The controller was modified to switch
kVAR Static VAR Compensator (SVC) is connected at
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Yuvaraja et al/ International Journal of Advanced and Applied Sciences, 3(6) 2016, Pages: 27-34
between PID conventional control algorithm and Comparing Fuzzy and PI controller Output for
FMRLC algorithm. Voltage Control shown in Fig. 6-Fig. 8. For ‘R’ load
and ‘RL’ Load.
4. Comparison of simulation results Comparing Fuzzy and PI controller Output for
Frequency Control shown in Fig. 8 for ‘RL’ load and
‘R’ Load.
Fig. 6: Fuzzy PI controller output response for voltage control ‘R’ Load
Fig. 7: Fuzzy PI controller output response for voltage control ‘RL’ Load
Fig. 8: Fuzzy PI Controller output response for frequency control for ‘RL’ Load and ‘R’ Load
The objective of simulations is to verify the applying a well-known PID controller that is used as
enhancement of MG performance in islanded mode a benchmark for comparing different control
using proposed FMRLC against performance of algorithms. Moreover, to show effectiveness of SVC,
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Yuvaraja et al/ International Journal of Advanced and Applied Sciences, 3(6) 2016, Pages: 27-34
performance of the two control algorithms were algorithm was able to maintain line voltage to the
compared with MG performance without SVC. In this required level with minimal disturbance compared
case, asynchronous generator is used as a to both conventional PID controller and simulation
synchronous condenser and its excitation system without SVC. The transient behaviors of the system
controls the grid voltage at its nominal value. The follow closely the reference model transient. The
simulation is conducted using the system described second curve in Fig. 9 shows the error between
in section 3 for 15 sec. A load change is applied to the reference model output and measured bus voltage
induction motor by a repeating pattern as shown in for FMRLC algorithm. The learning algorithm was
Fig. 9. The objective of the repeating pattern of load able to store information about proper control action
change is to expose learning algorithm repeatedly to during grid transient and recall it to minimize error
possible variations that could take place within the during the full simulation run. On the other hand,
power system. Hence, the system would form and PID controller shows steady performance that does
memorize proper control surface for different not improve with time as expected as shown in
operating points. In addition, a linear load has been second curve in Fig. 10. The grid without SVC has
connected to MG after 2.5 sec to allow MG to operate degraded performance.
on its edge of power follow (the load was not The bottom curves, in both Fig. 9 and 10, show
connected at start of simulation to avoid MG the measured susceptance of the SVC voltage
instability during its transient). The reference model regulator for both FMRLC and PID controller
parameters were calculated from equation (1) and respectively. In addition the load variation of the
(3). The time constant however, as stated in section induction motor is presented. The proposed PID-
2, a larger time constant of 0.04 sec (about 7 times FMRLC algorithm was able to generate strong
the calculated one) is used to allow more achievable control action and deploy the full capacity of SVC to
performance. The selection is confirmed with the compensate for load disturbance. The PI controller
results shown in Fig. 10 where the average absolute was not able to generate strong control action
reactive power from the SVC was 40 kVAR. The despite of it operation close to the critical stability
required OS% is set to 1%, hence, ωn= 30sec. A PID region. The bus voltage and the voltage error in the
FMRLC was used in control loop of SVC. It was found period from 4.1 sec to 4.6 sec; at time 4 sec, the
that PI or PD FMRLC wouldn’t perform adequately as machine load increased form 0.1 pu to 0.9 pu. The
it will be shown in results discussion. Eleven measured overshoot was 0.9% for the FMRLC
membership functions are used for fuzzy controller algorithm while it was 1.2% using the PID controller.
and five for inverse model. A PID Without SVC, the overshoot was 1.8%. The voltage
FMRLC was used in control loop of SVC. It was settle within 6% of its maximum deviation from
found that PI or PD FMRLC wouldn’t perform desired bus level after 0.35 sec (four to five times the
adequately as it will be shown in results discussion. time constant) for the FMRLC while it takes 2.9 sec
Eleven membership functions are used for fuzzy with the PID controller.
controller and five for inverse model. The simulation Integral-of-Time Multiplied Absolute Error
result for the first 10 seconds for the proposed PID- (ITMAE) and integral square error (ISE) for the three
FMRLC. Fig. 10 shows the same simulation using PID cases for 16 sec simulation. The measurement of
SVC and without SVC. The scales in Fig. 9 and Fig. 10 both error parameters (ITMAE and ISE) was
are the same for convenience. Top curves, in Fig. 9, performed after the 1st 1.3 sec of simulation to avoid
show bus voltage (pu) for FMRLC (in solid black line) building high values during MG transient operation
and reference model in (in dashed blue line) and, for that would hide the details of system performance
PID controller (in solid black line) and without SVC during the rest of simulation period.
(in dashed blue line). It can be noted that FMRLC
Fig. 9: Measured performance of MG using FMRLC SVC. From top to bottom 2- the bus voltage/reference model output,
voltage error between bus voltages and reference model, and 1- the SVC susceptance/Load.
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Yuvaraja et al/ International Journal of Advanced and Applied Sciences, 3(6) 2016, Pages: 27-34
Fig. 10: Measured performances of the MG using PI VSC and without SVC. From top to bottom 1- the bus voltage, 2- voltage
error between bus voltages and reference model and 3- the SVC susceptance/Load
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