INVITED Cryo-CMOS Electronic Control

for Scalable Quantum Computing

Fabio Sebastiano1, Harald Homulle1, Bishnu Patra1, Rosario Incandela1, Jeroen van Dijk1,
Lin Song1,2, Masoud Babaie1, Andrei Vladimirescu1,3, Edoardo Charbon1,4,5
1
Delft University of Technology, Delft, The Netherlands,2Tsinghua Univ., Beijing, P.R. China, 3U.C. Berkeley, Berkeley,
CA, U.S.A. 4Intel Corp., Hillsboro, OR, U.S.A., 5EPFL, Neuchâtel, Switzerland
[email protected]

ABSTRACT
Quantum computers1 could revolutionize computing in a profound
way due to the massive speedup they promise. A quantum
computer comprises a cryogenic quantum processor and a
classical electronic controller. When scaling up the cryogenic
quantum processor to at least a few thousands, and possibly
millions, of qubits required for any practical quantum algorithm,
cryogenic CMOS (cryo-CMOS) electronics is required to allow
feasible and compact interconnections between the controller and
the quantum processor. Cryo-CMOS leverages the CMOS
fabrication infrastructure while exploiting the continuous
improvement of performance and miniaturization guaranteed by
Moore’s law, in order to enable the fabrication of a cost-effective
practical quantum computer. However, designing cryo-CMOS
integrated circuits requires a new set of CMOS device models, Figure 1. Bloch sphere representation of a qubit.
their embedding in design and verification tools, and the
possibility to co-simulate the cryo-CMOS/quantum-processor extremely large datasets, factorization of large integers in their
architecture for full-system optimization. In this paper, we address prime factors and simulations of quantum systems for the
these challenges by focusing on their impact on the design of optimization of drug synthesis, materials and industrial chemical
complex cryo-CMOS systems. processes [1]. In a quantum computer, standard logic bits are
replaced by quantum bits (qubits), which can be represented as a
CCS CONCEPTS point on the surface of a three-dimensional sphere, the so-called
Hardware → Quantum computation; Electronic design Bloch sphere, shown in Figure 1. In this construct, standard logic
automation; Analog and mixed-signal circuits; Application ‘1’ and ‘0’ are replaced by quantum states |0 and |1 , and are
specific integrated circuits. manipulated, so as to exploit the fundamental phenomena of
quantum mechanics for computation, i.e. superposition and
KEYWORDS entanglement [2]. Qubits can exist in a superposition of both state
Cryo-CMOS, cryogenics, quantum computation, qubit, error- |0 and |1 simultaneously, which results in a computing power
correcting loop, device models. that doubles with every additional qubit, thus resulting in a
massive speedup with respect to traditional computers. For
1 INTRODUCTION example, it has been estimated that the state of a 50-qubit system
Quantum computers hold the promise to successfully address cannot be stored in the memory of the world’s most powerful
computational problems that are intractable by standard computers today [3].
computing paradigms. These problems include efficient search in In addition to a quantum processor comprising several qubits,
a quantum computer also requires a classical controller to
manipulate and read out qubit states (Figure 2). Classical
Permission to make digital or hard copies of all or part of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed controller and quantum processor must be placed in close
for profit or commercial advantage and that copies bear this notice and the full proximity, because of the need for physical interconnections
citation on the first page. Copyrights for components of this work owned by others between them. This requirement will be especially stringent when
than ACM must be honored. Abstracting with credit is permitted. To copy otherwise,
or republish, to post on servers or to redistribute to lists, requires prior specific the number of qubits, and hence the wires connecting them, will
permission and/or a fee. Request permissions from [email protected]. grow to very large numbers. Since most quantum processors
DAC '17, June 18-22, 2017, Austin, TX, USA
© 2017 ACM. ISBN 978-1-4503-4927-7/17/06…$15.00 nowadays require operation at deep-cryogenic temperature well
DOI: http://dx.doi.org/10.1145/3061639.3072948 below 1 K, such as in the examples shown in Figure 2, the
 encoding the quantum information on a large number of qubits,
thus trading off simplicity for fidelity in execution of the quantum
algorithm [21]. Thus, although a quantum computer with 50
logical qubits can already exceed the memory capabilities of
today’s supercomputers and non-trivial quantum chemistry
problems can be solved with the availability of just 100 logical
qubits [22], thousands, or even millions, of physical qubits, i.e. the
real physical devices, are required to enable practical quantum
computation.
The classical controller in Figure 2 must serve this large
number of qubits by taking care of the execution of the quantum
algorithm and, in parallel, by implementing an error-correction
loop intended to maintain the fidelity of the computation beyond
Figure 2. Quantum-classical interface. coherence times. Interfacing solid-state qubits usually involves the
generation and acquisition of purely electrical signals, such as
classical controller must also operate at cryogenic temperature. To
microwave bursts with frequencies ranging from a few GHz to
address this issue, a cryogenic CMOS (cryo-CMOS) electronic
tens of GHz and voltage and current pulses with a bandwidth of
controller has been proposed [4]-[7]. The controller must satisfy
tens of MHz.
stringent requirements on noise, accuracy, and bandwidth, in
Since existing state-of-the-art quantum processors comprise
order not to reduce qubit performance, and to comply with power
only a few qubits, most of the electronics making up the classical
dissipation limits imposed by the cooling technology. Meeting
controller operate at room temperature and it is wired to the qubits
those demands requires effort and innovations both in the
in the cryogenic chamber. Only a few functionalities, such as low-
development of new system and circuit architectures and in the
noise amplification of read-out signals and attenuation of control
creation of novel design and verification strategies and tools. In
signals, are implemented at cryogenic temperature in close
regard to design tools, few topics require specific attention: the
proximity to the quantum processors. However, when scaling up
co-simulation of the electronic interface with the quantum
the number of qubits to the large number required for any
processor for a full system optimization; the need for models of
practical computation, this approach may incur a number of
CMOS devices operating at cryogenic temperature and their
limitations, including the thermal load of the large number of
embedding in commercial EDA tools to enable the design of
cables, or the latency of the error-correction loop [23]. Although
complex circuits and systems.
there is not yet a general consensus about whether those
In this paper, we focus on those challenges and their impact on
limitations are critical or may be circumvented in the near future,
the design of complex cryo-CMOS circuits. The paper is
it is clear that wiring thousands of low-frequency and high-
organized as follows. The motivations and the requirements for
frequency wires from room temperature to the cryogenic quantum
the cryo-CMOS controller are presented in section 2. Section 3
processor would lead to an extremely expensive, bulky, unreliable
and 4 discuss the challenges for the development of the quantum-
and, hence, unpractical quantum computer.
processor/controller co-simulations and cryo-CMOS device
As an alternative, a cryogenic controller may be employed, in
models, respectively, while remarks on cryo-CMOS design
order to relieve the requirements on interconnections, system size
automation occupy section 5. Conclusions are drawn in section 6.
and reliability. Several technologies have demonstrated
2 THE NEED FOR CRYO-CMOS CONTROL functionality at cryogenic temperature, such as junction field-
effect transistors (JFET), high-electron-mobility transistors
Several physical implementations have been proposed for
(HEMT), superconducting devices based on Josephson junctions,
qubits, however solid-state alternatives are currently the most
compound semiconductors (e.g. GaAs) and CMOS transistors
promising in terms of scalability to a large number of qubits,
[24][25]. However, by relying on the progress of the
although no more than a dozen qubits have been demonstrated in
semiconductor industry, only CMOS technology can ensure low
such platforms so far [8]. Solid-state qubits come in several
power consumption and functionality down to 30 mK [7][26],
variants, such as electron spins in quantum dots, superconducting
while offering the integration of billions of transistors on a single
circuits, and nitrogen-vacancies in diamond lattices [9]-[20]. A
chip, as it will be required to handle the complexity of future
common feature of most of those technologies is the required
quantum processors. Moreover, CMOS is preferred also because
operation at deep-cryogenic temperatures, typically below
the design automation infrastructure is very mature for the
100 mK. This is required both to expose their quantum behavior
standard industrial and military temperature ranges, i.e. down
and to increase the coherence time of their quantum state. The
to -55 °C.
coherence time is usually far below a second, that is a time frame
Figure 3 shows a generic platform for control and read-out of a
much shorter than what is required for the execution of any
quantum processor. It comprises a frontend for (de)multiplexing,
practical quantum algorithms. Consequently, to counteract the
amplification, analog-to-digital conversion (ADC) and digital-to-
loss of the quantum state, quantum error-correction techniques
analog conversion (DAC) for the analog signals coming from and
have been developed to exploit information redundancy by
 300K Table 1. Error sources for a microwave pulse for single-
1-4K
qubit operation (assuming a square pulse).
20-100mK OPTICAL GUIDE APD TDC
Accuracy
Microwave frequency
Noise
ADC Accuracy
Microwave amplitude
MUX

Noise
Digital
ADC Accuracy
control Microwave duration
Quantum (ASIC/ Noise
Processor FPGA) Accuracy
Microwave phase
Noise
DAC
DEMUX

hand with the development of more advanced and powerful

DAC refrigeration systems.
In addition to the above-mentioned challenges, proper design
Bias / References T Sensors tools and design flows are required to support the development of
a complex system as the one in Figure 3. Cryo-CMOS can already
exploit the design automation infrastructure already in place for
Figure 3. Generic electronic platform for the control and standard CMOS. However, specific issues related both to the
read-out of quantum processors. operation at cryogenic temperature and the interfacing with a
feeding to all qubits. Ideally, quantum processors and electronics quantum system must be addressed, as elaborated in the following
should operate at the same temperature, if not even on the same sections.
chip, to eliminate the need for any off-chip interconnect.
However, currently available refrigeration technologies limit the
3 CO-SIMULATING THE ELECTRONIC
available cooling power to less than ~1 mW at temperature below CONTROLLER AND THE QUANTUM
100 mK [28], and it is unlikely that the full electronic controller PROCESSOR
can operate with such power budget in the near future. On the The tight power budget coupled with very demanding
contrary, a cooling power exceeding 1 W is usually available at specifications calls for a careful system optimization. While
the 4-K stage, thus allowing the majority of the electronics to electronic controllers operating at room temperature can be
operate there. A limited amount of low-power electronics, overdesigned to make the performance of the full quantum
including (de)multiplexers to reduce the number of connections to computer limited by the qubits by a wide margin, this cannot be
the 4-K stage, is envisioned to operate at the same temperature as allowed in a cryogenic implementation. It is then necessary to
the quantum processor, as shown in Figure 3. understand clearly the effect of any non-ideality of the electronic
The specifications for the cryo-CMOS electronic controller are controller on the system performance.
extremely challenging. To ensure the target performance in the For example, in the case of spin qubits and transmons [10][17],
quantum processor, electronic signals driving the qubits must be single-qubit operations, i.e. rotations of the qubit state | in the
highly accurate (in terms of amplitude, timing, frequency and Bloch sphere in Figure 1, can be executed by exciting the qubit
phase) and contribute a negligible amount of noise. As a with a microwave pulse with a specific carrier frequency and
comparison, the control of state-of-the-art quantum processors is phase and specific pulse shape, amplitude and duration, which all
achieved by using the most accurate (and expensive) bench-top together determine the axis of rotation and the angle of rotation in
electronic instrumentation available on the market [9]-[20]. The the coordinate system in Figure 1. The possible error sources for
read-out must be very sensitive to detect the weak signals from this example are listed in Table 1. Any error or any additional
the quantum processor [6], and to ensure a low kickback, so as to noise on the pulse parameters would cause an error in the
avoid altering qubit states. These specifications must be granted operation that can be quantified by the fidelity of the quantum
while keeping the latency of the error-correction loop much lower operation [27]. The fidelity, which should be as close as possible
than the qubit coherence time. Moreover, while ensuring the to 100%, is a measure of the reliability of the quantum operation,
above-mentioned functionalities and specifications, the controller similar to the Bit Error Rate (BER) for classical communication
must dissipate very low power. Although more than 1-W cooling systems. Knowing how much each single source of error
power is available at 4 K, a processor with only 1000 qubits contributes to the final fidelity enables a better optimization of the
would limit the power budget to 1 mW/qubit, which is already design, since, for example, providing accuracy/noise in the pulse
very challenging, as shown in [6]. Thus, while targeting for a amplitude may be more expensive in terms of power consumption
power budget of 1 mW/qubit is ambitious, but probably than ensuring accuracy/noise in the pulse duration. Error
achievable in the short and medium term, it becomes clear that the budgeting for a minimum power consumption would then become
development of advanced cryo-CMOS systems must go hand in possible.
 10-3
2.5

1.5

Id [ A ]
1

V gs=0.68V
0.5 V gs=1.05V
Figure 4: Process for the co-simulation of the electronic
V gs=1.43V
controller and the quantum processor.
V gs=1.8V
0
For this purpose, we have developed a MATLAB simulation 0 0.5 1 1.5 1.8
tool that receives as input a description of the required electrical V [V]
ds
signals and simulates the quantum system with those excitations Figure 5: I-V characteristics of a 2320 nm/160 nm NMOS
by numerically solving the Schrödinger equation (Figure 4). As a fabricated in 160-nm CMOS: measurements at 300 K (dotted
result, the fidelity of the operation is computed. Since the lines) and 4 K (solid lines); SPICE-compatible model (dashed
simulation is computationally intensive, we are currently only lines).
able to simulate two spin qubits. However, since this allows the 10-4
7
simulation of single- and two-qubit operations and qubit read-out
(which are sufficient building blocks for most quantum computer 6
implementations), it is sufficient, together with a theoretical
model, to derive an accurate error budget for the general 5
electronic platform of Figure 3. Moreover, the MATLAB model
4
[A]

of the quantum processor can be used for verification of the

developed cryo-CMOS circuit during the design phase (or during 3
d
I

experimental validation before connection to the quantum

processor): the simulated (or measured) output waveforms could 2 Vgs =0.54V

be fed to the qubit simulator while the electrical signals generated Vgs =0.65V
1 Vgs =0.88V
for the read-out can be passed to the circuit simulator.
Vgs =1.1V
This represents the first step towards a fully integrated 0
environment for the design and verification of the 0 0.2 0.4 0.6 0.8 1 1.1
V [V]
controller/quantum-processor system, although several challenges ds

are already in sight. First, it is well known that quantum systems Figure 6. I-V characteristics of a 1200 nm/40 nm NMOS in 40-
cannot be efficiently simulated with traditional computers, and it nm CMOS: measurements at 300 K (dotted lines) and 4 K
is unclear how the simulations can be extended to a larger number (solid lines); SPICE-compatible model (dashed lines).
of qubits that can better represent a real scenario. Furthermore, it current when sweeping the drain-source voltage upwards or
would be convenient to embed the qubit simulation in commercial downwards.
EDA design/verification flows and tools. Finally, it will be Although the physics of cryo-CMOS is generally understood
necessary to fully or partially integrate the physical simulation of [30] and a few nanometer technologies have been cryogenically
qubit into the full design/validation stack of the quantum system characterized (65 nm at 78 K [31], 32 nm at 6 K [32], 14 nm at 77
[29], which includes the infrastructure for the quantum microcode K [33]), there is not yet a general consensus on a standard
execution and for the quantum compiler on top of the above- cryogenic model for modern technologies, since prior models
discussed physical layer. were limited to mature technologies (feature size ≥ 160 nm) and
moderate cryogenic temperatures (>20 K) [34]-[38].
4 CRYO-CMOS DEVICE MODELING
Characterization and modelling of nanometer CMOS technologies
Accurate device models are required to reliably design and is specifically relevant for implementing low-power circuits for
simulate complex cryo-CMOS circuits. At deep-cryogenic the platform in Figure 3, where handling of large-bandwidth high-
temperature, many physical parameters that determine transistor frequency signals is required.
behavior, such as carrier mobility, show a strong deviation from As a step in that direction, we have characterized a large
room temperature. This results, for example, in a larger drain number of active and passive components in standard 160-nm and
current and higher threshold voltage at 4 K. In addition, several 40-nm CMOS technologies [6][7][39]. As an illustration, Figure 5
non-idealities that are specific to the cryogenic operation appear, and Figure 6 shows the output characteristics of NMOS transistors
such as the a so-called ‘kink’, i.e. a sudden increase in drain in both technologies. Despite a non-negligible shift of the
current at high drain-source voltage, and hysteresis in the drain transistor parameters, such as threshold voltage and current gain,
those characteristics are not dissimilar to the ones of a standard limited to application-specific integrated circuits (ASIC). FPGAs
NMOS transistor, thus leading us to believe that standard SPICE could be beneficial thanks to their reconfigurability, which could
models may be applicable also at cryogenic temperature. prevent expensive and time-consuming cool-down-warm-up
However, although it seems that a SPICE-compatible model for cycles. In addition, FPGA design tools leverage a mature
the DC behavior of cryo-CMOS devices may be feasible, much synthesis and place-and-route technology, with advanced
work must still be devoted to develop a full cryo-CMOS device verification tools that could be used to emulate the operation of
model with the same reliability and accuracy of the models the circuit at cryogenic temperatures.
available for commercial technologies at room temperature, thus For the design and verification of the cryogenic FPGA,
allowing the design of the complex RF, analog, mixed-signal and standard tools for firmware design were employed. The
digital circuits of Figure 3. characterization of a standard FPGA library was an important step
The challenges to be addressed include the modelling and in creating the firmware, thus enabling correct operation at deep-
characterization of dynamic and RF behavior, of noise at low and cryogenic temperature. Similar efforts are needed in ASIC digital
high frequency, both for active devices and passives. Moreover, libraries, where transistor models are part of this characterization
some preliminary investigations have suggested that transistor and could enable fast library certification. Ultimately, logic gate
mismatch at 4 K is largely uncorrelated to that at 300 K and that farms will be required to verify simulations and to validate the
standard design techniques to mitigate the effect of mismatch may proposed models. In this context, the process of digital library
need to be modified [40]. The large impact of mismatch on the characterization is not unlike a conventional one, with the
performance and, hence, the design of analog and mixed-signal difference that it requires care in measuring the circuits at various
circuits asks for further investigations, and both additional temperatures with a well-controlled measurement setup and
experimental data and theoretical analysis will be required before particular attention to self-heating. The library characterization
the correct cryogenic mismatch model can be included in design will also yield non-functional library elements, depending on
tools. Finally, self-heating may give a non-negligible effect, since temperature, thus requiring that synthesis and place-and-route
even a temperature raise of only a few degrees represents a tools be temperature-driven and/or temperature-aware.
relatively large increase in absolute temperature that can result in A less trivial task would be the design of digital circuits that
a large variation of the electrical properties of the devices. exploit the specific features of cryo-CMOS. The main challenge
Because of this high sensitivity, it may be necessary to model the of operating large CMOS circuits and systems at cryogenic
self-heating for each individual device. This would require strong temperatures is power dissipation. In order to minimize power
efforts in properly updating the EDA tools, since self-heating of dissipation, the supply voltage could be reduced even down to a
single devices or circuit sub-blocks can be highly dependent both few tens of millivolt by exploiting the relaxed requirement on
on their physical placement on the die and their surroundings noise margins due to the low thermal-noise level at cryogenic
(including metal interconnections), not to mention the effect of temperature. Operation in sub-threshold regime can also be
thermal transients. At the moment, those issues are left largely heavily exploited thanks to the improved subthreshold slope at
unexplored for cryo-CMOS to the best of the author’s knowledge. low temperature and to the resulting large on/off-current ratio
(Ion/Ioff) ratio. Furthermore, the expected extremely low leakage
5 DESIGN AUTOMATION FOR CRYOGENIC current in cryo-CMOS may lead to power-efficient use of existing
DESIGNS dynamic logic, or even bring in the possibility of new dynamic
Although the characteristic of CMOS transistors show a very logic families. This can pose problems in the synthesis and
wide alteration at cryogenic temperature, it has been shown that verification of logic circuits, prompting the EDA industry to
even complex commercial components not designed or specified rethink models and perhaps even simulators, so as to achieve the
outside the commercial temperature range, such as FPGAs, can necessary accuracy in the simulation of these regimes.
reliably operate at cryogenic temperature [41]-[43]. Extensive Finally, the operating temperature can be exploited as a new
characterization showed not only that all major components of a design parameter. Since the cooling power in a cryogenic
standard Xilinx Artix 7 FPGA, including look-up tables (LUT), refrigerator is larger at higher temperature, higher computational
phase-locked loops (PLL) and IOs, operate correctly down to 4 K power could be placed at a higher temperature. However,
but also that their logic speed is very stable over temperature [43]. particular care should then be devoted to the interconnections that,
An ADC based on a time-to-digital converter (TDC) has also been apart from becoming unpractical, could also occupy a relevant
implemented in the same FPGA platform and its continuous fraction of the cooling power budget due to their thermal
operation from 300 K down to 15 K has been demonstrated, conduction. The full digital back-end of a quantum computer
although specific care had to be taken in designing the firmware would then spread over several temperature stages, eventually
to minimize the temperature sensitivity, and calibration was with a lower inter-stage data communication rate for circuits at
extensively used to compensate for temperature effects [42]. lower temperatures. Although conceptually interesting, such
Apart from showing the functionality of standard CMOS approach would require an ad-hoc EDA infrastructure covering
components at cryogenic temperature, FPGAs can also have a several multidisciplinary domains, including device modelling
practical application for the implementation of the system in and library characterization over a very wide temperature range,
Figure 3, which at least in the first instance will not be necessarily
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