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SN54HC32, SN74HC32
SCLS200E – DECEMBER 1982 – REVISED JULY 2016

SNx4HC32 Quadruple 2-Input Positive-OR Gates

1 Features 3 Description
•
1 Wide Operating Voltage Range: 2 V to 6 V The SNx4HC32 devices contain four independent
2-input OR gates. They perform the boolean function
• Outputs Can Drive Up to 10 LSTTL Loads Y = A • B or Y = A + B in positive logic.
• Low Power Consumption ICC: 20 µA (Maximum)
• Typical tpd: 8 ns Device Information(1)
• ±4-mA Output Drive at 5 V PART NUMBER PACKAGE BODY SIZE (NOM)

• Low Input Current: 1 µA (Maximum) SN54HC32J CDIP (14) 19.94 mm × 7.62 mm

SN54HC32W CFP (14) 9.21 mm × 7.11 mm
2 Applications SN54HC32FK LCCC (20) 8.89 mm × 8.89 mm
SN74HC32D SOIC (14) 4.90 mm × 3.91 mm
• Education
SN74HC32DB SSOP (14) 6.20 mm × 5.30 mm
• Toys
SN74HC32N PDIP (14) 19.30 mm × 6.35 mm
• Musical Instruments
SN74HC32NS SO (14) 10.30 mm × 5.30 mm
• Medical Healthcare and Fitness
SN74HC32PW TSSOP (14) 5.00 mm × 4.40 mm
• Grid Infrastructure
(1) For all available packages, see the orderable addendum at
• Electronic Point of Sale the end of the data sheet.
• Test and Measurement
• Factory Automation and Control
• Building Automation
Logic Diagram (Positive Logic)
A
Y
B
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC32, SN74HC32
SCLS200E – DECEMBER 1982 – REVISED JULY 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description .................................................. 9
2 Applications ........................................................... 1 8.4 Device Functional Modes ......................................... 9
3 Description ............................................................. 1 9 Application and Implementation ........................ 10
4 Revision History..................................................... 2 9.1 Application Information............................................ 10
9.2 Typical Application .................................................. 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 12
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 12
6.2 ESD Ratings: SN74HC32 ......................................... 4 11.1 Layout Guidelines ................................................. 12
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 12
6.4 Thermal Information: SN54HC32.............................. 5 12 Device and Documentation Support ................. 13
6.5 Thermal Information: SN74HC32.............................. 5 12.1 Documentation Support ........................................ 13
6.6 Electrical Characteristics.......................................... 5 12.2 Related Links ........................................................ 13
6.7 Switching Characteristics......................................... 6 12.3 Receiving Notification of Documentation Updates 13
6.8 Typical Characteristics .............................................. 7 12.4 Community Resources.......................................... 13
7 Parameter Measurement Information .................. 8 12.5 Trademarks ........................................................... 13
12.6 Electrostatic Discharge Caution ............................ 13
8 Detailed Description .............................................. 9
12.7 Glossary ................................................................ 13
8.1 Overview .................................................................. 9
8.2 Functional Block Diagram ......................................... 9 13 Mechanical, Packaging, and Orderable
Information ........................................................... 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (August 2003) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Removed Ordering Information table ..................................................................................................................................... 1
• Updated values in the Thermal Information tables to align with JEDEC standards............................................................... 5

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5 Pin Configuration and Functions

D, DB, J, N, NS, PW, W Package

14-Pin SOIC, SSOP, CDIP, PDIP, SOP, TSSOP, CFP FK Package
Top View 20-Pin LCCC
Top View

VCC
NC
1B

1A

4B
1A 1 14 VCC

1B 2 13 4B

20

19
1Y 3 12 4A

2A 4 11 4Y 1Y 4 18 4A

2B 5 10 3B NC 5 17 NC

2Y 6 9 3A 2A 6 16 4Y

GND 7 8 3Y
NC 7 15 NC

2B 8 14 3B

Not to scale

10

11

12

13
9
Not to scale

2Y

GND

NC

3Y

3A
Pin Functions
PIN
D, DB, J, N, I/O DESCRIPTION
NAME FK
NS, PW, W
1A 1 2 I Gate 1 input A
1B 2 3 I Gate 1 input B
1Y 3 4 O Gate 1 output
2A 4 6 I Gate 2 input A
2B 5 8 I Gate 2 input B
2Y 6 9 O Gate 2 output
3A 9 13 I Gate 3 input A
3B 10 14 I Gate 3 input B
3Y 8 12 O Gate 3 output
4A 12 18 I Gate 4 input A
4B 13 19 I Gate 4 input B
4Y 11 16 O Gate 4 output
GND 7 10 — Ground
1, 5, 7,
NC — — No internal connection
11, 15, 17
VCC 14 20 — Power supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
IIK Input clamp current VI < 0 or VI > VCC ±20 mA
IOK Output clamp current (2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings: SN74HC32

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
∆t/∆v Input transition rise or fall time VCC = 4.5 V 500 ns
VCC = 6 V 400
SN54HC32 –55 125
TA Operating free-air temperature °C
SN74HC32 –40 85

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to Implications of Slow or Floating
CMOS Inputs application report.

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6.4 Thermal Information: SN54HC32

SN54HC32
THERMAL METRIC (1) CDIP (J) CFP (W) LCCC (FK) UNIT
14 PINS 14 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance — — — °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.9 88.3 61 °C/W
RθJB Junction-to-board thermal resistance 80.1 156 59.6 °C/W
ψJT Junction-to-top characterization parameter — — — °C/W
ψJB Junction-to-board characterization parameter — — — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 25.1 15.2 11.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Thermal Information: SN74HC32

SN74HC32
(1)
THERMAL METRIC SOIC (D) SSOP (DB) PDIP (N) SOP (NS) TSSOP (PW) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-ambient
RθJA 90.1 105.4 54.9 88.8 119.6 °C/W
thermal resistance
Junction-to-case (top)
RθJC(top) 50.3 57.3 42.5 46.5 48.4 °C/W
thermal resistance
Junction-to-board
RθJB 44.4 52.7 34.7 47.6 61.3 °C/W
thermal resistance
Junction-to-top
ψJT 17.9 22.6 27.9 16.8 5.6 °C/W
characterization parameter
Junction-to-board
ψJB 44.1 52.2 34.6 47.2 60.7 °C/W
characterization parameter
Junction-to-case (bottom)
RθJC(bot) — — — — — °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 2 V 1.9 1.998
IOH = –20 µA VCC = 4.5 V 4.4 4.499
VCC = 6 V 5.9 5.999
TA = 25°C 3.98 4.3
VOH VI = VIH or VIL IOH = –4 mA, VCC = 4.5 V SN54HC32 3.7 V
SN74HC32 3.84
TA = 25°C 5.48 5.8
IOH = –5.2 mA, VCC = 6 V SN54HC32 5.2
SN74HC32 5.34

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 2 V 0.002 0.1
IOL = 20 µA VCC = 4.5 V 0.001 0.1
VCC = 6 V 0.001 0.1
TA = 25°C 0.17 0.26
VOL VI = VIH or VIL IOL = 4 mA, VCC = 4.5 V SN54HC32 0.4 V
SN74HC32 0.33
TA = 25°C 0.15 0.26
IOL = 5.2 mA, VCC = 6 V SN54HC32 0.4
SN74HC32 0.33
TA = 25°C ±0.1 ±100
II VI = VCC or 0, VCC = 6 V nA
SNx4HC32 ±1000
TA = 25°C 2
ICC VI = VCC or 0, IO = 0, VCC = 6 V SN54HC32 40 µA
SN74HC32 20
Ci VCC = 2 V to 6 V 3 10 pF
Power dissipation
Cpd capacitance TA = 25°C, no load 20 pF
per gate

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted; see Figure 4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25°C 50 100
VCC = 2 V SN54HC32 150
SN74HC32 125
TA = 25°C 10 20
CL = 50 pF, from A or B (input)
tpd VCC = 4.5 V SN54HC32 30 ns
to Y (output)
SN74HC32 25
TA = 25°C 8 17
VCC = 6 V SN54HC32 25
SN74HC32 21
TA = 25°C 38 75
VCC = 2 V SN54HC32 110
SN74HC32 95
TA = 25°C 8 15
tt CL = 50 pF, to Y (output) VCC = 4.5 V SN54HC32 22 ns
SN74HC32 19
TA = 25°C 6 13
VCC = 6 V SN54HC32 19
SN74HC32 16

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6.8 Typical Characteristics

TA = 25°C and CL = 50 pF
80

70

tt (max)(ns) 60

40 TA = 25oC
CL = 50 pF

20

10

0 2 4 5 6
Vcc
Figure 1. tt vs VCC

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7 Parameter Measurement Information

From Output Test
Under Test Point
CL = 50 pF
(see Note A)

Figure 2. Load Current

VCC
Input 90% 90%
50% 50%
10% 10% 0 V
tr tf

Figure 3. Input Rise and Fall Times

VCC
Input 50% 50%
0V
tPLH tPHL

In-Phase VOH
90% 90%
Output 50% 50%
10% 10%
VOL
tr tf
tPHL tPLH
VOH
Out-of-Phase 90% 90%
50% 50%
Output 10% 10%
VOL
tf tr

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationship between waveforms were chosen arbitrarily. All input pulses are supplied
by generators having the following characteristics:
PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurements.
D. tPLH and tPHL are the same as tpd.

Figure 4. Propagation Delay and Output Transition Times

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8 Detailed Description

8.1 Overview
The SNx4HC32 devices are quad 2-input OR gates. These devices are members of the High-Speed CMOS (HC)
logic family. The HC family of logic is optimized to operate with a 5-V supply, is low noise without characteristic
overshoot and undershoot, has low power consumption, small propagation delay, balanced propagation delay
and transition times, and operates over a wide temperature range.

8.2 Functional Block Diagram

A
Y
B
Copyright © 2016, Texas Instruments Incorporated

Figure 5. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Operating Voltage Range
The SNx4HC series of devices offer a wide operating voltage range from 2 V to 6 V.

8.3.2 LSTTL Loads

The outputs of the SNx4HC series can drive up to 10 LSTTL loads.

8.3.3 Low Power Consumption

The SNx4HC32 offers low power consumption of 20 μA (maximum).

8.3.4 Output Drive Capability

At 5 V, the outputs have ±4 mA of output drive capability.

8.3.5 Low Input Current Leakage

Inputs have low input current leakage of 1 μA (maximum).

8.4 Device Functional Modes

Table 1 lists the functional modes of SNx4HC32.

Table 1. Function Table

(Each Gate)
INPUTS OUTPUT
A B Y
H X H
X H H
L L L

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SNx4HC32 is an extremely versatile device with far more available applications than could be listed here.
The application chosen as an example is using all four OR gates in a single package to provide a four channel
output enable from a single active low enable signal (Enable). This circuit outputs a logic HIGH on all channels
when disabled (Enable is HIGH), and passes the input signals when enabled (Enable is LOW).

9.2 Typical Application

VCC

0.1 PF
Enable
Output 1
Input 1

Output 2
Input 2

Output 3
Input 3

Output 4
Input 4

Copyright © 2016, Texas Instruments Incorporated

Using a quad OR gate as a 4-channel active low enable with high output off state.

Figure 6. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions must be considered to prevent ringing.
The minimum output pulse time is approximately three times tpd from Switching Characteristics for the selected
VCC, device, and temperature range.

9.2.2 Detailed Design Procedure

Logic
• All four input channels are to be enabled or disabled simultaneously
• The enable signal is active low (LOW = enabled, HIGH = disabled)
• All four outputs are to output logic HIGH while disabled
Inputs
• Each input must follow requirements specified in Absolute Maximum Ratings:
– Avoid exceeding input voltages

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Typical Application (continued)

– If input voltages ratings must be exceeded, ensure that the maximum input current ratings are not
exceeded.
– Ensure that the input signals have edge rates that are equal to or faster than that listed in Recommended
Operating Conditions. Slower signals can cause incorrect behavior and possibly damage to the part.
• Each output must also follow requirements in Absolute Maximum Ratings:
– Avoid bus contention by only connecting outputs together when inputs are tied together directly.
– Avoid forcing output voltages outside those specified in Absolute Maximum Ratings.
– If output voltage ratings must be exceeded, ensure that the maximum output current ratings are not
exceeded.
– Ensure that the total current output does not exceed the continuous current through VCC or GND listed in
Absolute Maximum Ratings.

9.2.3 Application Curves

Enable

Input x

Output x
Dotted lines indicate Enable signal changes

Figure 7. Application Timing Diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF bypass capacitor. If there are multiple
VCC pins, TI recommends a 0.01-μF or 0.022-μF bypass capacitors for each power pin. It is acceptable to parallel
multiple bypass capacitors to reject different frequencies of noise. Two bypass capacitors of value 0.1-μF and 1-
μF are commonly used in parallel. For best results, install the bypass capacitor(s) as close to the power pin as
possible.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. Specified in Absolute
Maximum Ratings are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the outputs section of the part when asserted.
This does not disable the input section of the I/Os so they also cannot float when disabled.

11.2 Layout Example

Figure 8. Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs (SCBA004)

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54HC32 Click here Click here Click here Click here Click here
SN74HC32 Click here Click here Click here Click here Click here

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

5962-8404501VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8404501VC
A
SNV54HC32J
5962-8404501VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8404501VD
A
SNV54HC32W
84045012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84045012A
SNJ54HC
32FK
8404501CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501CA
SNJ54HC32J
8404501DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501DA
SNJ54HC32W
JM38510/65201B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
65201B2A
JM38510/65201BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BCA
JM38510/65201BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BDA
M38510/65201B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
65201B2A
M38510/65201BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BCA
M38510/65201BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BDA
SN54HC32J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC32J

SN74HC32D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32

& no Sb/Br)
SN74HC32DBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74HC32DRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32N ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC32N
& no Sb/Br)
SN74HC32NE4 ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC32N
& no Sb/Br)
SN74HC32NSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SNJ54HC32FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84045012A
SNJ54HC
32FK
SNJ54HC32J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501CA
SNJ54HC32J
SNJ54HC32W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501DA
SNJ54HC32W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC32, SN54HC32-SP, SN74HC32 :

• Catalog: SN74HC32, SN54HC32

• Military: SN54HC32
• Space: SN54HC32-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

• Military - QML certified for Military and Defense Applications

• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC32PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC32PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC32PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC32DR SOIC D 14 2500 333.2 345.9 28.6
SN74HC32DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC32DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC32DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC32DRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74HC32DT SOIC D 14 250 210.0 185.0 35.0
SN74HC32PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74HC32PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74HC32PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74HC32PWT TSSOP PW 14 250 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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