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SN54HC14, SN74HC14
SCLS085J – DECEMBER 1982 – REVISED OCTOBER 2016

SNx4HC14 Hex Schmitt-Trigger Inverters

1 Features 3 Description
•
1 Wide Operating Voltage Range of 2 V to 6 V The SNx4HC14 are Schmitt-trigger devices that
contain six independent inverters. They perform the
• Outputs Can Drive Up to 10 LSTTL Loads Boolean function Y = A in positive logic.
• Low Power Consumption, 20-μA Max ICC
• Typical tpd = 11 ns Device Information(1)
• ±4-mA Output Drive at 5 V PART NUMBER PACKAGE BODY SIZE (NOM)

• Low Input Current of 1 μA Max SNJ54HC14J CDIP (14) 7.62 mm x 19.94 mm

SNJ54HC14W CFP (14) 7.11 mm x 9.11 mm
• On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise SNJ54HC14FK LCCC (20) 8.89 mm x 8.89 mm
Noted. On All Other Products, Production SN74HC14D SOIC (14) 6.00 mm x 8.65 mm
Processing Does Not Necessarily Include Testing SN74HC14DB SSOP (14) 367.00 mm x 367.00 mm
of All Parameters. SN74HC14N PDIP (14) 7.94 mm x 10.35 mm
SN74HC14NS SO (14) 7.80 mm x 10.20 mm
2 Applications SN74HC14PW TSSOP (14) 6.40 mm x 5.00 mm
• Microwave Oven (1) For all available packages, see the orderable addendum at
• Mice the end of the data sheet.

• Printers
• AC Inverter Drives
• UPS
• AC Servo Drives
• Other Motor Drives
Logic Diagram (Positive Logic)

A Y

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC14, SN74HC14
SCLS085J – DECEMBER 1982 – REVISED OCTOBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 8
2 Applications ........................................................... 1 8.4 Device Functional Modes.......................................... 8
3 Description ............................................................. 1 9 Application and Implementation .......................... 9
4 Revision History..................................................... 2 9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 10
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 11
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 11
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 11
6.4 Thermal Information .................................................. 4 12 Device and Documentation Support ................. 12
6.5 Electrical Characteristics........................................... 5 12.1 Documentation Support ........................................ 12
6.6 Switching Characteristics .......................................... 5 12.2 Related Links ........................................................ 12
6.7 Operating Characteristics.......................................... 5 12.3 Receiving Notification of Documentation Updates 12
6.8 Typical Characteristics .............................................. 6 12.4 Community Resources.......................................... 12
7 Parameter Measurement Information .................. 7 12.5 Trademarks ........................................................... 12
12.6 Electrostatic Discharge Caution ............................ 12
8 Detailed Description .............................................. 8
12.7 Glossary ................................................................ 12
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision I (February 2016) to Revision J Page

• Changed " Y = A" to "Y = A" throughout ................................................................................................................................ 1

• Added The SNx4HC14 to Description section ....................................................................................................................... 1
• Deleted Device Comparison Table section ............................................................................................................................ 1
• Added Receiving Notification of Documentation Updates section ....................................................................................... 12

Changes from Revision H (September 2015) to Revision I Page

• Changed part number from SN54HC08 to SN54HC14 in Switching Characteristics table.................................................... 5

• Changed part number from SN74HC08 to SN74HC14 in Switching Characteristics table.................................................... 5

Changes from Revision G (January 2014) to Revision H Page

• Added Applications ................................................................................................................................................................. 1

• Added Military Disclaimer to Features list. ............................................................................................................................. 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision F (December 2010) to Revision G Page

• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

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5 Pin Configuration and Functions

SN54HC14 J or W Package
SN74HC14 D, DB, N, NS, or PW Package SN54HC14 FK Package
14-Pin CDIP, CFP, SOIC, SSOP, PDIP, SO, or TSSOP 20-Pin LCCC
Top View Top View

VCC
NC
1Y
1A

6A
1A 1 14 VCC
1Y 2 13 6A 3 2 1 20 19
2A 3 12 6Y 2A 4 18 6Y
2Y 4 11 5A NC 5 17 NC
3A 5 10 5Y 2Y 6 16 5A
3Y 6 9 4A NC 7 15 NC
GND 7 8 4Y 3A 8 14 5Y
9 10 11 12 13

NC
3Y

4Y
4A
GND
Pin Functions
PIN
CDIP, CFP,
SOIC, SSOP, I/O DESCRIPTION
NAME LCCC
PDIP, SO,
TSSOP
1A 1 2 I Channel 1 input
1Y 2 3 O Channel 1 output
2A 3 4 I Channel 2 input
2Y 4 6 O Channel 2 output
3A 5 8 I Channel 3 input
3Y 6 9 O Channel 3 output
GND 7 10 — Ground
4Y 8 12 O Channel 4 output
4A 9 13 I Channel 4 input
5Y 10 14 O Channel 5 output
5A 11 16 I Channel 5 input
6Y 12 18 O Channel 6 output
6A 13 19 I Channel 6 input
VCC 14 20 — Power supply
1
5
7
NC (1) — — No internal connection
11
15
17

(1) NC – No internal connection

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
(2)
IIK Input clamp current VI < 0 or VI > VCC ±20 mA
IOK Output clamp current (2) VO < 0 ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
Tj Junction temperature 150
°C
Tstg Storage temperature –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

See note (1).
SN54HC14 SN74HC14
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
TA Operating free-air temperature –55 125 –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

6.4 Thermal Information

SNx4HC14
THERMAL METRIC (1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 86 96 80 76 113 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HC14 SN74HC14
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 0.7 1.2 1.5 0.7 1.5 0.7 1.5
VT+ 4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 V
6V 2.1 3.3 4.2 2.1 4.2 2.1 4.2
2V 0.3 0.6 1 0.3 1 0.3 1
VT− 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 V
6V 1.2 2 3.2 1.2 3.2 1.2 3.2
2V 0.2 0.6 1.2 0.2 1.2 0.2 1.2
VT+ − VT− 4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 V
6V 0.5 1.3 2.5 0.5 2.5 0.5 2.5
2V 1.9 1.998 1.9 1.9
IOH = –20 μA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 μA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 2 40 20 μA
Ci 2 V to 6 V 3 10 10 10 pF

6.6 Switching Characteristics

over operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3)
FROM TO TA = 25°C SN54HC14 SN74HC14
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 55 125 190 155
tpd A Y 4.5 V 12 25 38 31 ns
6V 11 21 22 26
2V 38 75 110 95
tt Y 4.5 V 8 15 22 19 ns
6V 6 13 19 16

6.7 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per inverter No load 20 pF

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6.8 Typical Characteristics

14.5 70

14 60

50
13.5

TPD (ns)
TPD (ns)

40
13
30
12.5
20

12 10

11.5 0
-100 -50 0 50 100 150 0 2 4 6 8
Temperature D001
VCC D002
Figure 1. TPD vs Temperature at 4.5 V, 25°C Figure 2. TPD vs VCC at 25°C

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7 Parameter Measurement Information

VCC
From Output Test Input
Under Test Point 50% 50%
0V
CL= 50 pF
(see Note A) tPLH tPHL

VOH
In-Phase 90% 90%
LOAD CIRCUIT 50% 50%
Output 10% 10%
VOL
tr tf
VCC tPHL tPLH
90% 90%
Input 50% 50% VOH
10% 10% Out-of-Phase 90% 50% 90%
0V 50%
Output 10% 10%
VOL
tr tf tf tr

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

Figure 3. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A in
positive logic.
Schmitt-trigger inputs are designed to provide a minimum separation between positive and negative switching
thresholds. This allows for noisy or slow inputs that would cause problems such as oscillation or excessive
current draw with normal CMOS inputs.

8.2 Functional Block Diagram

A Y

Figure 4. Logic Diagram (Positive Logic)

8.3 Feature Description

The wide operating range of the device allows it to be used in a variety of systems that use different logic levels.
The outputs can drive up to 10 LSTTL loads each. The device has very low power consumption, with 20-μA Max
ICC. Typical propagation delay is also low at 11 ns. The balanced drive outputs can source or sink 4 mA at 5-V
VCC. The input leakage current is 1 μA Max.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SNx4HC14.

Table 1. Function Table (Each Inverter)

INPUTS OUTPUT
A Y
H L
L H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SNx4HC14 are Schmitt-trigger input CMOS devices that can be used for a multitude of inverting buffer type
functions. The application shown in Figure 5 takes advantage of the Schmitt-trigger inputs to produce a delay for
a logic output.

9.2 Typical Application

R1
INPUT 1A 1Y 2A 2Y OUTPUT
C1

Figure 5. Simplified Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology. Take care to avoid bus contention because it can drive currents that would
exceed maximum limits. Parallel output drive can create fast edges into light loads so consider routing and load
conditions to prevent ringing.

9.2.2 Detailed Design Procedure

This circuit is designed around an RC network that produces a slow input to the second inverter. The RC time
constant, τ, is calculated from: τ = R×C
The delay time for this circuit is between 1.2τ and 0.42τ. The delay is consistent for each device, but because the
switching threshold is only guaranteed between a minimum and maximum value, the output pulse length varies
between the devices. These values were calculated by using the minimum and maximum guaranteed VT+ values.
The resistor value should be chosen such that the maximum current from and to the SNx4HC14 is 4 mA.
• Recommended input conditions:
– Schmitt-trigger inputs allow for slow inputs.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
• Recommended output conditions:
– Load currents should not exceed 4 mA per output.

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Typical Application (continued)

9.2.3 Application Curve

5.0

4.5

4.0

3.5

3.0
Voltage (V)

VT+ Typical
2.5
VT+

2.0

1.5
Max Delay Time = 1.202 VC
1.0
Min Delay Time = 0.422 VOUT
0.5

0.0
t0 t0 + 2 t0 + 22 t0 + 32 t0 + 42 t0 + 52
Time

Figure 6. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold Range
Representation

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC
terminals, then TI recommends a 0.01-µF or 0.022-µF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal
for best results.

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11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should never float. In many cases, functions or parts of functions of
digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC whichever makes more sense or is more convenient. Floating outputs is generally acceptable, unless the
part is a transceiver.

11.2 Layout Example

Figure 7. Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54HC05 Click here Click here Click here Click here Click here
SN74HC05 Click here Click here Click here Click here Click here

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8409101VCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8409101VC
& Green A
SNV54HC14J
5962-8409101VDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8409101VD
& Green A
SNV54HC14W
84091012A ACTIVE LCCC FK 20 1 Non-RoHS POST-PLATE N / A for Pkg Type -55 to 125 84091012A
& Green SNJ54HC
14FK
8409101CA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101CA
& Green SNJ54HC14J
8409101DA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101DA
& Green SNJ54HC14W
JM38510/65702BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65702BCA
JM38510/65702BDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65702BDA
M38510/65702BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65702BCA
M38510/65702BDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/
& Green 65702BDA
SN54HC14J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC14J
& Green
SN74HC14D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 HC14

Addendum-Page 1
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC14DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14DTG4 ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -40 to 85 SN74HC14N

SN74HC14NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC14N

SN74HC14NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14NSRE4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PWE4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SN74HC14PWTG4 ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC14

SNJ54HC14FK ACTIVE LCCC FK 20 1 Non-RoHS POST-PLATE N / A for Pkg Type -55 to 125 84091012A
& Green SNJ54HC
14FK
SNJ54HC14J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101CA
& Green SNJ54HC14J
SNJ54HC14W ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409101DA
& Green SNJ54HC14W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 2
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OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC14, SN54HC14-SP, SN74HC14 :

• Catalog: SN74HC14, SN54HC14

• Automotive: SN74HC14-Q1, SN74HC14-Q1
• Military: SN54HC14
• Space: SN54HC14-SP

NOTE: Qualified Version Definitions:

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Feb-2021

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC14DR SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC14DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC14DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC14DRG3 SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC14DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC14DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC14DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC14NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC14PWR TSSOP PW 14 2000 330.0 16.4 6.8 5.4 1.6 8.0 16.0 Q1
SN74HC14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC14PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC14PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jan-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC14DR SOIC D 14 2500 366.0 364.0 50.0
SN74HC14DR SOIC D 14 2500 853.0 449.0 35.0
SN74HC14DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC14DRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74HC14DRG3 SOIC D 14 2500 366.0 364.0 50.0
SN74HC14DRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74HC14DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC14DT SOIC D 14 250 210.0 185.0 35.0
SN74HC14NSR SO NS 14 2000 367.0 367.0 38.0
SN74HC14PWR TSSOP PW 14 2000 366.0 364.0 50.0
SN74HC14PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74HC14PWRG4 TSSOP PW 14 2000 853.0 449.0 35.0
SN74HC14PWT TSSOP PW 14 250 853.0 449.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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