TPA2011D1 3.2-W Mono Filter-Free Class-D Audio Power Amplifier With Auto-Recovering Short-Circuit Protection

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TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015

TPA2011D1 3.2-W Mono Filter-Free Class-D Audio Power Amplifier


With Auto-Recovering Short-Circuit Protection
1 Features 3 Description
1• Powerful Mono Class-D Amplifier The TPA2011D1 is a 3.2-W high efficiency filter-free
class-D audio power amplifier (class-D amp) in a
– 3.24 W (4 Ω, 5 V, 10% THDN) 1.21 mm × 1.16 mm wafer chip scale package
– 2.57 W (4 Ω, 5 V, 1% THDN) (DSBGA) that requires only three external
– 1.80 W (8 Ω, 5 V, 10% THDN) components.
– 1.46 W (8 Ω, 5 V, 1% THDN) Features like 95% efficiency, 86-dB PSRR, 1.5 mA
• Integrated Feedback Resistor of 300 kΩ quiescent current and improved RF immunity make
the TPA2011D1 class-D amp ideal for cellular
• Integrated Image Reject Filter for DAC Noise handsets. A fast start-up time of 4 ms with no audible
Reduction turn-on pop makes the TPA2011D1 ideal for PDA
• Low Output Noise of 20 μV and smart-phone applications. The TPA2011D1
• Low Quiescent Current of 1.5 mA allows independent gain while summing signals from
separate sources, and has a low 20 μV noise floor.
• Auto Recovering Short-Circuit Protection
• Thermal Overload Protection Device Information(1)
• 9-Ball, 1.21mm x 1.16 mm 0.4 mm Pitch DSBGA PART NUMBER PACKAGE BODY SIZE (NOM)
TPA2011D1 DSBGA (9) 1.60 mm x 1.21 mm
2 Applications (1) For all available packages, see the orderable addendum at
• Wireless or Cellular Handsets and PDAs the end of the data sheet.
• Portable Navigation Devices
• General Portable Audio Devices
Typical Application Diagram

EN

TPA2011D1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 13
2 Applications ........................................................... 1 9.3 Feature Description................................................. 13
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 15
4 Revision History..................................................... 2 10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
5 Device Comparison Table..................................... 3
10.2 Typical Applications .............................................. 18
6 Pin Configuration and Functions ......................... 4
11 Power Supply Recommendations ..................... 21
7 Specifications......................................................... 4
11.1 Power Supply Decoupling Capacitors................... 21
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 5 12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
7.3 Recommended Operating Conditions....................... 5
12.2 Layout Example .................................................... 23
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 5 13 Device and Documentation Support ................. 24
7.6 Operating Characteristics.......................................... 6 13.1 Community Resources.......................................... 24
7.7 Dissipation Ratings ................................................... 6 13.2 Trademarks ........................................................... 24
7.8 Typical Characteristics .............................................. 7 13.3 Electrostatic Discharge Caution ............................ 24
13.4 Glossary ................................................................ 24
8 Parameter Measurement Information ................ 12
9 Detailed Description ............................................ 13 14 Mechanical, Packaging, and Orderable
Information ........................................................... 24
9.1 Overview ................................................................. 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2010) to Revision B Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1

Changes from Original (December 2009) to Revision A Page

• Changed the Package Dimensions table. D was Max = 1244μm, Min = 1184μm. E was Max = 1190μm, Min =
1130μm .................................................................................................................................................................................. 1

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5 Device Comparison Table

SPEAKER SPEAKER AMP


DEVICE NUMBER OUTPUT POWER (W) PSRR (dB)
CHANNELS TYPE
TPA2011D1 Mono Class D 3.2 86
TPA2005D1 Mono Class D 1.4 75
TPA2010D1 Mono Class D 2.5 75

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6 Pin Configuration and Functions

YFF Package
9-Pin DSBGA
Top View

IN+ GND VO-

A1 A2 A3

VDD PVDD PGND

1.160 mm
B1 B2 B3

IN- EN VO+

C1 C2 C3

1.214 mm

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
EN C2 I Shutdown terminal. When terminal is low the device is put into Shutdown mode.
Analog ground terminal. Must be connected to same potential as PGND using a direct connection
GND A2 I
to a single point ground.
IN– C1 I Negative differential audio input
IN+ A1 I Positive differential audio input
High-current Analog ground terminal. Must be connected to same potential as GND using a direct
PGND B3 I
connection to a single point ground.
High-current Power supply terminal. Must be connected to same power supply as VDD using a
PVDD B2 I direct connection. Voltage must be within values listed in Recommended Operating Conditions
table.
Power supply terminal. Must be connected to same power supply as PVDD using a direct
VDD B1 I
connection. Voltage must be within values listed in Recommended Operating Conditions table.
VO- A3 O Negative BTL audio output
VO+ C3 O Positive BTL audio output

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
Supply In active mode –0.3 6 V
VDD, PVDD
voltage In shutdown mode –0.3 6 V
VI Input EN, IN+, IN– V
–0.3 VDD + 0.3
voltage
RL Minimum load resistance 3.2 Ω
Output continuous total power dissipation See Dissipation Ratings
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Tstg Storage temperature –65 85 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
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7.2 ESD Ratings


VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions


MIN MAX UNIT
VDD Class-D supply voltage 2.5 5.5 V
VIH High-level input voltage EN 1.3 V
VIL Low-level input voltage EN 0.35 V
RI Input resistor Gain ≤ 20 V/V (26 dB) 15 kΩ
VIC Common mode input voltage range VDD = 2.5V, 5.5V, CMRR ≥ 49 dB 0.75 VDD-1.1 V
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information


TPA2011D1
THERMAL METRIC (1) YFF (DSBGA) UNIT
9 PINS
RθJA Junction-to-ambient thermal resistance 107 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 18.1 °C/W
ψJT Junction-to-top characterization parameter 3.8 °C/W
ψJB Junction-to-board characterization parameter 18 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

7.5 Electrical Characteristics


TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output offset voltage (measured
|VOS| VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V 1 5 mV
differentially)
|IIH| High-level input current VDD = 5.5 V, VEN = 5.5 V 50 μA
|IIL| Low-level input current VDD = 5.5 V, VEN = 0 V 1 μA
VDD = 5.5 V, no load 1.8 2.5
I(Q) Quiescent current VDD = 3.6 V, no load 1.5 2.3 mA
VDD = 2.5 V, no load 1.3 2.1
I(SD) Shutdown current VEN = 0.35 V, VDD = 2.5 V to 5.5 V 0.1 2 μA
RO, SD Output impedance in shutdown mode VEN = 0.35 V 2 kΩ
f(SW) Switching frequency VDD = 2.5 V to 5.5 V 250 300 350 kHz
AV Gain VDD = 2.5 V to 5.5 V, RI in kΩ 285/RI 300/RI 315/RI V/V
REN Resistance from EN to GND 300 kΩ

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7.6 Operating Characteristics


VDD = 3.6 V, TA = 25°C, AV = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5 V 3.24
THD + N = 10%, f = 1 kHz, RL = 4 Ω VDD = 3.6 V 1.62 W
VDD = 2.5 V 0.70
VDD = 5 V 2.57
THD + N = 1%, f = 1 kHz, RL = 4 Ω VDD = 3.6 V 1.32 W
VDD = 2.5 V 0.57
PO Output power
VDD = 5 V 1.80
THD + N = 10%, f = 1 kHz, RL = 8 Ω VDD = 3.6 V 0.91 W
VDD = 2.5 V 0.42
VDD = 5 V 1.46
THD + N = 1%, f = 1 kHz, RL = 8 Ω VDD = 3.6 V 0.74 W
VDD = 2.5 V 0.33
VDD = 3.6 V, Inputs AC grounded A-weighting 20
Vn Noise output voltage with CI = 2μF, f = 20 Hz to 20 kHz μVRMS
No weighting 25
VDD = 5.0 V, PO = 1.0 W, f = 1 kHz, RL = 8 Ω 0.11%
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz, RL = 8 Ω 0.05%
Total harmonic distortion VDD = 2.5 V, PO = 0.2 W, f = 1 kHz, RL = 8 Ω 0.05%
THD+N
plus noise VDD = 5.0 V, PO = 2.0 W, f = 1 kHz, RL = 4 Ω 0.23%
VDD = 3.6 V, PO = 1.0 W, f = 1 kHz, RL = 4 Ω 0.07%
VDD = 2.5 V, PO = 0.4 W, f = 1 kHz, RL = 4 Ω 0.06%
AC power supply rejection VDD = 3.6 V, Inputs AC grounded with CI = 2 μF,
PSRR 86 dB
ratio 200 mVpp ripple, f = 217 Hz
CMRR Common mode rejection VDD = 3.6 V, VIC = 1 VPP, f = 217 Hz 79 dB
ratio
TSU Startup time from VDD = 3.6 V 4 ms
shutdown
VDD = 3.6 V, VO+ shorted to VDD 2
VDD = 3.6 V, VO– shorted to VDD 2
Overcurrent protection
IOC VDD = 3.6 V, VO+ shorted to GND 2 A
threshold
VDD = 3.6 V, VO– shorted to GND 2
VDD = 3.6 V, VO+ shorted to VO– 2
Time for which output is
disabled after a short-
TSD circuit event, after which VDD = 2.5 V to 5.5 V 100 ms
auto-recovery trials are
continuously made

7.7 Dissipation Ratings


PACKAGE DERATING FACTOR (1) TA < 25°C TA = 70°C TA = 85°C
YFF (DSBGA) 4.2 mW/°C 525 mW 336 mW 273 mW

(1) Derating factor measure with high K board.

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7.8 Typical Characteristics


VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)

100 100

90 90

80 80

70 70
η − Efficiency − %

η − Efficiency − %
60 60

50 50

40 40
RL = 8 Ω + 33 µH RL = 4 Ω + 33 µH
30 Gain = 6 dB 30 Gain = 6 dB
20 20
VDD = 2.5 V VDD = 2.5 V
10 VDD = 3.6 V 10 VDD = 3.6 V
VDD = 5.0 V VDD = 5.0 V
0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
PO − Output Power − W PO − Output Power − W

Figure 1. Efficiency vs Output Power Figure 2. Efficiency vs Output Power


0.4 0.6
RL = 8 Ω + 33 µH VDD = 3.6 V RL = 8 Ω + 33 µH VDD = 5.0 V
RL = 4 Ω + 33 µH Gain = 6 dB RL = 4 Ω + 33 µH Gain = 6 dB
0.5
PD − Power Dissipation − W

PD − Power Dissipation − W
0.3
0.4

0.2 0.3

0.2
0.1
0.1

0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
PO − Output Power − W PO − Output Power − W

Figure 3. Power Dissipation vs Output Power Figure 4. Power Dissipation vs Output Power
1.0 0.5
VDD = 2.5 V RL = 4 Ω + 33 µH VDD = 2.5 V RL = 8 Ω + 33 µH
0.9 VDD = 3.6 V Gain = 6 dB VDD = 3.6 V Gain = 6 dB
VDD = 5.0 V VDD = 5.0 V
0.8 0.4
IDD − Supply Current − A

IDD − Supply Current − A

0.7

0.6 0.3

0.5

0.4 0.2

0.3

0.2 0.1

0.1

0.0 0.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
PO − Output Power − W PO − Output Power − W

Figure 5. Supply Current vs Output Power Figure 6. Supply Current vs Output Power

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Typical Characteristics (continued)


VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
2.00 200
RL = No Load Gain = 6 dB VDD = 2.5 V Gain = 6 dB
RL = 8 Ω + 33 µH VDD = 3.6 V
RL = 4 Ω + 33 µH VDD = 5.0 V
IDD − Supply Current − mA

1.75 150

IDD − Supply Current − nA


1.50 100

1.25 50

1.00 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.1 0.2 0.3 0.4 0.5
VDD − Supply Voltage − V VEN − EN Voltage − V

Figure 7. Supply Current vs Supply Voltage Figure 8. Supply Current vs EN Voltage


5 4
THD+N = 10 % VDD = 2.5 V THD+N = 1 % VDD = 2.5 V
Frequency = 1 kHz VDD = 3.6 V Frequency = 1 kHz VDD = 3.6 V
Gain = 6 dB VDD = 5.0 V Gain = 6 dB VDD = 5.0 V
4
3
PO − Output Power − W

3 PO − Output Power − W
2
2

1
1

0 0
4 8 12 16 20 24 28 32 4 8 12 16 20 24 28 32
RL − Load Resistance − Ω RL − Load Resistance − Ω
Figure 9. Output Power vs Load Resistance Figure 10. Output Power vs Load Resistance
4
RL = 4 Ω, THD+N = 1 %
RL = 4 Ω, THD+N = 10 %
RL = 8 Ω, THD+N = 1 %
RL = 8 Ω, THD+N = 10 %
3
PO − Output Power − W

Frequency = 1 kHz
Gain = 6 dB
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD − Supply Voltage − V
Figure 11. Output Power vs Supply Resistance Figure 12. THD + Noise vs Output Power

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Typical Characteristics (continued)


VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
10

THD+N − Total Harmonic Distortion + Noise − %


VDD = 5.0 V PO = 50 mW
RL = 8 Ω + 33 µH PO = 250 mW
Gain = 6 dB PO = 1 W
1

0.1

0.01

0.001
20 100 1k 10k 20k
f − Frequency − Hz

Figure 13. THD + Noise vs Output Power Figure 14. THD + Noise vs Frequency
10 10
THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %


VDD = 3.6 V PO = 25 mW VDD = 2.5 V PO = 15 mW
RL = 8 Ω + 33 µH PO = 125 mW RL = 8 Ω + 33 µH PO = 75 mW
Gain = 6 dB PO = 500 mW Gain = 6 dB PO = 200 mW
1 1

0.1 0.1

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 15. THD + Noise vs Frequency Figure 16. THD + Noise vs Frequency
10 10
THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

VDD = 5.0 V PO = 100 mW VDD = 3.6 V PO = 50 mW


RL = 4 Ω + 33 µH PO = 500 mW RL = 4 Ω + 33 µH PO = 250 mW
Gain = 6 dB PO = 2 W Gain = 6 dB PO = 1 W
1 1

0.1 0.1

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 17. THD + Noise vs Frequency Figure 18. THD + Noise vs Frequency

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Typical Characteristics (continued)


VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
10 10
THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %


VDD = 2.5 V PO = 30 mW RL = 8 Ω + 33 µH VDD = 2.5 V
RL = 4 Ω + 33 µH PO = 150 mW Frequency = 1 kHz VDD = 3.6 V
Gain = 6 dB PO = 400 mW PO = 200 mW VDD = 5.0 V
Gain = 6 dB
1
1

0.1

0.1
0.01

0.001 0.01
20 100 1k 10k 20k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
f − Frequency − Hz VIC − Common Mode Input Voltage − V

Figure 19. THD + Noise vs Frequency Figure 20. THD + Noise vs Common Mode Input Voltage
0 0
Inputs AC−Grounded VDD = 2.5 V Inputs AC−Grounded VDD = 2.5 V
PSRR − Power Supply Rejection Ratio − dB

PSRR − Power Supply Rejection Ratio − dB


−10 −10
CI = 2 µF VDD = 3.6 V CI = 2 µF VDD = 3.6 V
−20 RL = 8 Ω + 33 µH VDD = 5.0 V −20 RL = 4 Ω + 33 µH VDD = 5.0 V
Gain = 6 dB Gain = 6 dB
−30 −30
−40 −40
−50 −50
−60 −60
−70 −70
−80 −80
−90 −90
−100 −100
−110 −110
−120 −120
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 21. Power Supply Rejection Ratio vs Frequency Figure 22. Power Supply Rejection Ratio vs Frequency
0 −30
RL = 8 Ω + 33 µH
CMRR − Common Mode Rejection Ratio − dB

VDD = 2.5 V VIC = 1 VPP VDD = 2.5 V


PSRR − Power Supply Rejection Ratio − dB

−10 Frequency = 217 Hz VDD = 3.6 V RL = 8 Ω + 33 µH VDD = 3.6 V


VDD = 5.0 V −40 VDD = 5.0 V
Gain = 6 dB Gain = 6 dB
−20

−30 −50

−40
−60
−50
−70
−60

−70 −80
−80
−90
−90

−100 −100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 20 100 1k 10k 20k
VIC − Common Mode Input Voltage − V f − Frequency − Hz

Figure 23. Power Supply Rejection Ratio vs Common Mode Figure 24. Common Mode Rejection Ratio vs Frequency
Input Voltage

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Typical Characteristics (continued)


VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
0
RL = 8 Ω + 33 µH
CMRR − Common Mode Rejection Ratio − dB

VDD = 2.5 V
−10 Frequency = 217 Hz VDD = 3.6 V
Gain = 6 dB VDD = 5.0 V VDD
−20 High – 3.6 V
Amplitude – 500 mV
−30 Duty Cycle – 20%

−40

−50 VOUT
2 mV/div
−60

−70

−80 0 2.5m 5m 7.5m 10m 12.5m 15m 17.5m 20m


0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIC − Common Mode Input Voltage − V t – Time – 2.5ms/div
Figure 25. Common Mode Rejection Ratio vs Common Mode Figure 26. GSM Power Supply Rejection vs Time
Input Voltage

VDD - Supply Voltage (dBV)


VO - Output Voltage (dBV)

Inputs ac-grounded
Gain = 6 dB

Frequency (Hz)
Figure 27. GSM Power Supply Rejection vs Frequency

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8 Parameter Measurement Information


All parameters are measured according to the conditions described in the Specifications section.
CI RI
+ IN+ OUT+ +
30 kHz
Measurement Measurement
Output TPA2011D1 Load Low Pass
Input
CI RI Filter
- IN- -
OUT-
VDD GND

CS1

CS2

+
VDD
-

(1) Input resistor RI = 150kΩ gives a gain of 6 dB which is used for all the graphs
(2) CI was shorted for any common-mode input voltage measurement. All other measurements were taken with CI = 0.1-
μF (unless otherwise noted).
(3) CS1 = 0.1μF is placed very close to the device. The optional CS2 = 10μF is used for datasheet graphs.
(4) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low-pass filter (1kΩ,
4700pF) is used on each output for the data sheet graphs.

Figure 28. Test Setup for Typical Application Graphs

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9 Detailed Description

9.1 Overview
The TPA2011D1 is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 3.2W into 4-Ω
load with 5-V power supply. The fully-differential design of this amplifier avoids the usage of bypass capacitors
and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the device size a perfect
choice for small, portable applications as only three external components are required. The advanced modulation
used in the TPA2011D1 PWM output stage eliminates the need for an output filter.

9.2 Functional Block Diagram

Input
EN
Buffer SC

300 KΩ

9.3 Feature Description


9.3.1 Fully Differential Amplifier
The TPA2011D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2
regardless of the common-mode voltage at the input. The fully differential TPA2011D1 can still be used with a
single-ended input; however, the TPA2011D1 should be used with differential inputs when in a noisy
environment, like a wireless handset, to ensure maximum noise rejection.

9.3.1.1 Advantages of Fully Differential Amplifiers


• Input-coupling Capacitors Not Required
– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example,
if a codec has a midsupply lower than the midsupply of the TPA2011D1, the common-mode feedback
circuit will adjust, and the TPA2011D1 outputs will still be biased at midsupply of the TPA2011D1. The
inputs of the TPA2011D1 can be biased from 0.5 V to VDD –0.8 V. If the inputs are biased outside of that
range, input-coupling capacitors are required.
• Midsupply Bypass Capacitor, C(BYPASS), Not Required
– The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
• Better RF-Immunity
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The

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TPA2011D1
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Feature Description (continued)


transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal
much better than the typical audio amplifier.

9.3.2 Eliminating the Output Filter With the TPA2011D1


This section focuses on why the user can eliminate the output filter with the TPA2011D1.

9.3.2.1 Effect on Audio


The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.

9.3.2.2 When to Use an Output Filter

Design the TPA2011D1 without an Inductor / Capacitor (LC) output filter if the traces from the amplifier to the
speaker are short. Wireless handsets and PDAs are great applications for this class-D amplifier to be used
without an output filter.
The TPA2011D1 does not require an LC output filter for short speaker connections (approximately 100 mm long
or less). A ferrite bead can often be used in the design if failing radiated emissions testing without an LC filter;
and, the frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies. The selection must also take into
account the currents flowing through the ferrite bead. Ferrites can begin to loose effectiveness at much lower
than rated current values. See the TPA2011D1 EVM User's Guide for components used successfully by TI.
Figure 29 shows a typical ferrite-bead output filter.
Ferrite
Chip Bead
VO−

1 nF
Ferrite
Chip Bead
VO+

1 nF

Figure 29. Typical Ferrite Chip Bead Filter

9.3.3 Short Circuit Auto-Recovery


When a short-circuit event occurs, the TPA2011D1 goes to shutdown mode and activates the integrated auto-
recovery process whose aim is to return the device to normal operation once the short-circuit is removed. This
process repeatedly examines (once every 100ms) whether the short-circuit condition persists, and returns the
device to normal operation immediately after the short-circuit condition is removed. This feature helps protect the
device from large currents and maintain a good long-term reliability.

9.3.4 Integrated Image Reject Filter for DAC Noise Rejection


In applications which use a DAC to drive Class-D amplifiers, out-of-band noise energy present at the DAC's
image frequencies fold back into the audio-band at the output of the Class-D amplifier. An external low-pass filter
is often placed between the DAC and the Class-D amplifier in order to attenuate this noise.
The TPA2011D1 has an integrated Image Reject Filter with a low-pass cutoff frequency of 130 kHz, which
significantly attenuates this noise. Depending on the system noise specification, the integrated Image Reject
Filter may help eliminate external filtering, thereby saving board space and component cost.

14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: TPA2011D1


TPA2011D1
www.ti.com SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015

9.4 Device Functional Modes


9.4.1 Summing Input Signals With the TPA2011D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2011D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.

9.4.1.1 Summing Two Differential Input Signals


Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input
source can be set independently (see Equation 1 and Equation 2, and Figure 30).
V
Gain 1 + O + 2 x 150 kW
V R
V
V
ǒǓ
I1 I1 (1)
V
Gain 2 + O + 2 x 150 kW
V R
V
V
ǒǓ
I2 I2 (2)
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain 1
= 0.1 V/V. The resistor values would be:
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
RI1
+
Differential
Input 1 RI1 To Battery
- Internal VDD
Oscillator CS
RI2
+ IN-
VO+
_ PWM H-
Differential Bridge
Input 2 + VO-
RI2
- IN+

GND
Bias
SHUTDOWN Circuitry

Filter-Free Class D

Figure 30. Application Schematic With TPA2011D1 Summing Two Differential Inputs

9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal


Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in Equation 5. To assure that each input is balanced, the single-ended input must be
driven by a low-impedance source even if the input is not in use
V
Gain 1 + O + 2 x 150 kW
V R
V
V
ǒǓ
I1 I1 (3)
V
Gain 2 + O + 2 x 150 kW
V R
V
V
ǒǓ
I2 I2 (4)

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Device Functional Modes (continued)


C + 1
I2 ǒ2p RI2 f c2Ǔ (5)
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set
to gain 2 = 2 V/V, the resistor values would be…
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz...
C u 1
I2 ǒ2p 150kW 20HzǓ (6)
CI2 > 53 nF (7)
RI1

Differential
RI1 To Battery
Input 1 Internal VDD
Oscillator CS
CI2 R
Single-Ended I2
IN-
Input 2 VO+
_ PWM H-
Bridge
+ VO-
RI2
IN+
CI2
GND
Bias
SHUTDOWN Circuitry

Filter-Free Class D

Figure 31. Application Schematic With TPA2011D1 Summing Differential Input and Single-Ended Input
Signals

9.4.1.3 Summing Two Single-Ended Input Signals


Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 8 through Equation 11,
and Figure 32). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN– terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
Gain 1 + O + 2 x 150 kW
V R
V
V
ǒǓ
I1 I1 (8)
V
Gain 2 + O + 2 x 150 kW
V R
V
V
ǒǓ
I2 I2 (9)
C + 1
I1 ǒ Ǔ
2p R f
I1 c1 (10)
C + 1
I2 ǒ Ǔ
2p R f
I2 c2 (11)
C +C ) C
P I1 I2 (12)

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TPA2011D1
www.ti.com SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015

Device Functional Modes (continued)


R R
R + I1 I2
P ǒRI1 Ǔ
) R
I2 (13)
CI1 R
I1
Single-Ended
Input 1 To Battery
Internal VDD
Oscillator CS
CI2 R
Single-Ended I2
IN-
Input 2 VO+
_ PWM H-
Bridge
+ VO-
RP
IN+
CP
GND
Bias
SHUTDOWN Circuitry

Filter-Free Class D

Figure 32. Application Schematic With TPA2011D1 Summing Two Single-Ended Inputs

9.4.2 Shutdown Mode


The TPA2011D1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin.

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TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015 www.ti.com

10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information


These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases. Each of these configurations can be realized using
the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the
most common modes of operation. Any design variation can be supported by TI through schematic and layout
reviews. Visit e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional
information.

10.2 Typical Applications


10.2.1 TPA2011D1 with Differential Input

To Battery
Internal VDD
Oscillator CS
RI
+ IN−
VO+
_ PWM H−
Differential Bridge
Input + VO−
RI
− IN+

Bias GND
EN Circuitry
TPA2011D1
Filter-Free Class D

Figure 33. Typical TPA2011D1 Application Schematic with Differential Input

10.2.1.1 Design Requirements


For this design example, use the parameters listed in Table 1.

Table 1. Design Parameters


DESIGN PARAMETER EXMAPLE VALUE
Power supply 5V
High > 2 V
Enable input
Low < 0.8 V
Speaker 8Ω

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TPA2011D1
www.ti.com SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Input Resistors (RI)


The input resistors (RI) set the gain of the amplifier according to the following equation.
2 ´ 150kW æ V ö
Gain = çV÷
RI è ø (14)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with
1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2011D1 to limit noise injection on the high-impedance nodes.
For optimal performance, the gain should be set to 2 V/V or lower. Lower gain allows the TPA2011D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.

10.2.1.2.2 Decoupling Capacitor (CS)


The TPA2011D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1
μF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to
the TPA2011D1 is very important for the efficiency of the class-D amplifier, because any resistance or
inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-
frequency noise signals, a 10 μF or greater capacitor placed near the audio power amplifier would also help, but
it is not required in most applications because of the high PSRR of this device.

10.2.1.3 Application Curves


For application curves, see the figures listed in Table 2.

Table 2. Table of Graphs


DESCRIPTION FIGURE NUMBER
Output Power vs Supply Resistance Figure 11
GSM Power Supply Rejection vs Time Figure 26
GSM Power Supply Rejection vs Frequency Figure 27

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10.2.2 TPA2011D1 with Differential Input and Input Capacitors

To Battery
Internal VDD
Oscillator CS
CI RI
IN−
VO+
_ PWM H−
Differential
Bridge
Input VO −
CI RI +
IN+

GND
Bias
EN
Circuitry TPA2011D1
Filter-Free Class D

Figure 34. TPA2011D1 Application Schematic with Differential Input and Input Capacitors

10.2.2.1 Design Requirements


For this design example, use the parameters listed in Table 1.

10.2.2.2 Detailed Design Procedure


For the design procedure see Input Resistors (RI) and Decoupling Capacitor (CS).

10.2.2.2.1 Input Capacitors (CI)


The TPA2011D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD –0.8 V. If the input signal is not biased within the recommended common mode input range, if
needing to use the input as a high pass filter, or if using a single-ended source, input coupling capacitors are
required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fC, determined in the
following equation.
1
fC =
2pRICI (15)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
The equation below is reconfigured to solve for the input coupling capacitance.
1
CI =
2pRIfC (16)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 μF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.

10.2.2.3 Application Curves


For application curves, see the figures listed in Table 2.

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10.2.3 TPA2011D1 with Single-Ended Input

To Battery
Internal VDD
Oscillator CS
CI RI
Single-ended IN−
Input VO+
_ PWM H−
Bridge
+ VO−
RI
IN+
CI
GND
Bias
EN Circuitry
TPA2011D1
Filter-Free Class D

Figure 35. TPA2011D1 Application Schematic with Single-Ended Input

10.2.3.1 Design Requirements


For this design example, use the parameters listed in Table 1.

10.2.3.2 Detailed Design Procedure


For the design procedure see Input Resistors (RI), Decoupling Capacitor (CS), and Input Capacitors (CI).

10.2.3.3 Application Curves


For application curves, see the figures listed in Table 2.

11 Power Supply Recommendations


The TPA2011D1 is designed to operate from an input voltage supply range between 2.5-V and 5.5-V. Therefore,
the output voltage range of power supply should be within this range and well regulated. The current capability of
upper power should not exceed the maximum current limit of the power switch.

11.1 Power Supply Decoupling Capacitors


The TPA2011D1 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, is recommended to place a 2.2 μF
to 10 μF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any drop in the supply voltage.

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12 Layout

12.1 Layout Guidelines


In making the pad size for the DSBGA balls, TI recommends that the layout use nonsolder mask defined (NSMD)
land. With this method, the solder mask opening is made larger than the desired land area, and the opening size
is defined by the copper pad width. Figure 36 shows the appropriate diameters for a DSBGA layout.
Place all the external components close to the TPA2011D1 device. Placing the decoupling capacitors as close as
possible to the device is important for the efficiency of the class-D amplifier. Any resistance or inductance in the
trace between the device and the capacitor can cause a loss in efficiency.
An on-pad via is not required to route the middle ball B2 (PVDD) of the TPA2011D1. Just short ball B2 (PVDD) to
ball B1 (VDD) and connect both to the supply trace as shown in Figure 37. This simplifies board routing and
saves manufacturing cost.
Copper
Trace Width

Solder
Solder Mask Pad Width
Opening

Solder Mask Copper Trace


Thickness Thickness

Figure 36. Land Pattern Dimensions

Table 3. Land Pattern Dimensions (1) (2) (3) (4)


SOLDER PAD SOLDER MASK COPPER STENCIL
COPPER PAD STENCIL OPENING (6) (7)
DEFINITIONS OPENING (5) THICKNESS THICKNESS
Nonsolder mask 1 oz max 0.275 mm x 0.275 mm Sq.
0.23 mm 0.310 mm 0.1 mm thick
defined (NSMD) (0.032 mm) (rounded corners)

(1) Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils give inferior
solder paste volume control.
(7) Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.

22 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: TPA2011D1


TPA2011D1
www.ti.com SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015

12.2 Layout Example

Input Resistors
placed as close as
possible to the device

IN + OUT -
Decoupling capacitor
placed as close as A1 A2 A3
possible to the device

B1 B2 B3

0.1µF C1 C2 C3

TPA2011D1
IN - OUT +

EN

Top Layer Ground Plane Top Layer Traces

Pad to Top Layer Ground Plane Via to Power Supply

Via to Bottom Layer Ground Plane


Figure 37. TPA2011D1 Layout Example

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Product Folder Links: TPA2011D1
TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015 www.ti.com

13 Device and Documentation Support

13.1 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

24 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: TPA2011D1


PACKAGE OPTION ADDENDUM

www.ti.com 19-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPA2011D1YFFR ACTIVE DSBGA YFF 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 OEW Samples

TPA2011D1YFFT ACTIVE DSBGA YFF 9 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 OEW Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 19-Oct-2022

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jun-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA2011D1YFFR DSBGA YFF 9 3000 180.0 8.4 1.34 1.34 0.81 4.0 8.0 Q1
TPA2011D1YFFT DSBGA YFF 9 250 180.0 8.4 1.34 1.34 0.81 4.0 8.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jun-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA2011D1YFFR DSBGA YFF 9 3000 182.0 182.0 20.0
TPA2011D1YFFT DSBGA YFF 9 250 182.0 182.0 20.0

Pack Materials-Page 2
PACKAGE OUTLINE
YFF0009 SCALE 10.000
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER
D

0.625 MAX C

SEATING PLANE
0.30
BALL TYP 0.05 C
0.12

0.8 TYP

B SYMM
0.8
TYP D: Max = 1.244 mm, Min =1.184 mm
0.4 TYP
E: Max = 1.19 mm, Min = 1.13 mm
A
0.3 1 2 3
9X
0.2
0.015 C A B SYMM

0.4 TYP

4219552/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
EXAMPLE BOARD LAYOUT
YFF0009 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.23)
1 2 3
A

(0.4) TYP
SYMM
B

SYMM

LAND PATTERN EXAMPLE


SCALE:30X

0.05 MAX METAL UNDER


( 0.23) 0.05 MIN
METAL SOLDER MASK

SOLDER MASK ( 0.23)


OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS


NOT TO SCALE

4219552/A 05/2016
NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

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EXAMPLE STENCIL DESIGN
YFF0009 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.25) (R0.05) TYP

1 2 3
A

(0.4) TYP
B SYMM

METAL
TYP
C

SYMM

SOLDER PASTE EXAMPLE


BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4219552/A 05/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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