TPA2011D1 3.2-W Mono Filter-Free Class-D Audio Power Amplifier With Auto-Recovering Short-Circuit Protection
TPA2011D1 3.2-W Mono Filter-Free Class-D Audio Power Amplifier With Auto-Recovering Short-Circuit Protection
TPA2011D1 3.2-W Mono Filter-Free Class-D Audio Power Amplifier With Auto-Recovering Short-Circuit Protection
TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015
EN
TPA2011D1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2011D1
SLOS626B – DECEMBER 2009 – REVISED NOVEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 13
2 Applications ........................................................... 1 9.3 Feature Description................................................. 13
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 15
4 Revision History..................................................... 2 10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
5 Device Comparison Table..................................... 3
10.2 Typical Applications .............................................. 18
6 Pin Configuration and Functions ......................... 4
11 Power Supply Recommendations ..................... 21
7 Specifications......................................................... 4
11.1 Power Supply Decoupling Capacitors................... 21
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 5 12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
7.3 Recommended Operating Conditions....................... 5
12.2 Layout Example .................................................... 23
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 5 13 Device and Documentation Support ................. 24
7.6 Operating Characteristics.......................................... 6 13.1 Community Resources.......................................... 24
7.7 Dissipation Ratings ................................................... 6 13.2 Trademarks ........................................................... 24
7.8 Typical Characteristics .............................................. 7 13.3 Electrostatic Discharge Caution ............................ 24
13.4 Glossary ................................................................ 24
8 Parameter Measurement Information ................ 12
9 Detailed Description ............................................ 13 14 Mechanical, Packaging, and Orderable
Information ........................................................... 24
9.1 Overview ................................................................. 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
• Changed the Package Dimensions table. D was Max = 1244μm, Min = 1184μm. E was Max = 1190μm, Min =
1130μm .................................................................................................................................................................................. 1
YFF Package
9-Pin DSBGA
Top View
A1 A2 A3
1.160 mm
B1 B2 B3
IN- EN VO+
C1 C2 C3
1.214 mm
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
EN C2 I Shutdown terminal. When terminal is low the device is put into Shutdown mode.
Analog ground terminal. Must be connected to same potential as PGND using a direct connection
GND A2 I
to a single point ground.
IN– C1 I Negative differential audio input
IN+ A1 I Positive differential audio input
High-current Analog ground terminal. Must be connected to same potential as GND using a direct
PGND B3 I
connection to a single point ground.
High-current Power supply terminal. Must be connected to same power supply as VDD using a
PVDD B2 I direct connection. Voltage must be within values listed in Recommended Operating Conditions
table.
Power supply terminal. Must be connected to same power supply as PVDD using a direct
VDD B1 I
connection. Voltage must be within values listed in Recommended Operating Conditions table.
VO- A3 O Negative BTL audio output
VO+ C3 O Positive BTL audio output
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
Supply In active mode –0.3 6 V
VDD, PVDD
voltage In shutdown mode –0.3 6 V
VI Input EN, IN+, IN– V
–0.3 VDD + 0.3
voltage
RL Minimum load resistance 3.2 Ω
Output continuous total power dissipation See Dissipation Ratings
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Tstg Storage temperature –65 85 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
4 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
100 100
90 90
80 80
70 70
η − Efficiency − %
η − Efficiency − %
60 60
50 50
40 40
RL = 8 Ω + 33 µH RL = 4 Ω + 33 µH
30 Gain = 6 dB 30 Gain = 6 dB
20 20
VDD = 2.5 V VDD = 2.5 V
10 VDD = 3.6 V 10 VDD = 3.6 V
VDD = 5.0 V VDD = 5.0 V
0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
PO − Output Power − W PO − Output Power − W
PD − Power Dissipation − W
0.3
0.4
0.2 0.3
0.2
0.1
0.1
0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
PO − Output Power − W PO − Output Power − W
Figure 3. Power Dissipation vs Output Power Figure 4. Power Dissipation vs Output Power
1.0 0.5
VDD = 2.5 V RL = 4 Ω + 33 µH VDD = 2.5 V RL = 8 Ω + 33 µH
0.9 VDD = 3.6 V Gain = 6 dB VDD = 3.6 V Gain = 6 dB
VDD = 5.0 V VDD = 5.0 V
0.8 0.4
IDD − Supply Current − A
0.7
0.6 0.3
0.5
0.4 0.2
0.3
0.2 0.1
0.1
0.0 0.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
PO − Output Power − W PO − Output Power − W
Figure 5. Supply Current vs Output Power Figure 6. Supply Current vs Output Power
1.75 150
1.25 50
1.00 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.1 0.2 0.3 0.4 0.5
VDD − Supply Voltage − V VEN − EN Voltage − V
3 PO − Output Power − W
2
2
1
1
0 0
4 8 12 16 20 24 28 32 4 8 12 16 20 24 28 32
RL − Load Resistance − Ω RL − Load Resistance − Ω
Figure 9. Output Power vs Load Resistance Figure 10. Output Power vs Load Resistance
4
RL = 4 Ω, THD+N = 1 %
RL = 4 Ω, THD+N = 10 %
RL = 8 Ω, THD+N = 1 %
RL = 8 Ω, THD+N = 10 %
3
PO − Output Power − W
Frequency = 1 kHz
Gain = 6 dB
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD − Supply Voltage − V
Figure 11. Output Power vs Supply Resistance Figure 12. THD + Noise vs Output Power
0.1
0.01
0.001
20 100 1k 10k 20k
f − Frequency − Hz
Figure 13. THD + Noise vs Output Power Figure 14. THD + Noise vs Frequency
10 10
THD+N − Total Harmonic Distortion + Noise − %
0.1 0.1
0.01 0.01
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
Figure 15. THD + Noise vs Frequency Figure 16. THD + Noise vs Frequency
10 10
THD+N − Total Harmonic Distortion + Noise − %
0.1 0.1
0.01 0.01
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
Figure 17. THD + Noise vs Frequency Figure 18. THD + Noise vs Frequency
0.1
0.1
0.01
0.001 0.01
20 100 1k 10k 20k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
f − Frequency − Hz VIC − Common Mode Input Voltage − V
Figure 19. THD + Noise vs Frequency Figure 20. THD + Noise vs Common Mode Input Voltage
0 0
Inputs AC−Grounded VDD = 2.5 V Inputs AC−Grounded VDD = 2.5 V
PSRR − Power Supply Rejection Ratio − dB
Figure 21. Power Supply Rejection Ratio vs Frequency Figure 22. Power Supply Rejection Ratio vs Frequency
0 −30
RL = 8 Ω + 33 µH
CMRR − Common Mode Rejection Ratio − dB
−30 −50
−40
−60
−50
−70
−60
−70 −80
−80
−90
−90
−100 −100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 20 100 1k 10k 20k
VIC − Common Mode Input Voltage − V f − Frequency − Hz
Figure 23. Power Supply Rejection Ratio vs Common Mode Figure 24. Common Mode Rejection Ratio vs Frequency
Input Voltage
VDD = 2.5 V
−10 Frequency = 217 Hz VDD = 3.6 V
Gain = 6 dB VDD = 5.0 V VDD
−20 High – 3.6 V
Amplitude – 500 mV
−30 Duty Cycle – 20%
−40
−50 VOUT
2 mV/div
−60
−70
Inputs ac-grounded
Gain = 6 dB
Frequency (Hz)
Figure 27. GSM Power Supply Rejection vs Frequency
CS1
CS2
+
VDD
-
(1) Input resistor RI = 150kΩ gives a gain of 6 dB which is used for all the graphs
(2) CI was shorted for any common-mode input voltage measurement. All other measurements were taken with CI = 0.1-
μF (unless otherwise noted).
(3) CS1 = 0.1μF is placed very close to the device. The optional CS2 = 10μF is used for datasheet graphs.
(4) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low-pass filter (1kΩ,
4700pF) is used on each output for the data sheet graphs.
9 Detailed Description
9.1 Overview
The TPA2011D1 is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 3.2W into 4-Ω
load with 5-V power supply. The fully-differential design of this amplifier avoids the usage of bypass capacitors
and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the device size a perfect
choice for small, portable applications as only three external components are required. The advanced modulation
used in the TPA2011D1 PWM output stage eliminates the need for an output filter.
Input
EN
Buffer SC
300 KΩ
Design the TPA2011D1 without an Inductor / Capacitor (LC) output filter if the traces from the amplifier to the
speaker are short. Wireless handsets and PDAs are great applications for this class-D amplifier to be used
without an output filter.
The TPA2011D1 does not require an LC output filter for short speaker connections (approximately 100 mm long
or less). A ferrite bead can often be used in the design if failing radiated emissions testing without an LC filter;
and, the frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies. The selection must also take into
account the currents flowing through the ferrite bead. Ferrites can begin to loose effectiveness at much lower
than rated current values. See the TPA2011D1 EVM User's Guide for components used successfully by TI.
Figure 29 shows a typical ferrite-bead output filter.
Ferrite
Chip Bead
VO−
1 nF
Ferrite
Chip Bead
VO+
1 nF
GND
Bias
SHUTDOWN Circuitry
Filter-Free Class D
Figure 30. Application Schematic With TPA2011D1 Summing Two Differential Inputs
Differential
RI1 To Battery
Input 1 Internal VDD
Oscillator CS
CI2 R
Single-Ended I2
IN-
Input 2 VO+
_ PWM H-
Bridge
+ VO-
RI2
IN+
CI2
GND
Bias
SHUTDOWN Circuitry
Filter-Free Class D
Figure 31. Application Schematic With TPA2011D1 Summing Differential Input and Single-Ended Input
Signals
Filter-Free Class D
Figure 32. Application Schematic With TPA2011D1 Summing Two Single-Ended Inputs
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
To Battery
Internal VDD
Oscillator CS
RI
+ IN−
VO+
_ PWM H−
Differential Bridge
Input + VO−
RI
− IN+
Bias GND
EN Circuitry
TPA2011D1
Filter-Free Class D
To Battery
Internal VDD
Oscillator CS
CI RI
IN−
VO+
_ PWM H−
Differential
Bridge
Input VO −
CI RI +
IN+
GND
Bias
EN
Circuitry TPA2011D1
Filter-Free Class D
Figure 34. TPA2011D1 Application Schematic with Differential Input and Input Capacitors
To Battery
Internal VDD
Oscillator CS
CI RI
Single-ended IN−
Input VO+
_ PWM H−
Bridge
+ VO−
RI
IN+
CI
GND
Bias
EN Circuitry
TPA2011D1
Filter-Free Class D
12 Layout
Solder
Solder Mask Pad Width
Opening
(1) Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils give inferior
solder paste volume control.
(7) Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Input Resistors
placed as close as
possible to the device
IN + OUT -
Decoupling capacitor
placed as close as A1 A2 A3
possible to the device
B1 B2 B3
0.1µF C1 C2 C3
TPA2011D1
IN - OUT +
EN
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 19-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPA2011D1YFFR ACTIVE DSBGA YFF 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 OEW Samples
TPA2011D1YFFT ACTIVE DSBGA YFF 9 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 OEW Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jun-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jun-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0009 SCALE 10.000
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
D
0.625 MAX C
SEATING PLANE
0.30
BALL TYP 0.05 C
0.12
0.8 TYP
B SYMM
0.8
TYP D: Max = 1.244 mm, Min =1.184 mm
0.4 TYP
E: Max = 1.19 mm, Min = 1.13 mm
A
0.3 1 2 3
9X
0.2
0.015 C A B SYMM
0.4 TYP
4219552/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0009 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
9X ( 0.23)
1 2 3
A
(0.4) TYP
SYMM
B
SYMM
4219552/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0009 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
1 2 3
A
(0.4) TYP
B SYMM
METAL
TYP
C
SYMM
4219552/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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