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Detailed design procedure of a DC-DC buck-boost converter employing a

passive snubber

Conference Paper · November 2017

DOI: 10.1109/COBEP.2017.8257224

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 DETAILED DESIGN PROCEDURE OF A DC-DC BUCK-BOOST CONVERTER
EMPLOYING A PASSIVE SNUBBER

Alexandre Rodrigues Vaz1, Fernando Lessa Tofoli2

1
Federal Center for Technological Education of Minas Gerais, Nepomuceno – Minas Gerais, Brazil
2
Federal University of São João del-Rei, São João del-Rei – Minas Gerais, Brazil
e-mail: [email protected], [email protected]

Abstract – This paper presents an optimized design energy is dissipated in the discharge resistor [8]. This
procedure for a dc-dc buck-boost converter associated approach is not recommended for high power levels, since
with a dissipative snubber. Initially, the static gain of the efficiency can be seriously compromised. However, it is still
converter is determined from the charging and used in practical low-power applications to reduce the
discharging times of the inductor in an approach that is voltage stress across the switch during turn-off.
valid for any conduction mode and does not depend on Of course, both the RCD snubber and the dc-dc buck-
the load condition. The influence of the snubber circuit is boost converter have been extensively studied in literature
also analyzed considering tradeoffs between the and many didactic books on power electronics [9]. However,
maximum voltage stress across the switch and related the proper selection of the snubber circuit and optimization
losses. Experimental results are also presented in order to of the design procedure in a straightforward, practical, and
validate the theoretical assumptions. efficient way are worth of investigation, since the maximum
voltage across the semiconductors has direct impact on cost
Keywords – buck-boost converter, dc-dc converters, and converter losses. Within this context, this paper presents
snubbers. an alternative methodology for the design of the power stage
elements in a conventional dc-dc buck-boost converter. The
I. INTRODUCTION influence of the snubber circuit in the limitation of the
maximum voltage stress across the switch is analyzed while
Dc-dc converters are employed in a wide variety of also taking into account the power losses due to the snubber
applications that range from switch-mode power supplies to resistor, which influence the converter efficiency. An
renewable energy systems [1] [2]. Numerous nonisolated and experimental prototype is also implemented, as relevant
isolated topologies have been proposed so far for distinct issues are discussed.
purposes, which allow voltage step down and/or step up [3].
The classical or conventional nonisolated dc-dc buck-boost II. DC-DC BUCK-BOOST CONVERTER
converter is a common choice because the output voltage can
be lower or higher than the input voltage by simply adjusting A. Qualitative Analysis
the duty cycle, from which several structures have been Fig. 1 shows the dc-dc buck-boost converter associated
derived [4]. Besides, it is a far simple topology than the with the RCD snubber, which is composed of an auxiliary
classical Ćuk, SEPIC (Single-Ended Primary Inductance diode DA, a snubber capacitor CS, and a snubber resistor RS.
Converter), and Zeta ones, whose respective power stages Of course, the converter in Fig. 1 does not operate like its
present higher component count with additional complexity hard switching counterpart, which does not use an auxiliary
associated to the control system [5]. Besides, the voltage circuit. The qualitative analysis of the topology is then
stress across both semiconductors in the conventional dc-dc presented in Fig. 2, as there are six stages considering the
step up/down of converters is equal to the sum of the input operation in discontinuous conduction mode (DCM). Some
voltage and the output voltage, which may lead to the use of theoretical waveforms are presented in Fig. 3 to Fig. 6.
high cost semiconductors and appreciable losses [6].
The power semiconductors used in dc-dc converters
operate under two switching states i.e. on or off. Typically,
such transition when both current and voltage are not null, as
the overlap between the aforementioned quantities during
commutation causes appreciable switching losses and EMI
(electromagnetic interference) levels. This phenomenon is
known as hard switching in literature. In order to reduce
switching losses and improve efficiency, soft switching
techniques can be used, which are classified in either active
or passive methods [7].
Dissipative snubbers, also known as RCD (resistor- Fig. 1. Dc-dc buck-boost converter with RCD snubber.
capacitor-diode) snubbers, are still very popular due to the
inherent simplicity and use of only passive components. This
type of circuit is limited by the fact that all capacitor-stored
 (a) First stage (b) Second stage

(c) Third stage (d) Fourth stage

(e) Fifth stage (f) Sixth stage

Fig. 2. Operating stages of the dc-dc buck-boost converter with RCD snubber in DCM.

First stage [t0, t1] (Fig. 2 (a)): Active switch S is turned on, inductor continues discharging linearly through diode DM.
while main diode DM remains reverse biased. The current Both inductor and dc input source transfer energy to the
through inductor L increases linearly. During a brief time output stage composed by capacitor Co and load Ro.
interval, capacitor CS is charged exponentially to the level (Vi
+Vo), while the charging current is limited by snubber
resistor RS. During this stage, the load is supplied by the
output capacitor Co.
Second stage [t1, t2] (Fig. 2 (b)): After the voltage across
capacitor CS becomes equal to (Vi +Vo), the current through
RS becomes null. The input filter inductor is still storing
energy and the load is supplied by the output capacitor.
Third stage [t2, t3] (Fig. 2 (c)): Switch S is turned off, while
the voltage across inductor L becomes negative due to its
Fig. 3. Current (A) and voltage (B) waveforms in the filter inductor.
discharge. Considering that diode DM is not turned on
instantly, capacitor CS is charged linearly by the inductor
Fifth stage [t4, t5] (Fig. 2 (e)): Capacitor CS is fully
current through diode DA. The voltage across CS becomes
discharged at instant t4, as the current through the inductor
-X, which defines the maximum voltage stress across switch
becomes null, thus evidencing the operation in DCM.
S, being this an important design criterion. Diode DM is
Sixth stage [t5, t6] (Fig. 2 (f)): This stage begins when diode
forward biased at instant t3.
DM is reverse biased. A damped oscillating circuit is formed
Fourth stage [t3, t4] (Fig. 2 (d)): A short-circuit occurs in the
by CS, RS, and L, which is supplied by voltage source defined
snubber as diode DM is turned on, causing CS to be
as Vo. This stage is only supposed to exist in DCM operation.
discharged exponentially though DM and RS. Besides, the
 tc  t d
DI  , DI 0,1 (3)
Ts
By solving the system of equations composed by (2) and
(3), it is possible to write the following expressions:
Gv
tc   D T (4)
Fig. 4. Current (A) and voltage (B) waveforms in the active switch.
1  Gv  I s
DI  Ts
td  (5)
1  Gv 
III. DESIGN PROCEDURE OF THE DC-DC BUCK-
BOOST CONVERTER EMPLOYING AN RCD SNUBBER

A. Filter Inductor
Let us consider a generic waveform of the input current in
Fig. 5. Current (B) and voltage (A) waveforms in the main diode. the dc-dc buck-boost as in Fig. 7, which in this case
represents the operation in CCM. However, the analysis
developed in this session can be extended to DCM and CRM
as follows, as the converter losses are neglected for
simplicity.
It is important to define Ip=IL(pk) as the maximum or peak
value of the inductor current, K as the minimum value of the
inductor current or shift factor, and ΔI as the current ripple.
According to Fig. 7, K=0 and tc+td=Ts when the converter
Fig. 6. Voltage across snubber capacitor CS (A),voltage across snubber
operates in CRM. If K=0 and tc+td<Ts, the converter is
resistor RS (B), input voltage (C), and output voltage (D). supposed to operate in DCM. Finally, the converter operates
in CCM if K>0 and tc+td=Ts. In other words, the choice of K
B. Alternative Analysis of The Static Gain and the sum of tc and td associated to the static gain and the
Let us consider voltage vL(t) and current iL(t), where tc is rated output power allows defining the operation mode.
the charging time and td is the discharging time of inductor L.
Considering the operation in DCM, it can be stated that
iL(t)=0 during part of the switching period Ts i.e. tc+td<Ts.
Besides, the voltages across the inductor during charging and
discharging are Vi and –Vo, respectively.
By analyzing vL(t) and assuming tc=td, it is possible to
state that Vi=|–Vo| or Vo=Vi. If tc<td, Vi>|–Vo| or Vo<Vi.
Finally, if tc>td, Vi<|–Vo| or Vo>Vi. Such conclusions are
based on the fact that Vitc=|–Vo|td, that is, the average
voltage across the inductor is null considering the steady- Fig. 7. Input current in the dc-dc buck-boost converter.
state operation. It is then possible to write the following
expressions: Besides, based on the definition of the average value of a
Ts signal, the following statement is valid:
1
 vL  t  dt  0
Ts 0
(1) 0  K  Ii  I o  I L ( pk ) (6)
where Ii and Io is the average input and output current,
V t respectively. For a given operating point defined in the
Gv  o  c (2)
design specifications of the dc-dc buck-boost converter, it
Vi td
can be stated that increasing parameter K causes the current
According to (2), it is possible to express the static gain Gv ripple ΔI=Ip–K to decrease.
as a function of the inductor charging and discharging times. The average value of the input current it can be calculated
Besides, it is interesting to notice that the average value of from Fig. 7 as in (7) or (8):
the output voltage can be determined as a function of Vi, tc,
1 tc
Ts 0
and td, being independent on load variations even though the Ii   i (t )dt (7)
converter operates in DCM. In other words, expression (2) is
valid for any operating mode of the converter.
1  I  tc 
Alternatively it is possible to define DI as the duty cycle Ii    K  tc  (8)
associated to the inductor operation, which corresponds to Ts  2 
the interval during which the current flows through it over On the other hand, the current ripple is given by:
the switching period i.e.
  2  Pi  T  I L pk 
I    2 K  (9) vCS  t     t  Vo  Vi (17)
 Vi  tc  CS
where Pi is the input power calculated by (10) considering a
lossless converter. trt  t3  t2 
Vo Vi  X   CS
(18)
Pi  Po  Vi  I i (10)
I L  pk 
Considering that vL(t)=Vi during the time interval defined
by [0, tc], the peak current through the inductor can be
obtained from (11), which results in (12).
1 tc
iL  t    vL  t  dt
L 0
(11)

V
I L ( pk )  i  tc (max)  K (12)
L
where tc(max) is the inductor charging time under rated load
condition. Fig. 8. Detailed view of the voltage across snubber capacitor CS (A) and
Finally, the filter inductance can be obtained from (12) as: voltage across snubber resistor RS (B).
Vi  tc (max) Vi  tc (max)
L  (13) Vo Vi  X trt
I L ( pk )  K I  (19)
Besides, substituting (9) in (13) gives: X t fr
Vi  tc (max) where IL(pk) is the peak current through the inductor under
L (14) rated load condition, X is the additional voltage stress across
 2  Pi  T  the switch during turn-off i.e. VS(max)=Vi+Vo+X is its
  2 K  respective maximum value, and tfr is the diode forward
Vi  tc (max)  recovery time.
where tc(max) is the inductor charging time under rated load Substituting (19) in (18) gives:
condition. t fr  I L pk 
CS  (20)
B. Filter Capacitor X
In order to calculate the output filter capacitor, it is According to (20), it can be stated that the maximum
necessary to consider that the output current is constant in the voltage stress across the switch is inversely proportional to
analysis. Then the following expressions result: the capacitance used in the snubber circuit.
Vi  tc max   L   K  I o  
2 By applying the superposition theorem to Fig. 6
  if K  I (15)
1 considering the converter operation in steady state and CCM,
Co 
VC  max  2  L Vo the rms current through the snubber resistor RS can be
o
obtained as:
where ΔVC(max)=Vo(max)–Vo(min) is the maximum ripple voltage
across the filter capacitor defined in the design 1  Vo  Vi 2  X 2  
I RS  rms  2
    (21)
 2  RS 2  RS 2 
specifications. Ts 2


 V t
 
2
where =RSCS is the time constant related to the exponential
 i c  
max 
charge and discharge of CS through RS during the switching
1  2  L Vo 
Co    if K  I o (16) period.
VC  max   V  t


i c  max    K I o


Substituting  in (21) and rearranging it gives (22), which
does not only provide the power dissipated in the snubber
  circuit, but also shows that such losses do not depend on
Vo
resistance RS for the same load condition.
C. Snubber Circuit t fr  I L  pk   Vo  Vi 2 
The analysis of the operating stages in Fig. 2 and the Pd   X (22)
waveforms in Fig. 3 to Fig. 6 reveal that the voltage across
2  Ts  X 
CS at instant t3 defines exactly the maximum voltage stress Finally, resistor RS can be expressed as:
across the switch. Fig. 8 presents the voltages across CS and
 Vo  Vi 2
t fr  I L  pk  
RS during interval [t2, t3] i.e. between the switch turn-off at t2 RS     X  (23)
and the main diode turn-on at t3. 2  Ts  I RS  rms  2  X 
Expressions (17) to (19) can be obtained from Fig. 8 as:
considering that IL(pk) is defined as a design criterion.
 The analysis of the first and second derivatives of The average, rms, and peak currents through the diode are
expression (22) allows concluding that the power losses in RS given by (34), (35), and (36), respectively, while the
are minimum when X=Vo+Vi, as stated in (24). maximum voltage stress is calculated from (37).
t fr  I L pk   Vo  Vi  td (max)  I 
Pd  min   (24) I DM  avg     K (34)
Ts Ts  2 
Therefore, it is possible to calculate RS according to (25) td (max)  I 2 
I DM  rms     K  I L ( pk ) 
3 
so that the power losses in the snubber circuit are minimized. (35)
t fr  I L pk   Vo  Vi  Ts 
RS  min    I DM  pk   I L pk 
Ts  I RS  rms  2 (36)

VDM  max   Vo  Vi (37)

V 
t fr   i  tc max   K   Vo  Vi 
L  IV. EXPERIMENTAL RESULTS
Ts  I RS  rms  2
(25) In order to validate the proposed methodology, the design
It is worth to mention that the choice of IRS(rms) does affect specifications of the dc-dc buck-boost converter given in
the peak, average, and rms current through the switch, as this Table II have been chosen and an experimental prototype
parameter must be chosen wisely so that the semiconductor was implemented accordingly. It is important to mention that
related cost and conduction losses do not increase the sum of the inductor charging and discharging times must
significantly. be defined as a portion of the switching period, being this a
It can be demonstrated that good tradeoffs can be made design criterion. If the operation occurs in CCM or CRM,
considering X=0.5(Vo+Vi). If X is further reduced, tc(max)+td(max)=(1/fs), where td(max) is the inductor discharging
appreciable losses are supposed to exist in the snubber time under rated load condition. Otherwise,
circuit, thus compromising the very converter efficiency tc(max)+td(max)<(1/fs) in DCM. The choice of CS is directly
Once again, it is important to notice in (22) that the power related to the maximum voltage stress across the switch,
losses in the snubber circuit do not depend on RS as long as while Rs is associated to the power dissipated in the auxiliary
CS is charged and discharged during the switching period. In circuit, which affects the converter efficiency.
other words, the following condition must be obeyed: TABLE I
Ts>10. DESIGN SPECIFICATIONS OF THE DC-DC BUCK-BOOST CONVERTER
Parameter Specification
Finally, the current and voltage stresses in the snubber
Input voltage Vi=100 V
diode are: Output voltage Vo=100 V

I DA avg  
Vo Vi  X   Cs (26)
Output power Po=200 W
Maximum output current Io(max)=2 A
Ts Switching frequency fs=40 kHz
Sum of the inductor charging
Vo Vi  X   Cs  I L pk  and discharging times
tc(max)+td(max)=(1/fs)

I DA rms   (27) Typical forward recovery time

tfr=280 ns
Ts of the auxiliary diode
Maximum output voltage ripple ΔVo=0.25%Vo
I DA pk   I L pk  (28) Shift factor K=2.4
Duty cycle associated to the
VDA max   Vo  Vi (29) inductor operation (CCM)
DI=1
Additional voltage stress across
X=0.5(Vo+Vi)=100 V
the switch
D. Semiconductor Elements Filter inductor L=400 µH
The average, rms, and peak currents through the switch Output filter capacitor Co=100 µF/250 V
are given by (30), (31), and (32), respectively, while the Snubber capacitor CS=16 nF
maximum voltage stress is calculated from (33). Snubber resistor RS=156.6 
Snubber diode SB1100 by Fairchild Semiconductor
tc (max)  I  Active switch MOSFET IRFP460
I S  avg     K (30) Diode Ultrafast diode DTV32
Ts  2 
The waveforms in the snubber circuit are represented in
t  I 2  Fig. 9, which are in accordance with the theoretical analysis.
 c (max)   K  I L ( pk ) 
3 
I S  rms  (31) The snubber capacitor is charged to about the level voltage
Ts  (Vi +Vo)=200 V. On the other hand, the maximum dissipated
I S  pk   I L pk  (32) power in snubber circuit is 15 W, which is less than that
related to design specifications defined in Table II and
VS  max   Vo  Vi  X (33) correspond to a theoretical value of 16.2 W.
Fig. 10 shows the voltage across the switch at rated load
condition, whose maximum value is expected to be
VS(max)=Vo+Vi+X=300 V as stated in Table II. However, it can
be seen that VS(max)=260 V in the experimental results. It can
be stated that the snubber circuit operates adequately in order
to limit the voltage stress according to the maximum desired
ratings.
Considering that the current through the inductor does not
become null over the entire switching period, the converter
operates in CCM as stated in Table II since K=2.4. Besides,
the voltage across the main diode DM is presented in Fig. 11,
whose maximum value about 300 V.
Finally, the input voltage and output voltage waveforms
can be seen in Fig. 12, whose average values are nearly the Fig. 12. Input voltage (Ch 1 – 50 V/ div., 10 µs/div.) and output voltage (Ch
same as those specified in Table II. 2 – 50 V/ div., 10 µs/div.) (Po=200 W).

An optimized design procedure has also been developed

to determine the power stage elements, which is also
dependent on parameters tc and td. It is worth to mention that
the accurate specification of such elements results in
prominent advantages e.g. reliable operation of the converter,
reduced cost associated to the correct design of components,
and improved dynamic response regarding the output voltage
control.
REFERENCES
Fig. 9. Voltages across the snubber resistor (Ch 2 – 50 V/ div., 10 µs/div.) [1] M. R. Banaei and H. A. F. Bonab, "A Novel Structure for
and snubber capacitor (Ch 1 – 50 V/ div., 10 µs/div.) (Po=200 W).
Single-Switch Nonisolated Transformerless Buck-Boost
DC-DC Converter," IEEE Transactions on Industrial
Electronics, vol. 64, pp. 198-205, 2017.
[2] T. Sreekanth, N. Lakshminarasamma, and M. K. Mishra,
"A Single-Stage Grid-Connected High Gain Buck-Boost
Inverter With Maximum Power Point Tracking," IEEE
Transactions on Energy Conversion, vol. 32, pp. 330-
339, 2017.
[3] D. Kilani, M. Alhawari, B. Mohammad, H. Saleh, and M.
Ismail, "An Efficient Switched-Capacitor DC-DC Buck
Converter for Self-Powered Wearable Electronics," IEEE
Fig. 10. Voltage across the switch (Ch 1 – 50 V/ div., 10 µs/div.) and Transactions on Circuits and Systems I: Regular Papers,
current through the inductor (Ch 2 – 5 A/ div., 10 µs/div.) (Po=200 W). vol. 63, pp. 1557-1566, 2016.
[4] B. J. Saharia and B. K. Talukdar, "Theoretical study on
performance constraints of a DC-DC buck-boost
converter," in 2015 International Conference on Energy,
Power and Environment: Towards Sustainable Growth
(ICEPE), 2015, pp. 1-4.
[5] M. Zhu and F. L. Luo, "Series SEPIC implementing
voltage-lift technique for DC-DC power conversion," IET
Power Electronics, vol. 1, pp. 109-121, 2008.
[6] R. Haroun, A. Cid-Pastor, A. E. Aroudi, and L. Martínez-
Salamero, "Synthesis of Canonical Elements for Power
Fig. 11. Voltage across the main diode (Ch 1 – 50 V/ div., 10 µs/div.) and Processing in DC Distribution Systems Using Cascaded
current through the inductor (Ch 2 – 5 A/ div., 10 µs/div.) (Po=200 W). Converters and Sliding-Mode Control," IEEE
Transactions on Power Electronics, vol. 29, pp. 1366-
V. CONCLUSION 1381, 2014.
[7] K. M. Smith and K. M. Smedley, "A comparison of
This paper has presented an alternative approach for the voltage-mode soft-switching methods for PWM
calculation of the static gain in a dc-dc buck-boost converter converters," IEEE Transactions on Power Electronics,
based on the charging and discharging times of the inductor, vol. 12, pp. 376-386, 1997.
which are related to both the voltage gain and rated power [8] S. J. Finney, B. W. Williams, and T. C. Green, "RCD
defined in the design specifications. The analysis has shown snubber revisited," IEEE Transactions on Industry
that the same expression can be used for the calculation of Applications, vol. 32, pp. 155-160, 1996.
the static gain in any operation mode i.e. CCM, DCM, and [9] N. Mohan, T. M. Undeland, and W. P. Robbins, Power
CRM. Besides, the converter analysis can be based on the Electronics: Converters, Applications, and Design, 3rd
load and/or output voltage variations. ed.: Wiley & Sons, 2002.

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