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CD4066B
SCHS051G – NOVEMBER 1998 – REVISED JUNE 2017

CD4066B CMOS Quad Bilateral Switch

1 Features 3 Description
•
1 15-V Digital or ±7.5-V Peak-to-Peak Switching The CD4066B device is a quad bilateral switch
intended for the transmission or multiplexing of
• 125-Ω Typical On-State Resistance for analog or digital signals. It is pin-for-pin compatible
15-V Operation with the CD4016B device, but exhibits a much lower
• Switch On-State Resistance Matched to Within on-state resistance. In addition, the on-state
5 Ω Over 15-V Signal-Input Range resistance is relatively constant over the full signal-
• On-State Resistance Flat Over Full input range.
Peak-to-Peak Signal Range The CD4066B device consists of four bilateral
• High ON/OFF Output-Voltage Ratio: switches, each with independent controls. Both the p
80 dB Typical at fis = 10 kHz, RL = 1 kΩ and the n devices in a given switch are biased on or
off simultaneously by the control signal. As shown in
• High Degree of Linearity: <0.5% Distortion Typical Figure 17, the well of the n-channel device on each
at fis = 1 kHz, Vis = 5 Vp-p switch is tied to either the input (when the switch is
VDD – VSS ≥ 10 V, RL = 10 kΩ on) or to VSS (when the switch is off). This
• Extremely Low Off-State Switch Leakage, configuration eliminates the variation of the switch-
Resulting in Very Low Offset Current and High transistor threshold voltage with input signal and,
Effective Off-State Resistance: 10 pA Typical at thus, keeps the on-state resistance low over the full
VDD – VSS = 10 V, TA = 25°C operating-signal range.
• Extremely High Control Input Impedance The advantages over single-channel switches include
(Control Circuit Isolated From Signal Circuit): peak input-signal voltage swings equal to the full
1012 Ω Typical supply voltage and more constant on-state
impedance over the input-signal range. However, for
• Low Crosstalk Between Switches: –50 dB Typical
sample-and-hold applications, the CD4016B device is
at fis = 8 MHz, RL = 1 kΩ recommended.
• Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal Transients Device Information(1)
• Frequency Response, PART NUMBER PACKAGE BODY SIZE (NOM)
Switch On = 40 MHz Typical PDIP (14) 19.30 mm × 6.35 mm
• 100% Tested for Quiescent Current at 20 V CDIP (14) 19.50 mm × 6.92 mm
• 5-V, 10-V, and 15-V Parametric Ratings CD4066B SOIC (14) 8.65 mm × 3.91 mm
SOP (14) 10.30 mm × 5.30 mm
2 Applications TSSOP (14) 5.00 mm × 4.40 mm
• Analog Signal Switching/Multiplexing: Signal (1) For all available packages, see the orderable addendum at
Gating, Modulators, Squelch Controls, the end of the datasheet.
Demodulators, Choppers, Commutating Switches
Bidirectional Signal Transmission Via Digital
• Digital Signal Switching/Multiplexing Control Logic
• Transmission-Gate Logic Implementation Switch

Control CMOS Protection Network

• Analog-to-Digital and Digital-to-Analog In
Vis
Conversions VDD

• Digital Control of Frequency, Impedance, Phase, p n

and Analog-Signal Gain p
Out
n Vos VSS

Control n
VC (1)
VSS

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4066B
SCHS051G – NOVEMBER 1998 – REVISED JUNE 2017 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 14
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 14
3 Description ............................................................. 1 9 Application and Implementation ........................ 15
4 Revision History..................................................... 2 9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 17
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 17
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 17
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 17
6.4 Thermal Information .................................................. 4 12 Device and Documentation Support ................. 18
6.5 Electrical Characteristics........................................... 5 12.1 Receiving Notification of Documentation Updates 18
6.6 Switching Characteristics .......................................... 8 12.2 Community Resources.......................................... 18
6.7 Typical Characteristics .............................................. 9 12.3 Trademarks ........................................................... 18
7 Parameter Measurement Information ................ 10 12.4 Electrostatic Discharge Caution ............................ 18
12.5 Glossary ................................................................ 18
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 14
Information ........................................................... 18

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (March 2017) to Revision G Page

• Changed From: VSS To: Hi-Z in the SIG OUT/IN column of Table 1 .................................................................................. 14

Changes from Revision E (September 2016) to Revision F Page

• Corrected the ron VDD = 10 V values in the Electrical Characteristics table. .......................................................................... 7
• Corrected the y axis scale in Figure 6 ................................................................................................................................... 9

Changes from Revision D (September 2003) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Deleted Ordering Information table, see POA at the end of the data sheet........................................................................... 1
• Changed values in the Thermal Information table to align with JEDEC standards ............................................................... 4

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5 Pin Configuration and Functions

N, J, D, NS, or PW Packages
14-Pin PDIP, CDIP, SOIC, SO, or TSSOP
Top View

SIG A IN/OUT 1 14 VDD

SIG A OUT/IN 2 13 CONTROL A
SIG B OUT/IN 3 12 CONTROL D
SIG B IN/OUT 4 11 SIG D IN/OUT
CONTROL B 5 10 SIG D OUT/IN
CONTROL C 6 9 SIG C OUT/IN
VSS 7 8 SIG C IN/OUT

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 SIG A IN/OUT I/O Input/Output for Switch A
2 SIG A OUT/IN I/O Output/Input for Switch A
3 SIG B OUT/IN I/O Output/Input for Switch B
4 SIG B IN/OUT I/O Input/Output for Switch B
5 CONTROL B I Control pin for Switch B
6 CONTROL C I Control pin for Switch C
7 VSS — Low Voltage Power Pin
8 SIG C IN/OUT I/O Input/Output for Switch C
9 SIG C OUT/IN I/O Output/Input for Switch C
10 SIG D OUT/IN I/O Output/Input for Switch D
11 SIG D IN/OUT I/O Input/Output for Switch D
12 CONTROL D I Control Pin for D
13 CONTROL A I Control Pin for A
14 VDD — Power Pin

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD DC supply-voltage Voltages referenced to VSS pin –0.5 20 V
Vis Input voltage All inputs –0.5 VDD + 0.5 V
IIN DC input current Any one input ±10 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
±500
pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-
±1500
C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage 3 18 V
TA Operating free-air temperature –55 125 °C

6.4 Thermal Information

CD4066B
(1) N D NS PW
THERMAL METRIC UNIT
(PDIP) (SOIC) (SO) (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 53.7 89.5 88.2 119.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 41.0 49.7 46.1 48.2 °C/W
RθJB Junction-to-board thermal resistance 33.6 43.8 47.0 61.2 °C/W
ψJT Junction-to-top characterization parameter 25.8 17.4 16.3 5.5 °C/W
ψJB Junction-to-board characterization parameter 33.5 43.5 46.6 60.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5 V
0.4 V
Vis = 0 V
VDD = 5 V
4.6 V
Vis = 5 V
VDD = 10 V
0.5 V
Vis = 0 V
Vos Switch output voltage
VDD = 10 V
9.5 V
Vis = 10 V
VDD = 15 V
1.5 V
Vis = 0 V
VDD = 15 V
13.5 V
Vis = 15 V
VDD = 5 V 15
On-state resistance
Δron difference between any RL = 10 kΩ, VC = VDD VDD = 10 V 10 Ω
two switches
VDD = 15 V 5
VC = VDD = 5 V, VSS = –5 V,
THD Total harmonic distortion Vis(p-p) = 5 V (sine wave centered on 0 V), 0.4%
RL = 10 kΩ, fis = 1-kHz sine wave
–3-dB cutoff frequency VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V
40 MHz
(switch on) (sine wave centered on 0 V), RL = 1 kΩ
–50-dB feedthrough VC = VSS = –5 V, Vis(p-p) = 5 V
1 MHz
frequency (switch off) (sine wave centered on 0 V), RL = 1 kΩ
VC(A) = VDD = 5 V,
–50-dB crosstalk VC(B) = VSS = –5 V,
8 MHz
frequency Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
Cis Input capacitance VDD = 5 V, VC = VSS = –5 V 8 pF
Cos Output capacitance VDD = 5 V, VC = VSS = –5 V 8 pF
Cios Feedthrough VDD = 5 V, VC = VSS = –5 V 0.5 pF
VDD = 5 V 3.5
VIHC Control input, high voltage See Figure 7 VDD = 10 V 7 V
VDD = 15 V 11
Crosstalk VC = 10 V (square wave),
(control input to signal tr, tf = 20 ns, RL = 10 kΩ 50 mV
output) VDD = 10 V
VDD = 5 V 35 70
Turnon and turnoff VIN = VDD, tr, tf = 20 ns,
VDD = 10 V 20 40 ns
propagation delay CL = 50 pF, RL = 1 kΩ
VDD = 15 V 15 30
Vis = VDD, VSS = GND, VDD = 5 V 6
RL = 1 kΩ to GND,
VDD = 10 V 9
Maximum control input CL = 50 pF,
MHz
repetition rate VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns, VDD = 15 V 9.5
Vos = 1/2 Vos at 1 kHz
CI Input capacitance 5 7.5 pF

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = –55°C 0.64
TA = –40°C 0.61
VDD = 5 V
TA = 25°C 0.51 mA
Vis = 0 V
TA = 85°C 0.42
TA = 125°C 0.36
–0.6
TA = –55°C
4
–0.6
TA = –40°C
1
VDD = 5 V
TA = 25°C –0.51 mA
Vis = 5 V
–0.4
TA = 85°C
2
–0.3
TA = 125°C
6
TA = –55°C 1.6
TA = –40°C 1.5
VDD = 10 V
TA = 25°C 1.3 mA
Vis = 0 V
Iis Switch input current TA = 85°C 1.1
TA = 125°C 0.9
TA = –55°C –1.6
TA = –40°C –1.5
VDD = 10 V
TA = 25°C –1.3 mA
Vis = 10 V
TA = 85°C –1.1
TA = 125°C –0.9
TA = –55°C 4.2
TA = –40°C 4
VDD = 15 V
TA = 25°C 3.4 mA
Vis = 0 V
TA = 85°C 2.8
TA = 125°C 2.4
TA = –55°C –4.2
TA = –40°C –4
VDD = 15 V
TA = 25°C –3.4 mA
Vis = 15 V
TA = 85°C –2.8
TA = 125°C –2.4

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = –55°C 0.25
TA = –40°C 0.25
VIN = 0 to 5 V
TA = 25°C 0.01 0.25 µA
VDD = 5 V
TA = 85°C 7.5
TA = 125°C 7.5
TA = –55°C 0.5
TA = –40°C 0.5
VIN = 0 to 10 V
TA = 25°C 0.01 0.5 µA
VDD = 10 V
TA = 85°C 15
TA = 125°C 15
IDD Quiescent device current
TA = –55°C 1
TA = –40°C 1
VIN = 0 to 15 V
TA = 25°C 0.01 1 µA
VDD = 15 V
TA = 85°C 30
TA = 125°C 30
TA = –55°C 5
TA = –40°C 5
VIN = 0 to 20 V
TA = 25°C 0.02 5 µA
VDD = 20 V
TA = 85°C 150
TA = 125°C 150
TA = –55°C 800
TA = –40°C 850
VDD = 5 V TA = 25°C 470 1050
TA = 85°C 1200
TA = 125°C 1300
TA = –55°C 310
V - V SS ) TA = –40°C 330
to ( DD
ron On-state resistance (max) VC = VDD,2 VDD = 10 V TA = 25°C 180 400 Ω
RL = 10 kΩ returned Vis = VSS TA = 85°C 500
to VDD
TA = 125°C 500
TA = –55°C 200
TA = –40°C 210
VDD = 15 V TA = 25°C 125 240
TA = 85°C 300
TA = 125°C 320

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = –55°C 1
TA = –40°C 1
VDD = 5 V TA = 25°C 1
TA = 85°C 1
TA = 125°C 1
TA = –55°C 2

|Iis| < 10 µA, TA = –40°C 2

Control input, Vis = VSS, VOS = VDD, and
VILC VDD = 10 V TA = 25°C 2 V
low voltage (max)
Vis = VDD, VOS = VSS TA = 85°C 2
TA = 125°C 2
TA = –55°C 2
TA = –40°C 2
VDD = 15 V TA = 25°C 2
TA = 85°C 2
TA = 125°C 2
TA = –55°C ±0.1
TA = –40°C ±0.1
Vis ≤ VDD, VDD – VSS = 18 V,
–5
IIN Input current (max) VCC ≤ VDD – VSS TA = 25°C ±10 ±0.1 µA
VDD = 18 V
TA = 85°C ±1
TA = 125°C ±1

6.6 Switching Characteristics

TA = 25°C
PARAMETER FROM TO TEST CONDITIONS VCC MIN TYP MAX UNIT
5V 20 40
VIN = VDD, tr, tf = 20 ns,
tpd Signal input Signal output 10 V 10 20 ns
CL = 50 pF, RL = 1 kΩ
15 V 7 15
5V 35 70
VIN = VDD, tr, tf = 20 ns,
tplh Signal input Signal output 10 V 20 40 ns
CL = 50 pF, RL = 1 kΩ
15 V 15 30
5V 35 70
VIN = VDD, tr, tf = 20 ns,
tphl Signal input Signal output 10 V 20 40 ns
CL = 50 pF, RL = 1 kΩ
15 V 15 30

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6.7 Typical Characteristics

600 Supply Voltage (VDD − VSS) = 5 V

r − Channel On-State Resistance − Ω

300

r − Channel On-State Resistance − Ω

Supply Voltage (VDD − VSS) = 10 V
TA = 125°C
500 250 TA = 125°C

400 200
+25°C
300 150
+25°C
−55°C
200 100
−55°C
100 50
on

0 0

on
−4 −3 −2 −1 0 1 2 3 4
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Vis − Input Signal Voltage − V Vis − Input Signal Voltage − V
92CS-27326RI 92CS-27327RI

Figure 1. Typical ON-State Resistance vs Input Signal Figure 2. Typical ON-State Resistance vs Input Signal
Voltage (All Types) Voltage (All Types)
Supply Voltage (VDD − VSS) = 15 V TA = 125°C

r − Channel On-State Resistance − Ω

r − Channel On-State Resistance − Ω

300 600

250 500 Supply Voltage (VDD − VSS) = 5 V

200 400
TA = 125°C
150 300

100 +25°C 200

−55°C 10 V
50 100 −15 V

0 0
on
on

−10 −7.5 −5 −2.5 0 2.5 5 7.5 10 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10

Vis − Input Signal Voltage − V Vis − Input Signal Voltage − V

92CS-27329RI 92CS-27330RI

Figure 3. Typical ON-State Resistance vs Input Signal Figure 4. Typical ON-State Resistance vs Input Signal
Voltage (All Types) Voltage (All Types)
104
6 TA = 25°C
3
PD − Power Dissipation Per Package − µ W

2 2
Supply Voltage
103 (VDD) = 15 V
VO − Output Voltage − V

8
1 6
10 V
4

0 2
VDD
VDD
5V 14
VC = VDD
5
Vos
102
CD4066B 8 6
−1 Vis 1 of 4 6 CD4066B
Switches 12
RL 4
13
VSS
−2 2 7
All unused terminals are VSS
connected to VSS
10
−3 10 2 4 6
102 2 4 6
103
−3 −2 −1 0 1 2 3 4
VI − Input Voltage − V f − Switching Frequency − kHz

92CS-30919

Figure 6. Power Dissipation per Package vs Switching

Figure 5. Typical ON Characteristics for 1 of 4 Channels Frequency

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7 Parameter Measurement Information

I is CD4066B
V is V os
1 of 4 Switches

|V is í V os |
r on =
|I is |

Copyright © 2016, Texas Instruments Incorporated

Figure 7. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification

Keithley
VDD 160 Digital
Multimeter

TG
10 kΩ 1-kΩ
On
Range Y
H. P.
VSS X-Y
Moseley
Plotter 7030A

92CS-22716

Figure 8. Channel On-State Resistance Measurement Circuit

Cios

VC = −5 V VDD = 5 V

CD4066B
1 of 4
Switches

Cis Cos
VSS = −5 V

92CS-30921
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.

Figure 9. Typical On Characteristics for One of Four Channels

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Parameter Measurement Information (continued)

VDD
VC = VSS
Vos
CD4066B
Vis = VDD
1 of 4
Switches I

VSS
92CS-30922
All unused terminals are connected to VSS.
Figure 10. Off-Switch Input or Output Leakage

VDD
VC = VDD
Vos
Vis CD4066B
1 of 4
Switches
200 kΩ
VSS 50 pF
VDD
tr = tf = 20 ns
92CS-30923
All unused terminals are connected to VSS.

Figure 11. Propagation Delay Time Signal Input

(Vis) to Signal Output (Vos)

+10 V VC VDD

tr = tf = 20 ns Vis Vos
CD4066B
1 of 4
1 kΩ Switches 10 kΩ
VSS

92CS-30924
All unused terminals are connected to VSS.
Figure 12. Crosstalk-Control Input to Signal Output

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Parameter Measurement Information (continued)

VDD VDD
VC=VDD
t r = t f = 20 ns
Vos
VDD CD4066B
1 of 4
Switches
1 kŸ
VSS 50 pF

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All unused pins are connected to VSS.
Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).

Figure 13. Propagation Delay, tPLH, tPHL Control-Signal Output

tr tf

VC 10 V
90%
10% 50%
0V
Repetition
Rate

tr = t f = 20 ns
V OS at1kHz
Vos V
OS 2

VDD = 10 V
VC V at1kHz
V OS
OS 2
Vis = 10 V CD4066B
1 of 4
Switches
50 pF 1 kŸ
VSS

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All unused pins are connected to VSS.

Figure 14. Maximum Allowable Control-Input Repetition Rate

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Parameter Measurement Information (continued)

VDD

Inputs

VDD

VSS

VSS 92CS-27555

Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.

Figure 15. Input Leakage-Current Test Circuit

10 2 3 7 9 12
10 2 3 7 9 12 Clock
Clock 14 PE J1 J2 J3 J4 J5
14 PE J 1 J 2 J3 J 4 J5 External
Reset 15 CD4018B
15 CD4018B 13 Reset
1 Q1 Q2
1 Q1 Q2
5 4
1 1/4 CD4066B 2
5 4

13 12 9 8 6 5 2 1
1
3
2 7 6
1/3 CD4049B
3 2 5
4 10 CD4001B
9
CD4001B

1/3 CD4049B 6
11 10 4 3
5 4 8
10
9
6 Signal
6 5 13 12 5 11
12 Outputs
11
13 Channel 1
2 LPF
Signal 12 11 12
Inputs 10 NŸ
Channel 1 1/6 CD4049B
1 2
1
Channel 2 5 Channel 2
4 CD4066B 3 3 LPF
4
Channel 3
8 9 10 NŸ
Channel 4 4 1/4 CD4066B CD4066B
3 8
11 10
11 Channel 3
9 LPF
10 kŸ
10 NŸ

Channel 4
10 LPF
10 NŸ

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Figure 16. Four-Channel PAM Multiplex System Diagram

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8 Detailed Description

8.1 Overview
CD4066B has four independent digitally controlled analog switches with a bias voltage of VSS to allow for
different voltage levels to be used for low output. Both the p and the n devices in a given switch are biased on or
off simultaneously by the control signal. As shown in Figure 17, the well of the n-channel device on each switch
is tied to either the input (when the switch is on) or to VSS (when the switch is off). Thus when the control of the
device is low, the output of the switch goes to VSS while when the control is high the output of the device goes to
VDD.

8.2 Functional Block Diagram

Switch

Control CMOS Protection Network

In
Vis
VDD

p n

p
Out
n Vos VSS

Control n
VC (1)
VSS

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(1) All control inputs are protected by the CMOS protection network.
(2) All p substrates are connected to VDD.
(3) Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS.
(4) Signal-level range: VSS ≤ Vis ≤ VDD.

Figure 17. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

8.3 Feature Description

Each switch has different control pins, which allows for more options for the outputs. Bias Voltage allows the
device to output a voltage other than 0 V when the device control is low. The CD4066B has a large absolute
maximum voltage for VDD of 20 V.

8.4 Device Functional Modes

Table 1 lists the functions of this device.

Table 1. Function Table

INPUTS OUTPUT
SIG IN/OUT CONTROL SIG OUT/IN
H H H
L H L
X L Hi-Z

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B device bilateral switches). This provision
avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the
CD4066B device.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To
avoid drawing VDD current when switch current flows into pins 1, 4, 8, or 11, the voltage drop across the
bidirectional switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current flows through RL if the switch current flows into pins 2, 3, 9, or 10.

9.2 Typical Application

5V
Analog Inputs (±5 V)
0
−5 V
VDD = 5 V
VDD = 5 V

CD4066B
5V SWA
0 SWB
IN CD4054B
SWC

SWD
Digital
Control
Inputs
VSS = 0 V
VEE = −5 V VSS = −5 V
Analog Outputs (±5 V)

92CS-30927

Figure 18. Bidirectional Signal Transmission Through Digital Control Logic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive
currents in excess of maximum limits. The high drive also creates fast edges into light loads, so consider routing
and load conditions to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
2. Recommended Output Conditions:
– Load currents should not exceed ±10 mA.

Copyright © 1998–2017, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: CD4066B
CD4066B
SCHS051G – NOVEMBER 1998 – REVISED JUNE 2017 www.ti.com

Typical Application (continued)

9.2.3 Application Curve
104
6 TA = 25°C

PD − Power Dissipation Per Package − µ W

4

2
Supply Voltage
103 (VDD) = 15 V
8
6
10 V
4

2
VDD
5V 14
5
102
8 6
6 CD4066B
12
4
13

2 7
VSS
10
2 4 6 2 4 6
10 102 103

f − Switching Frequency − kHz

Figure 19. Power Dissipation vs. Switching Frequency

16 Submit Documentation Feedback Copyright © 1998–2017, Texas Instruments Incorporated

Product Folder Links: CD4066B

 CD4066B
www.ti.com SCHS051G – NOVEMBER 1998 – REVISED JUNE 2017

10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in Recommended
Operating Conditions.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1-µF is recommended; if there are multiple VCC pins, then 0.01-µF or 0.022-µF is recommended for
each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. A
0.1-µF and a 1-µF are commonly used in parallel. The bypass capacitor should be installed as close to the power
pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from
floating. The logic level that should be applied to any particular unused input depends on the function of the
device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. It is
generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin,
it disables the output section of the part when asserted. This does not disable the input section of the I/Os, so
they cannot float when disabled.

11.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 20. Diagram for Unused Inputs

Copyright © 1998–2017, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: CD4066B
CD4066B
SCHS051G – NOVEMBER 1998 – REVISED JUNE 2017 www.ti.com

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Documentation Feedback Copyright © 1998–2017, Texas Instruments Incorporated

Product Folder Links: CD4066B

 PACKAGE OPTION ADDENDUM

www.ti.com 26-Sep-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD4066BE ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU | CU SN N / A for Pkg Type -55 to 125 CD4066BE
& no Sb/Br)
CD4066BEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE
(RoHS)
CD4066BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF

CD4066BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF3A

CD4066BM ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BM96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BMT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BNS ACTIVE SO NS 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM CD4066B
& no Sb/Br)
CD4066BNSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B
& no Sb/Br)
CD4066BPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
JM38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05852BCA
M38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05852BCA

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Sep-2018

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :

• Catalog: CD4066B
• Automotive: CD4066B-Q1, CD4066B-Q1
• Military: CD4066B-MIL

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Sep-2018

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jun-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4066BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4066BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4066BPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jun-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4066BM96 SOIC D 14 2500 333.2 345.9 28.6
CD4066BM96 SOIC D 14 2500 367.0 367.0 38.0
CD4066BM96 SOIC D 14 2500 364.0 364.0 27.0
CD4066BM96G4 SOIC D 14 2500 333.2 345.9 28.6
CD4066BM96G4 SOIC D 14 2500 367.0 367.0 38.0
CD4066BMT SOIC D 14 250 367.0 367.0 38.0
CD4066BNSR SO NS 14 2000 367.0 367.0 38.0
CD4066BPWR TSSOP PW 14 2000 367.0 367.0 35.0
CD4066BPWR TSSOP PW 14 2000 364.0 364.0 27.0
CD4066BPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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